LPC13xx Peripheral Coverage

Overall: 721/1731 fields covered

ADC

0x4001c000: Analog-to-Digital Converter (ADC)

22/83 fields covered. Toggle Registers

Offset	Name	31	30	29	27	26	23	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR	RESERVED			EDGE	START	RESERVED	CLKS	BURST	CLKDIV								SEL
0x4	GDR	DONE	OVERRUN	RESERVED		CHN	RESERVED			V_VREF										RESERVED
0xc	INTEN	RESERVED								RESERVED							ADGINTEN	ADINTEN7	ADINTEN6	ADINTEN5	ADINTEN4	ADINTEN3	ADINTEN2	ADINTEN1	ADINTEN0
0x10	DR[0]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x14	DR[1]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x18	DR[2]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x1c	DR[3]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x20	DR[4]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x24	DR[5]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x28	DR[6]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x2c	DR[7]	DONE	OVERRUN	RESERVED						V_VREF										RESERVED
0x30	STAT	RESERVED							ADINT	OVERRUN7	OVERRUN6	OVERRUN5	OVERRUN4	OVERRUN3	OVERRUN2	OVERRUN1	OVERRUN0	DONE7	DONE6	DONE5	DONE4	DONE3	DONE2	DONE1	DONE0

CR

A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur.

Offset: 0x0, reset: 0x00000000, access: read-write

4/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw				EDGE rw	START rw			RESERVED rw				CLKS rw			BURST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKDIV rw								SEL rw

Toggle Fields

SEL

Bits 0-7: Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)..

CLKDIV

Bits 8-15: The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable..

BURST

Bit 16: Burst select.

Allowed values:
0: SOFTWARE_CONTROLLED_: Software-controlled mode: Conversions are software-controlled and require 11 clocks.
1: HARDWARE_SCAN_MODE_: Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start.

CLKS

Bits 17-19: This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)..

Allowed values:
0x0: 11_CLOCKS: 11 clocks / 10 bits
0x1: 10_CLOCKS: 10 clocks / 9 bits
0x2: 9_CLOCKS: 9 clocks / 8 bits
0x3: 8_CLOCKS: 8 clocks / 7 bits
0x4: 7_CLOCKS: 7 clocks / 6 bits
0x5: 6_CLOCKS: 6 clocks / 5 bits
0x6: 5_CLOCKS: 5 clocks / 4 bits
0x7: 4_CLOCKS: 4 clocks / 3 bits

RESERVED

Bits 20-23: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

START

Bits 24-26: When the BURST bit is 0, these bits control whether and when an A/D conversion is started:.

Allowed values:
0x0: NO_START_THIS_VALUE: No start (this value should be used when clearing PDN to 0).
0x1: NOW: Start conversion now.
0x2: EDGEPIO0_2: Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0.
0x3: EDGEPIO1_5: Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0.
0x4: EDGECT32B0_MAT0: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0. Timer match function does not need to be selected on the device pin.
0x5: EDGECT32B1_MAT1: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1. Timer match function does not need to be selected on the device pin.
0x6: EDGECT16B0_MAT0: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0. Timer match function does not need to be selected on the device pin.
0x7: EDGECT16B0_MAT1: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1. Timer match function does not need to be selected on the device pin.

EDGE

Bit 27: This bit is significant only when the START field contains 010-111. In these cases:.

Allowed values:
0: RISING: Start conversion on a rising edge on the selected CAP/MAT signal.
1: FALLING: Start conversion on a falling edge on the selected CAP/MAT signal.

RESERVED

Bits 28-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

GDR

A/D Global Data Register. Contains the result of the most recent A/D conversion.

Offset: 0x4, reset: 0, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw			CHN rw			RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

Bits 6-15: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF..

RESERVED

Bits 16-23: Reserved..

CHN

Bits 24-26: These bits contain the channel from which the V_VREF bits were converted..

RESERVED

Bits 27-29: Reserved..

OVERRUN

Bit 30: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits..

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started..

INTEN

A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.

Offset: 0xc, reset: 0x00000100, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw							ADGINTEN rw	ADINTEN7 rw	ADINTEN6 rw	ADINTEN5 rw	ADINTEN4 rw	ADINTEN3 rw	ADINTEN2 rw	ADINTEN1 rw	ADINTEN0 rw

Toggle Fields

ADINTEN0

Bit 0: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN1

Bit 1: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN2

Bit 2: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN3

Bit 3: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN4

Bit 4: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN5

Bit 5: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN6

Bit 6: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADINTEN7

Bit 7: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc..

ADGINTEN

Bit 8: When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts..

RESERVED

Bits 9-31: Reserved..

DR[0]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x10, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

Bits 6-15: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF..

RESERVED

Bits 16-29: Reserved..

OVERRUN

Bit 30: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register..

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[1]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x14, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[2]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x18, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[3]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x1c, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[4]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x20, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[5]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x24, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[6]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x28, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

DR[7]

A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n

Offset: 0x2c, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DONE rw	OVERRUN rw	RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
V_VREF rw										RESERVED rw

Toggle Fields

RESERVED

Bits 0-5: Reserved..

V_VREF

RESERVED

Bits 16-29: Reserved..

OVERRUN

DONE

Bit 31: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read..

STAT

A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.

Offset: 0x30, reset: 0, access: read-only

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r															ADINT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVERRUN7 r	OVERRUN6 r	OVERRUN5 r	OVERRUN4 r	OVERRUN3 r	OVERRUN2 r	OVERRUN1 r	OVERRUN0 r	DONE7 r	DONE6 r	DONE5 r	DONE4 r	DONE3 r	DONE2 r	DONE1 r	DONE0 r

Toggle Fields

DONE0

Bit 0: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE1

Bit 1: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE2

Bit 2: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE3

Bit 3: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE4

Bit 4: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE5

Bit 5: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE6

Bit 6: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

DONE7

Bit 7: These bits mirror the DONE status flags that appear in the result register for each A/D channel..

OVERRUN0

Bit 8: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN1

Bit 9: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN2

Bit 10: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN3

Bit 11: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN4

Bit 12: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN5

Bit 13: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN6

Bit 14: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

OVERRUN7

Bit 15: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously..

ADINT

Bit 16: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register..

RESERVED

Bits 17-31: Reserved..

CT16B0

0x4000c000: 16-bit counter/timers (CT16B0/1)

27/59 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IR	RESERVED	RESERVED								CR0INT	MR3INT	MR2INT	MR1INT	MR0INT
0x4	TCR	RESERVED	RESERVED											CRESET	CEN
0x8	TC	RESERVED	TCVAL
0xc	PR	RESERVED	PRVAL
0x10	PC	RESERVED	PCVAL
0x14	MCR	RESERVED	RESERVED	MR3S	MR3R	MR3I	MR2S	MR2R	MR2I	MR1S	MR1R	MR1I	MR0S	MR0R	MR0I
0x18	MR[0]	RESERVED	MATCH
0x1c	MR[1]	RESERVED	MATCH
0x20	MR[2]	RESERVED	MATCH
0x24	MR[3]	RESERVED	MATCH
0x28	CCR	RESERVED	RESERVED										CAP0I	CAP0FE	CAP0RE
0x2c	CR0	RESERVED	CAP
0x3c	EMR	RESERVED	RESERVED	EMC3		EMC2		EMC1		EMC0		EM3	EM2	EM1	EM0
0x70	CTCR	RESERVED	RESERVED									CIS		CTM
0x74	PWMC	RESERVED	RESERVED									PWMEN3	PWMEN2	PWMEN1	PWMEN0

IR

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Offset: 0x0, reset: 0, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											CR0INT rw	MR3INT rw	MR2INT rw	MR1INT rw	MR0INT rw

Toggle Fields

MR0INT

Bit 0: Interrupt flag for match channel 0..

MR1INT

Bit 1: Interrupt flag for match channel 1..

MR2INT

Bit 2: Interrupt flag for match channel 2..

MR3INT

Bit 3: Interrupt flag for match channel 3..

CR0INT

Bit 4: Interrupt flag for capture channel 0 event..

RESERVED

Bits 5-31: Reserved.

TCR

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Offset: 0x4, reset: 0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														CRESET rw	CEN rw

Toggle Fields

CEN

Bit 0: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled..

CRESET

Bit 1: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero..

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TC

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

Offset: 0x8, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCVAL rw

Toggle Fields

TCVAL

Bits 0-15: Timer counter value..

RESERVED

Bits 16-31: Reserved..

PR

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

Offset: 0xc, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRVAL rw

Toggle Fields

PRVAL

Bits 0-15: Prescale max value..

RESERVED

Bits 16-31: Reserved..

PC

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

Offset: 0x10, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCVAL rw

Toggle Fields

PCVAL

Bits 0-15: Prescale counter value..

RESERVED

Bits 16-31: Reserved..

MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Offset: 0x14, reset: 0, access: read-write

12/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MR3S rw	MR3R rw	MR3I rw	MR2S rw	MR2R rw	MR2I rw	MR1S rw	MR1R rw	MR1I rw	MR0S rw	MR0R rw	MR0I rw

Toggle Fields

MR0I

Bit 0: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0R

Bit 1: Reset on MR0: the TC will be reset if MR0 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0S

Bit 2: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1I

Bit 3: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1R

Bit 4: Reset on MR1: the TC will be reset if MR1 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1S

Bit 5: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2I

Bit 6: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2R

Bit 7: Reset on MR2: the TC will be reset if MR2 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2S

Bit 8: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3I

Bit 9: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3R

Bit 10: Reset on MR3: the TC will be reset if MR3 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3S

Bit 11: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MR[0]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x18, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[1]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x1c, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[2]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x20, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[3]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x24, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

CCR

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Offset: 0x28, reset: 0, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw													CAP0I rw	CAP0FE rw	CAP0RE rw

Toggle Fields

CAP0RE

Bit 0: Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0FE

Bit 1: Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0I

Bit 2: Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CR0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.

Offset: 0x2c, reset: 0, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAP r

Toggle Fields

CAP

Bits 0-15: Timer counter capture value..

RESERVED

Bits 16-31: Reserved..

EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].

Offset: 0x3c, reset: 0, access: read-write

4/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				EMC3 rw		EMC2 rw		EMC1 rw		EMC0 rw		EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle Fields

EM0

Bit 0: External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM1

Bit 1: External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM2

Bit 2: External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM3

Bit 3: External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers..

EMC0

Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..

Allowed values:
0x0: DO_NOTHING_: Do Nothing.
0x1: CLEAR_THE_CORRESPOND: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).
0x2: SET_THE_CORRESPONDIN: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).
0x3: TOGGLE_THE_CORRESPON: Toggle the corresponding External Match bit/output.

EMC1

Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..

EMC2

Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..

EMC3

Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CTCR

Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Offset: 0x70, reset: 0, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												CIS rw		CTM rw

Toggle Fields

CTM

Bits 0-1: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)..

Allowed values:
0x0: TIMER_MODE_EVERY_RI: Timer Mode: every rising PCLK edge
0x1: RISING: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: FALLING: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: BOTHEDGES: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

CIS

Bits 2-3: Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000..

Allowed values:
0x0: CT16BN_CAP0: CT16Bn_CAP0

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].

Offset: 0x74, reset: 0, access: read-write

4/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												PWMEN3 rw	PWMEN2 rw	PWMEN1 rw	PWMEN0 rw

Toggle Fields

PWMEN0

Bit 0: PWM channel0 enable.

Allowed values:
0: EM0: CT16Bn_MAT0 is controlled by EM0.
1: PWM: PWM mode is enabled for CT16Bn_MAT0.

PWMEN1

Bit 1: PWM channel1 enable.

Allowed values:
0: EM1: CT16Bn_MAT1 is controlled by EM1.
1: PWM: PWM mode is enabled for CT16Bn_MAT1.

PWMEN2

Bit 2: PWM channel2 enable.

Allowed values:
0: EM2: Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1.
1: PWM: PWM mode is enabled for match channel 2 or pin CT16B0_MAT2.

PWMEN3

Bit 3: PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out..

Allowed values:
0: EM3: Match channel 3 match channel 3 is controlled by EM3.
1: PWM: PWM mode is enabled for match channel 3match channel 3.

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CT16B1

0x40010000: 16-bit counter/timers (CT16B0/1)

27/59 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IR	RESERVED	RESERVED								CR0INT	MR3INT	MR2INT	MR1INT	MR0INT
0x4	TCR	RESERVED	RESERVED											CRESET	CEN
0x8	TC	RESERVED	TCVAL
0xc	PR	RESERVED	PRVAL
0x10	PC	RESERVED	PCVAL
0x14	MCR	RESERVED	RESERVED	MR3S	MR3R	MR3I	MR2S	MR2R	MR2I	MR1S	MR1R	MR1I	MR0S	MR0R	MR0I
0x18	MR[0]	RESERVED	MATCH
0x1c	MR[1]	RESERVED	MATCH
0x20	MR[2]	RESERVED	MATCH
0x24	MR[3]	RESERVED	MATCH
0x28	CCR	RESERVED	RESERVED										CAP0I	CAP0FE	CAP0RE
0x2c	CR0	RESERVED	CAP
0x3c	EMR	RESERVED	RESERVED	EMC3		EMC2		EMC1		EMC0		EM3	EM2	EM1	EM0
0x70	CTCR	RESERVED	RESERVED									CIS		CTM
0x74	PWMC	RESERVED	RESERVED									PWMEN3	PWMEN2	PWMEN1	PWMEN0

IR

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Offset: 0x0, reset: 0, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											CR0INT rw	MR3INT rw	MR2INT rw	MR1INT rw	MR0INT rw

Toggle Fields

MR0INT

Bit 0: Interrupt flag for match channel 0..

MR1INT

Bit 1: Interrupt flag for match channel 1..

MR2INT

Bit 2: Interrupt flag for match channel 2..

MR3INT

Bit 3: Interrupt flag for match channel 3..

CR0INT

Bit 4: Interrupt flag for capture channel 0 event..

RESERVED

Bits 5-31: Reserved.

TCR

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Offset: 0x4, reset: 0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														CRESET rw	CEN rw

Toggle Fields

CEN

Bit 0: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled..

CRESET

Bit 1: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero..

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TC

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

Offset: 0x8, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCVAL rw

Toggle Fields

TCVAL

Bits 0-15: Timer counter value..

RESERVED

Bits 16-31: Reserved..

PR

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

Offset: 0xc, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRVAL rw

Toggle Fields

PRVAL

Bits 0-15: Prescale max value..

RESERVED

Bits 16-31: Reserved..

PC

Offset: 0x10, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCVAL rw

Toggle Fields

PCVAL

Bits 0-15: Prescale counter value..

RESERVED

Bits 16-31: Reserved..

MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Offset: 0x14, reset: 0, access: read-write

12/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MR3S rw	MR3R rw	MR3I rw	MR2S rw	MR2R rw	MR2I rw	MR1S rw	MR1R rw	MR1I rw	MR0S rw	MR0R rw	MR0I rw

Toggle Fields

MR0I

Bit 0: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0R

Bit 1: Reset on MR0: the TC will be reset if MR0 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0S

Bit 2: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1I

Bit 3: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1R

Bit 4: Reset on MR1: the TC will be reset if MR1 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1S

Bit 5: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2I

Bit 6: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2R

Bit 7: Reset on MR2: the TC will be reset if MR2 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2S

Bit 8: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3I

Bit 9: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3R

Bit 10: Reset on MR3: the TC will be reset if MR3 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3S

Bit 11: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MR[0]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x18, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[1]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x1c, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[2]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x20, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

MR[3]

Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Offset: 0x24, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-15: Timer counter match value..

RESERVED

Bits 16-31: Reserved..

CCR

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Offset: 0x28, reset: 0, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw													CAP0I rw	CAP0FE rw	CAP0RE rw

Toggle Fields

CAP0RE

Bit 0: Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0FE

Bit 1: Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0I

Bit 2: Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CR0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.

Offset: 0x2c, reset: 0, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAP r

Toggle Fields

CAP

Bits 0-15: Timer counter capture value..

RESERVED

Bits 16-31: Reserved..

EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].

Offset: 0x3c, reset: 0, access: read-write

4/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				EMC3 rw		EMC2 rw		EMC1 rw		EMC0 rw		EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle Fields

EM0

EM1

EM2

EM3

EMC0

Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..

EMC1

Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..

EMC2

Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..

EMC3

Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CTCR

Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Offset: 0x70, reset: 0, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												CIS rw		CTM rw

Toggle Fields

CTM

Bits 0-1: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)..

CIS

Allowed values:
0x0: CT16BN_CAP0: CT16Bn_CAP0

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].

Offset: 0x74, reset: 0, access: read-write

4/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												PWMEN3 rw	PWMEN2 rw	PWMEN1 rw	PWMEN0 rw

Toggle Fields

PWMEN0

Bit 0: PWM channel0 enable.

Allowed values:
0: EM0: CT16Bn_MAT0 is controlled by EM0.
1: PWM: PWM mode is enabled for CT16Bn_MAT0.

PWMEN1

Bit 1: PWM channel1 enable.

Allowed values:
0: EM1: CT16Bn_MAT1 is controlled by EM1.
1: PWM: PWM mode is enabled for CT16Bn_MAT1.

PWMEN2

Bit 2: PWM channel2 enable.

PWMEN3

Bit 3: PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out..

Allowed values:
0: EM3: Match channel 3 match channel 3 is controlled by EM3.
1: PWM: PWM mode is enabled for match channel 3match channel 3.

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CT32B0

0x40014000: 32-bit counter/timers (CT32B0/1)

26/51 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IR	RESERVED	RESERVED								CR0INT	MR3INT	MR2INT	MR1INT	MR0INT
0x4	TCR	RESERVED	RESERVED											CRES	CEN
0x8	TC	TCVAL	TCVAL
0xc	PR	PRVAL	PRVAL
0x10	PC	PCVAL	PCVAL
0x14	MCR	RESERVED	RESERVED	MR3S	MR3R	MR3I	MR2S	MR2R	MR2I	MR1S	MR1R	MR1I	MR0S	MR0R	MR0I
0x18	MR[0]	MATCH	MATCH
0x1c	MR[1]	MATCH	MATCH
0x20	MR[2]	MATCH	MATCH
0x24	MR[3]	MATCH	MATCH
0x28	CCR	RESERVED	RESERVED										CAP0I	CAP0FE	CAP0RE
0x2c	CR0	CAP	CAP
0x3c	EMR	RESERVED	RESERVED	EMC3		EMC2		EMC1		EMC0		EM3	EM2	EM1	EM0
0x70	CTCR	RESERVED	RESERVED									CIS		CTM
0x74	PWMC	RESERVED	RESERVED									PWMEN3	PWMEN2	PWMEN1	PWMEN0

IR

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Offset: 0x0, reset: 0, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											CR0INT rw	MR3INT rw	MR2INT rw	MR1INT rw	MR0INT rw

Toggle Fields

MR0INT

Bit 0: Interrupt flag for match channel 0..

MR1INT

Bit 1: Interrupt flag for match channel 1..

MR2INT

Bit 2: Interrupt flag for match channel 2..

MR3INT

Bit 3: Interrupt flag for match channel 3..

CR0INT

Bit 4: Interrupt flag for capture channel 0 event..

RESERVED

Bits 5-31: Reserved.

TCR

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Offset: 0x4, reset: 0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														CRES rw	CEN rw

Toggle Fields

CEN

Bit 0: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled..

CRES

Bit 1: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero..

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TC

Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCVAL rw

Toggle Fields

TCVAL

Bits 0-31: Timer counter value..

PR

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

Offset: 0xc, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRVAL rw

Toggle Fields

PRVAL

Bits 0-31: Prescale value..

PC

Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCVAL rw

Toggle Fields

PCVAL

Bits 0-31: Prescale counter value..

MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Offset: 0x14, reset: 0, access: read-write

12/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MR3S rw	MR3R rw	MR3I rw	MR2S rw	MR2R rw	MR2I rw	MR1S rw	MR1R rw	MR1I rw	MR0S rw	MR0R rw	MR0I rw

Toggle Fields

MR0I

Bit 0: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0R

Bit 1: Reset on MR0: the TC will be reset if MR0 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0S

Bit 2: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1I

Bit 3: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1R

Bit 4: Reset on MR1: the TC will be reset if MR1 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1S

Bit 5: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2I

Bit 6: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2R

Bit 7: Reset on MR2: the TC will be reset if MR2 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2S

Bit 8: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3I

Bit 9: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3R

Bit 10: Reset on MR3: the TC will be reset if MR3 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3S

Bit 11: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MR[0]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x18, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[1]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[2]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[3]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

CCR

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Offset: 0x28, reset: 0, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw													CAP0I rw	CAP0FE rw	CAP0RE rw

Toggle Fields

CAP0RE

Bit 0: Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0FE

Bit 1: Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0I

Bit 2: Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CR0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.

Offset: 0x2c, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAP r

Toggle Fields

CAP

Bits 0-31: Timer counter capture value..

EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].

Offset: 0x3c, reset: 0, access: read-write

4/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				EMC3 rw		EMC2 rw		EMC1 rw		EMC0 rw		EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle Fields

EM0

Bit 0: External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM1

Bit 1: External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM2

Bit 2: External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EM3

Bit 3: External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)..

EMC0

Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..

Allowed values:
0x0: DO_NOTHING_: Do Nothing.
0x1: CLEAR_THE_CORRESPOND: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).
0x2: SET_THE_CORRESPONDIN: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).
0x3: TOGGLE_THE_CORRESPON: Toggle the corresponding External Match bit/output.

EMC1

Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..

EMC2

Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..

EMC3

Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CTCR

Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Offset: 0x70, reset: 0, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												CIS rw		CTM rw

Toggle Fields

CTM

Bits 0-1: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge.

Allowed values:
0x0: TIMER_MODE_EVERY_RI: Timer Mode: every rising PCLK edge
0x1: RISING: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: FALLLING: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: BOTHEDGES: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

CIS

Bits 2-3: Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:.

Allowed values:
0x0: CT32BN_CAP0: CT32Bn_CAP0

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].

Offset: 0x74, reset: 0, access: read-write

4/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												PWMEN3 rw	PWMEN2 rw	PWMEN1 rw	PWMEN0 rw

Toggle Fields

PWMEN0

Bit 0: PWM channel 0 enable.

Allowed values:
0: EM0: CT32Bn_MAT0 is controlled by EM0.
1: PWM: PWM mode is enabled for CT32Bn_MAT0.

PWMEN1

Bit 1: PWM channel 1 enable.

Allowed values:
0: EM1: CT32Bn_MAT1 is controlled by EM1.
1: PWM: PWM mode is enabled for CT32Bn_MAT1.

PWMEN2

Bit 2: PWM channel 2 enable.

Allowed values:
0: EM2: CT32Bn_MAT2 is controlled by EM2.
1: PWM: PWM mode is enabled for CT32Bn_MAT2.

PWMEN3

Bit 3: PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle..

Allowed values:
0: EM3: CT32Bn_MAT3 is controlled by EM3.
1: PWM: PWM mode is enabled for CT32Bn_MAT3.

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CT32B1

0x40018000: 32-bit counter/timers (CT32B0/1)

26/51 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IR	RESERVED	RESERVED								CR0INT	MR3INT	MR2INT	MR1INT	MR0INT
0x4	TCR	RESERVED	RESERVED											CRES	CEN
0x8	TC	TCVAL	TCVAL
0xc	PR	PRVAL	PRVAL
0x10	PC	PCVAL	PCVAL
0x14	MCR	RESERVED	RESERVED	MR3S	MR3R	MR3I	MR2S	MR2R	MR2I	MR1S	MR1R	MR1I	MR0S	MR0R	MR0I
0x18	MR[0]	MATCH	MATCH
0x1c	MR[1]	MATCH	MATCH
0x20	MR[2]	MATCH	MATCH
0x24	MR[3]	MATCH	MATCH
0x28	CCR	RESERVED	RESERVED										CAP0I	CAP0FE	CAP0RE
0x2c	CR0	CAP	CAP
0x3c	EMR	RESERVED	RESERVED	EMC3		EMC2		EMC1		EMC0		EM3	EM2	EM1	EM0
0x70	CTCR	RESERVED	RESERVED									CIS		CTM
0x74	PWMC	RESERVED	RESERVED									PWMEN3	PWMEN2	PWMEN1	PWMEN0

IR

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Offset: 0x0, reset: 0, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											CR0INT rw	MR3INT rw	MR2INT rw	MR1INT rw	MR0INT rw

Toggle Fields

MR0INT

Bit 0: Interrupt flag for match channel 0..

MR1INT

Bit 1: Interrupt flag for match channel 1..

MR2INT

Bit 2: Interrupt flag for match channel 2..

MR3INT

Bit 3: Interrupt flag for match channel 3..

CR0INT

Bit 4: Interrupt flag for capture channel 0 event..

RESERVED

Bits 5-31: Reserved.

TCR

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Offset: 0x4, reset: 0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														CRES rw	CEN rw

Toggle Fields

CEN

Bit 0: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled..

CRES

Bit 1: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero..

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TC

Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCVAL rw

Toggle Fields

TCVAL

Bits 0-31: Timer counter value..

PR

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

Offset: 0xc, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRVAL rw

Toggle Fields

PRVAL

Bits 0-31: Prescale value..

PC

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCVAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCVAL rw

Toggle Fields

PCVAL

Bits 0-31: Prescale counter value..

MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Offset: 0x14, reset: 0, access: read-write

12/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MR3S rw	MR3R rw	MR3I rw	MR2S rw	MR2R rw	MR2I rw	MR1S rw	MR1R rw	MR1I rw	MR0S rw	MR0R rw	MR0I rw

Toggle Fields

MR0I

Bit 0: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0R

Bit 1: Reset on MR0: the TC will be reset if MR0 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR0S

Bit 2: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1I

Bit 3: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1R

Bit 4: Reset on MR1: the TC will be reset if MR1 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR1S

Bit 5: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2I

Bit 6: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2R

Bit 7: Reset on MR2: the TC will be reset if MR2 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR2S

Bit 8: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3I

Bit 9: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3R

Bit 10: Reset on MR3: the TC will be reset if MR3 matches it..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

MR3S

Bit 11: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MR[0]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x18, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[1]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[2]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

MR[3]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields

MATCH

Bits 0-31: Timer counter match value..

CCR

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Offset: 0x28, reset: 0, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw													CAP0I rw	CAP0FE rw	CAP0RE rw

Toggle Fields

CAP0RE

Bit 0: Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0FE

Bit 1: Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

CAP0I

Bit 2: Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt..

Allowed values:
1: ENABLED: Enabled
0: DISABLED: Disabled

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CR0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.

Offset: 0x2c, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAP r

Toggle Fields

CAP

Bits 0-31: Timer counter capture value..

EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].

Offset: 0x3c, reset: 0, access: read-write

4/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				EMC3 rw		EMC2 rw		EMC1 rw		EMC0 rw		EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle Fields

EM0

EM1

EM2

EM3

EMC0

Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..

EMC1

Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..

EMC2

Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..

EMC3

Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..

RESERVED

Bits 12-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CTCR

Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Offset: 0x70, reset: 0, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												CIS rw		CTM rw

Toggle Fields

CTM

Bits 0-1: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge.

Allowed values:
0x0: TIMER_MODE_EVERY_RI: Timer Mode: every rising PCLK edge
0x1: RISING: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: FALLLING: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: BOTHEDGES: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

CIS

Bits 2-3: Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:.

Allowed values:
0x0: CT32BN_CAP0: CT32Bn_CAP0

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].

Offset: 0x74, reset: 0, access: read-write

4/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												PWMEN3 rw	PWMEN2 rw	PWMEN1 rw	PWMEN0 rw

Toggle Fields

PWMEN0

Bit 0: PWM channel 0 enable.

Allowed values:
0: EM0: CT32Bn_MAT0 is controlled by EM0.
1: PWM: PWM mode is enabled for CT32Bn_MAT0.

PWMEN1

Bit 1: PWM channel 1 enable.

Allowed values:
0: EM1: CT32Bn_MAT1 is controlled by EM1.
1: PWM: PWM mode is enabled for CT32Bn_MAT1.

PWMEN2

Bit 2: PWM channel 2 enable.

Allowed values:
0: EM2: CT32Bn_MAT2 is controlled by EM2.
1: PWM: PWM mode is enabled for CT32Bn_MAT2.

PWMEN3

Bit 3: PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle..

Allowed values:
0: EM3: CT32Bn_MAT3 is controlled by EM3.
1: PWM: PWM mode is enabled for CT32Bn_MAT3.

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FMC

0x4003c000: Flash memory programming firmware

9/17 fields covered. Toggle Registers

Show register map

Offset	Name	31	17	16	15	2	1
0x10	FLASHCFG	RESERVED			RESERVED		FLASHTIM
0x20	FMSSTART	RESERVED		START	START
0x24	FMSSTOP	RESERVED	SIG_START	STOP	STOP
0x2c	FMSW0	SW0_31_0			SW0_31_0
0x30	FMSW1	SW1_63_32			SW1_63_32
0x34	FMSW2	SW2_95_64			SW2_95_64
0x38	FMSW3	SW3_127_96			SW3_127_96
0xfe0	FMSTAT	RESERVED			RESERVED	SIG_DONE	RESERVED
0xfe8	FMSTATCLR	RESERVED			RESERVED	SIG_DONE_CLR	RESERVED

FLASHCFG

Flash configuration register

Offset: 0x10, reset: 0, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														FLASHTIM rw

Toggle Fields

FLASHTIM

Bits 0-1: Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access..

Allowed values:
0x0: 1_SYSTEM_CLOCK_FLASH: 1 system clock flash access time (for system clock frequencies of up to 20 MHz).
0x1: 2_SYSTEM_CLOCKS_FLAS: 2 system clocks flash access time (for system clock frequencies of up to 40 MHz).
0x2: 3_SYSTEM_CLOCKS_FLAS: 3 system clocks flash access time (for system clock frequencies of up to 72 MHz).
0x3: RESERVED_: Reserved.

RESERVED

Bits 2-31: Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read..

FMSSTART

Signature start address register

Offset: 0x20, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw															START rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
START rw

Toggle Fields

START

Bits 0-16: Signature generation start address (corresponds to AHB byte address bits[20:4])..

RESERVED

Bits 17-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FMSSTOP

Signature stop-address register

Offset: 0x24, reset: 0, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw														SIG_START rw	STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
STOP rw

Toggle Fields

STOP

Bits 0-16: BIST stop address divided by 16 (corresponds to AHB byte address [20:4])..

SIG_START

Bit 17: Start control bit for signature generation..

Allowed values:
0: SIGNATURE_GENERATION: Signature generation is stopped
1: INITIATE_SIGNATURE_G: Initiate signature generation

RESERVED

Bits 18-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FMSW0

Word 0 [31:0]

Offset: 0x2c, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SW0_31_0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SW0_31_0 r

Toggle Fields

SW0_31_0

Bits 0-31: Word 0 of 128-bit signature (bits 31 to 0)..

FMSW1

Word 1 [63:32]

Offset: 0x30, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SW1_63_32 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SW1_63_32 r

Toggle Fields

SW1_63_32

Bits 0-31: Word 1 of 128-bit signature (bits 63 to 32)..

FMSW2

Word 2 [95:64]

Offset: 0x34, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SW2_95_64 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SW2_95_64 r

Toggle Fields

SW2_95_64

Bits 0-31: Word 2 of 128-bit signature (bits 95 to 64)..

FMSW3

Word 3 [127:96]

Offset: 0x38, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SW3_127_96 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SW3_127_96 r

Toggle Fields

SW3_127_96

Bits 0-31: Word 3 of 128-bit signature (bits 127 to 96)..

FMSTAT

Signature generation status register

Offset: 0xfe0, reset: 0, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r													SIG_DONE r	RESERVED r

Toggle Fields

RESERVED

Bits 0-1: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

SIG_DONE

Bit 2: When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag..

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FMSTATCLR

Signature generation status clear register

Offset: 0xfe8, reset: 0, access: write-only

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w													SIG_DONE_CLR w	RESERVED w

Toggle Fields

RESERVED

Bits 0-1: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

SIG_DONE_CLR

Bit 2: Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register..

RESERVED

Bits 3-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

GPIO0

0x50000000: General Purpose I/O (GPIO)

26/117 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x3ffc	DATA	RESERVED	RESERVED	DATA11	DATA10	DATA9	DATA8	DATA7	DATA6	DATA5	DATA4	DATA3	DATA2	DATA1	DATA0
0x8000	DIR	RESERVED	RESERVED	IO11	IO10	IO9	IO8	IO7	IO6	IO5	IO4	IO3	IO2	IO1	IO0
0x8004	IS	RESERVED	RESERVED	ISENSE11	ISENSE10	ISENSE9	ISENSE8	ISENSE7	ISENSE6	ISENSE5	ISENSE4	ISENSE3	ISENSE2	ISENSE1	ISENSE0
0x8008	IBE	RESERVED	RESERVED	IBE11	IBE10	IBE9	IBE8	IBE7	IBE6	IBE5	IBE4	IBE3	IBE2	IBE1	IBE0
0x800c	IEV	RESERVED	RESERVED	IEV11	IEV10	IEV9	IEV8	IEV7	IEV6	IEV5	IEV4	IEV3	IEV2	IEV1	IEV0
0x8010	IE	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x8014	RIS	RESERVED	RESERVED	RAWST11	RAWST10	RAWST9	RAWST8	RAWST7	RAWST6	RAWST5	RAWST4	RAWST3	RAWST2	RAWST1	RAWST0
0x8018	MIS	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x801c	IC	RESERVED	RESERVED	CLR11	CLR10	CLR9	CLR8	CLR7	CLR6	CLR5	CLR4	CLR3	CLR2	CLR1	CLR0

DATA

Port n data register for pins PIOn_0 to PIOn_11

Offset: 0x3ffc, reset: 0, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				DATA11 rw	DATA10 rw	DATA9 rw	DATA8 rw	DATA7 rw	DATA6 rw	DATA5 rw	DATA4 rw	DATA3 rw	DATA2 rw	DATA1 rw	DATA0 rw

Toggle Fields

DATA0

Bit 0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA1

Bit 1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA2

Bit 2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA3

Bit 3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA4

Bit 4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA5

Bit 5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA6

Bit 6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA7

Bit 7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA8

Bit 8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA9

Bit 9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA10

Bit 10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA11

Bit 11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

RESERVED

Bits 12-31: Reserved.

DIR

Data direction register for port n

Offset: 0x8000, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IO11 rw	IO10 rw	IO9 rw	IO8 rw	IO7 rw	IO6 rw	IO5 rw	IO4 rw	IO3 rw	IO2 rw	IO1 rw	IO0 rw

Toggle Fields

IO0

Bit 0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO1

Bit 1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO2

Bit 2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO3

Bit 3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO4

Bit 4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO5

Bit 5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO6

Bit 6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO7

Bit 7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO8

Bit 8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO9

Bit 9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO10

Bit 10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO11

Bit 11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

RESERVED

Bits 12-31: Reserved.

IS

Interrupt sense register for port n

Offset: 0x8004, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				ISENSE11 rw	ISENSE10 rw	ISENSE9 rw	ISENSE8 rw	ISENSE7 rw	ISENSE6 rw	ISENSE5 rw	ISENSE4 rw	ISENSE3 rw	ISENSE2 rw	ISENSE1 rw	ISENSE0 rw

Toggle Fields

ISENSE0

Bit 0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE1

Bit 1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE2

Bit 2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE3

Bit 3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE4

Bit 4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE5

Bit 5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE6

Bit 6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE7

Bit 7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE8

Bit 8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE9

Bit 9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE10

Bit 10: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE11

Bit 11: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

RESERVED

Bits 12-31: Reserved.

IBE

Interrupt both edges register for port n

Offset: 0x8008, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IBE11 rw	IBE10 rw	IBE9 rw	IBE8 rw	IBE7 rw	IBE6 rw	IBE5 rw	IBE4 rw	IBE3 rw	IBE2 rw	IBE1 rw	IBE0 rw

Toggle Fields

IBE0

Bit 0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE1

Bit 1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE2

Bit 2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE3

Bit 3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE4

Bit 4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE5

Bit 5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE6

Bit 6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE7

Bit 7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE8

Bit 8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE9

Bit 9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE10

Bit 10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE11

Bit 11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

RESERVED

Bits 12-31: Reserved.

IEV

Interrupt event register for port n

Offset: 0x800c, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IEV11 rw	IEV10 rw	IEV9 rw	IEV8 rw	IEV7 rw	IEV6 rw	IEV5 rw	IEV4 rw	IEV3 rw	IEV2 rw	IEV1 rw	IEV0 rw

Toggle Fields

IEV0

Bit 0: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV1

Bit 1: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV2

Bit 2: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV3

Bit 3: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV4

Bit 4: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV5

Bit 5: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV6

Bit 6: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV7

Bit 7: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV8

Bit 8: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV9

Bit 9: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV10

Bit 10: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

IEV11

Bit 11: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt..

RESERVED

Bits 12-31: Reserved.

IE

Interrupt mask register for port n

Offset: 0x8010, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MASK11 rw	MASK10 rw	MASK9 rw	MASK8 rw	MASK7 rw	MASK6 rw	MASK5 rw	MASK4 rw	MASK3 rw	MASK2 rw	MASK1 rw	MASK0 rw

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

RESERVED

Bits 12-31: Reserved.

RIS

Raw interrupt status register for port n

Offset: 0x8014, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				RAWST11 r	RAWST10 r	RAWST9 r	RAWST8 r	RAWST7 r	RAWST6 r	RAWST5 r	RAWST4 r	RAWST3 r	RAWST2 r	RAWST1 r	RAWST0 r

Toggle Fields

RAWST0

Bit 0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST1

Bit 1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST2

Bit 2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST3

Bit 3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST4

Bit 4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST5

Bit 5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST6

Bit 6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST7

Bit 7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST8

Bit 8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST9

Bit 9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST10

Bit 10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST11

Bit 11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RESERVED

Bits 12-31: Reserved.

MIS

Masked interrupt status register for port n

Offset: 0x8018, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				MASK11 r	MASK10 r	MASK9 r	MASK8 r	MASK7 r	MASK6 r	MASK5 r	MASK4 r	MASK3 r	MASK2 r	MASK1 r	MASK0 r

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

RESERVED

Bits 12-31: Reserved.

IC

Interrupt clear register for port n

Offset: 0x801c, reset: 0x00, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w				CLR11 w	CLR10 w	CLR9 w	CLR8 w	CLR7 w	CLR6 w	CLR5 w	CLR4 w	CLR3 w	CLR2 w	CLR1 w	CLR0 w

Toggle Fields

CLR0

Bit 0: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR1

Bit 1: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR2

Bit 2: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR3

Bit 3: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR4

Bit 4: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR5

Bit 5: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR6

Bit 6: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR7

Bit 7: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR8

Bit 8: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR9

Bit 9: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR10

Bit 10: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

CLR11

Bit 11: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x..

RESERVED

Bits 12-31: Reserved.

GPIO1

0x50010000: General Purpose I/O (GPIO)

26/117 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x3ffc	DATA	RESERVED	RESERVED	DATA11	DATA10	DATA9	DATA8	DATA7	DATA6	DATA5	DATA4	DATA3	DATA2	DATA1	DATA0
0x8000	DIR	RESERVED	RESERVED	IO11	IO10	IO9	IO8	IO7	IO6	IO5	IO4	IO3	IO2	IO1	IO0
0x8004	IS	RESERVED	RESERVED	ISENSE11	ISENSE10	ISENSE9	ISENSE8	ISENSE7	ISENSE6	ISENSE5	ISENSE4	ISENSE3	ISENSE2	ISENSE1	ISENSE0
0x8008	IBE	RESERVED	RESERVED	IBE11	IBE10	IBE9	IBE8	IBE7	IBE6	IBE5	IBE4	IBE3	IBE2	IBE1	IBE0
0x800c	IEV	RESERVED	RESERVED	IEV11	IEV10	IEV9	IEV8	IEV7	IEV6	IEV5	IEV4	IEV3	IEV2	IEV1	IEV0
0x8010	IE	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x8014	RIS	RESERVED	RESERVED	RAWST11	RAWST10	RAWST9	RAWST8	RAWST7	RAWST6	RAWST5	RAWST4	RAWST3	RAWST2	RAWST1	RAWST0
0x8018	MIS	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x801c	IC	RESERVED	RESERVED	CLR11	CLR10	CLR9	CLR8	CLR7	CLR6	CLR5	CLR4	CLR3	CLR2	CLR1	CLR0

DATA

Port n data register for pins PIOn_0 to PIOn_11

Offset: 0x3ffc, reset: 0, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				DATA11 rw	DATA10 rw	DATA9 rw	DATA8 rw	DATA7 rw	DATA6 rw	DATA5 rw	DATA4 rw	DATA3 rw	DATA2 rw	DATA1 rw	DATA0 rw

Toggle Fields

DATA0

Bit 0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA1

Bit 1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA2

Bit 2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA3

Bit 3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA4

Bit 4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA5

Bit 5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA6

Bit 6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA7

Bit 7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA8

Bit 8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA9

Bit 9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA10

Bit 10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA11

Bit 11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

RESERVED

Bits 12-31: Reserved.

DIR

Data direction register for port n

Offset: 0x8000, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IO11 rw	IO10 rw	IO9 rw	IO8 rw	IO7 rw	IO6 rw	IO5 rw	IO4 rw	IO3 rw	IO2 rw	IO1 rw	IO0 rw

Toggle Fields

IO0

Bit 0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO1

Bit 1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO2

Bit 2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO3

Bit 3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO4

Bit 4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO5

Bit 5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO6

Bit 6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO7

Bit 7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO8

Bit 8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO9

Bit 9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO10

Bit 10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO11

Bit 11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

RESERVED

Bits 12-31: Reserved.

IS

Interrupt sense register for port n

Offset: 0x8004, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				ISENSE11 rw	ISENSE10 rw	ISENSE9 rw	ISENSE8 rw	ISENSE7 rw	ISENSE6 rw	ISENSE5 rw	ISENSE4 rw	ISENSE3 rw	ISENSE2 rw	ISENSE1 rw	ISENSE0 rw

Toggle Fields

ISENSE0

Bit 0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE1

Bit 1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE2

Bit 2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE3

Bit 3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE4

Bit 4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE5

Bit 5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE6

Bit 6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE7

Bit 7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE8

Bit 8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE9

Bit 9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE10

ISENSE11

RESERVED

Bits 12-31: Reserved.

IBE

Interrupt both edges register for port n

Offset: 0x8008, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IBE11 rw	IBE10 rw	IBE9 rw	IBE8 rw	IBE7 rw	IBE6 rw	IBE5 rw	IBE4 rw	IBE3 rw	IBE2 rw	IBE1 rw	IBE0 rw

Toggle Fields

IBE0

Bit 0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE1

Bit 1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE2

Bit 2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE3

Bit 3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE4

Bit 4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE5

Bit 5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE6

Bit 6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE7

Bit 7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE8

Bit 8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE9

Bit 9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE10

Bit 10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE11

Bit 11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

RESERVED

Bits 12-31: Reserved.

IEV

Interrupt event register for port n

Offset: 0x800c, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IEV11 rw	IEV10 rw	IEV9 rw	IEV8 rw	IEV7 rw	IEV6 rw	IEV5 rw	IEV4 rw	IEV3 rw	IEV2 rw	IEV1 rw	IEV0 rw

Toggle Fields

IEV0

IEV1

IEV2

IEV3

IEV4

IEV5

IEV6

IEV7

IEV8

IEV9

IEV10

IEV11

RESERVED

Bits 12-31: Reserved.

IE

Interrupt mask register for port n

Offset: 0x8010, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MASK11 rw	MASK10 rw	MASK9 rw	MASK8 rw	MASK7 rw	MASK6 rw	MASK5 rw	MASK4 rw	MASK3 rw	MASK2 rw	MASK1 rw	MASK0 rw

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

RESERVED

Bits 12-31: Reserved.

RIS

Raw interrupt status register for port n

Offset: 0x8014, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				RAWST11 r	RAWST10 r	RAWST9 r	RAWST8 r	RAWST7 r	RAWST6 r	RAWST5 r	RAWST4 r	RAWST3 r	RAWST2 r	RAWST1 r	RAWST0 r

Toggle Fields

RAWST0

Bit 0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST1

Bit 1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST2

Bit 2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST3

Bit 3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST4

Bit 4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST5

Bit 5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST6

Bit 6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST7

Bit 7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST8

Bit 8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST9

Bit 9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST10

Bit 10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST11

Bit 11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RESERVED

Bits 12-31: Reserved.

MIS

Masked interrupt status register for port n

Offset: 0x8018, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				MASK11 r	MASK10 r	MASK9 r	MASK8 r	MASK7 r	MASK6 r	MASK5 r	MASK4 r	MASK3 r	MASK2 r	MASK1 r	MASK0 r

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

RESERVED

Bits 12-31: Reserved.

IC

Interrupt clear register for port n

Offset: 0x801c, reset: 0x00, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w				CLR11 w	CLR10 w	CLR9 w	CLR8 w	CLR7 w	CLR6 w	CLR5 w	CLR4 w	CLR3 w	CLR2 w	CLR1 w	CLR0 w

Toggle Fields

CLR0

CLR1

CLR2

CLR3

CLR4

CLR5

CLR6

CLR7

CLR8

CLR9

CLR10

CLR11

RESERVED

Bits 12-31: Reserved.

GPIO2

0x50020000: General Purpose I/O (GPIO)

26/117 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x3ffc	DATA	RESERVED	RESERVED	DATA11	DATA10	DATA9	DATA8	DATA7	DATA6	DATA5	DATA4	DATA3	DATA2	DATA1	DATA0
0x8000	DIR	RESERVED	RESERVED	IO11	IO10	IO9	IO8	IO7	IO6	IO5	IO4	IO3	IO2	IO1	IO0
0x8004	IS	RESERVED	RESERVED	ISENSE11	ISENSE10	ISENSE9	ISENSE8	ISENSE7	ISENSE6	ISENSE5	ISENSE4	ISENSE3	ISENSE2	ISENSE1	ISENSE0
0x8008	IBE	RESERVED	RESERVED	IBE11	IBE10	IBE9	IBE8	IBE7	IBE6	IBE5	IBE4	IBE3	IBE2	IBE1	IBE0
0x800c	IEV	RESERVED	RESERVED	IEV11	IEV10	IEV9	IEV8	IEV7	IEV6	IEV5	IEV4	IEV3	IEV2	IEV1	IEV0
0x8010	IE	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x8014	RIS	RESERVED	RESERVED	RAWST11	RAWST10	RAWST9	RAWST8	RAWST7	RAWST6	RAWST5	RAWST4	RAWST3	RAWST2	RAWST1	RAWST0
0x8018	MIS	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x801c	IC	RESERVED	RESERVED	CLR11	CLR10	CLR9	CLR8	CLR7	CLR6	CLR5	CLR4	CLR3	CLR2	CLR1	CLR0

DATA

Port n data register for pins PIOn_0 to PIOn_11

Offset: 0x3ffc, reset: 0, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				DATA11 rw	DATA10 rw	DATA9 rw	DATA8 rw	DATA7 rw	DATA6 rw	DATA5 rw	DATA4 rw	DATA3 rw	DATA2 rw	DATA1 rw	DATA0 rw

Toggle Fields

DATA0

Bit 0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA1

Bit 1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA2

Bit 2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA3

Bit 3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA4

Bit 4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA5

Bit 5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA6

Bit 6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA7

Bit 7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA8

Bit 8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA9

Bit 9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA10

Bit 10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA11

Bit 11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

RESERVED

Bits 12-31: Reserved.

DIR

Data direction register for port n

Offset: 0x8000, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IO11 rw	IO10 rw	IO9 rw	IO8 rw	IO7 rw	IO6 rw	IO5 rw	IO4 rw	IO3 rw	IO2 rw	IO1 rw	IO0 rw

Toggle Fields

IO0

Bit 0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO1

Bit 1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO2

Bit 2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO3

Bit 3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO4

Bit 4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO5

Bit 5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO6

Bit 6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO7

Bit 7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO8

Bit 8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO9

Bit 9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO10

Bit 10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO11

Bit 11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

RESERVED

Bits 12-31: Reserved.

IS

Interrupt sense register for port n

Offset: 0x8004, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				ISENSE11 rw	ISENSE10 rw	ISENSE9 rw	ISENSE8 rw	ISENSE7 rw	ISENSE6 rw	ISENSE5 rw	ISENSE4 rw	ISENSE3 rw	ISENSE2 rw	ISENSE1 rw	ISENSE0 rw

Toggle Fields

ISENSE0

Bit 0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE1

Bit 1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE2

Bit 2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE3

Bit 3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE4

Bit 4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE5

Bit 5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE6

Bit 6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE7

Bit 7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE8

Bit 8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE9

Bit 9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE10

ISENSE11

RESERVED

Bits 12-31: Reserved.

IBE

Interrupt both edges register for port n

Offset: 0x8008, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IBE11 rw	IBE10 rw	IBE9 rw	IBE8 rw	IBE7 rw	IBE6 rw	IBE5 rw	IBE4 rw	IBE3 rw	IBE2 rw	IBE1 rw	IBE0 rw

Toggle Fields

IBE0

Bit 0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE1

Bit 1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE2

Bit 2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE3

Bit 3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE4

Bit 4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE5

Bit 5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE6

Bit 6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE7

Bit 7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE8

Bit 8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE9

Bit 9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE10

Bit 10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE11

Bit 11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

RESERVED

Bits 12-31: Reserved.

IEV

Interrupt event register for port n

Offset: 0x800c, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IEV11 rw	IEV10 rw	IEV9 rw	IEV8 rw	IEV7 rw	IEV6 rw	IEV5 rw	IEV4 rw	IEV3 rw	IEV2 rw	IEV1 rw	IEV0 rw

Toggle Fields

IEV0

IEV1

IEV2

IEV3

IEV4

IEV5

IEV6

IEV7

IEV8

IEV9

IEV10

IEV11

RESERVED

Bits 12-31: Reserved.

IE

Interrupt mask register for port n

Offset: 0x8010, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MASK11 rw	MASK10 rw	MASK9 rw	MASK8 rw	MASK7 rw	MASK6 rw	MASK5 rw	MASK4 rw	MASK3 rw	MASK2 rw	MASK1 rw	MASK0 rw

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

RESERVED

Bits 12-31: Reserved.

RIS

Raw interrupt status register for port n

Offset: 0x8014, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				RAWST11 r	RAWST10 r	RAWST9 r	RAWST8 r	RAWST7 r	RAWST6 r	RAWST5 r	RAWST4 r	RAWST3 r	RAWST2 r	RAWST1 r	RAWST0 r

Toggle Fields

RAWST0

Bit 0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST1

Bit 1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST2

Bit 2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST3

Bit 3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST4

Bit 4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST5

Bit 5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST6

Bit 6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST7

Bit 7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST8

Bit 8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST9

Bit 9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST10

Bit 10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST11

Bit 11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RESERVED

Bits 12-31: Reserved.

MIS

Masked interrupt status register for port n

Offset: 0x8018, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				MASK11 r	MASK10 r	MASK9 r	MASK8 r	MASK7 r	MASK6 r	MASK5 r	MASK4 r	MASK3 r	MASK2 r	MASK1 r	MASK0 r

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

RESERVED

Bits 12-31: Reserved.

IC

Interrupt clear register for port n

Offset: 0x801c, reset: 0x00, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w				CLR11 w	CLR10 w	CLR9 w	CLR8 w	CLR7 w	CLR6 w	CLR5 w	CLR4 w	CLR3 w	CLR2 w	CLR1 w	CLR0 w

Toggle Fields

CLR0

CLR1

CLR2

CLR3

CLR4

CLR5

CLR6

CLR7

CLR8

CLR9

CLR10

CLR11

RESERVED

Bits 12-31: Reserved.

GPIO3

0x50030000: General Purpose I/O (GPIO)

26/117 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	6	5	4	3	2	1	0
0x3ffc	DATA	RESERVED	RESERVED	DATA11	DATA10	DATA9	DATA8	DATA7	DATA6	DATA5	DATA4	DATA3	DATA2	DATA1	DATA0
0x8000	DIR	RESERVED	RESERVED	IO11	IO10	IO9	IO8	IO7	IO6	IO5	IO4	IO3	IO2	IO1	IO0
0x8004	IS	RESERVED	RESERVED	ISENSE11	ISENSE10	ISENSE9	ISENSE8	ISENSE7	ISENSE6	ISENSE5	ISENSE4	ISENSE3	ISENSE2	ISENSE1	ISENSE0
0x8008	IBE	RESERVED	RESERVED	IBE11	IBE10	IBE9	IBE8	IBE7	IBE6	IBE5	IBE4	IBE3	IBE2	IBE1	IBE0
0x800c	IEV	RESERVED	RESERVED	IEV11	IEV10	IEV9	IEV8	IEV7	IEV6	IEV5	IEV4	IEV3	IEV2	IEV1	IEV0
0x8010	IE	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x8014	RIS	RESERVED	RESERVED	RAWST11	RAWST10	RAWST9	RAWST8	RAWST7	RAWST6	RAWST5	RAWST4	RAWST3	RAWST2	RAWST1	RAWST0
0x8018	MIS	RESERVED	RESERVED	MASK11	MASK10	MASK9	MASK8	MASK7	MASK6	MASK5	MASK4	MASK3	MASK2	MASK1	MASK0
0x801c	IC	RESERVED	RESERVED	CLR11	CLR10	CLR9	CLR8	CLR7	CLR6	CLR5	CLR4	CLR3	CLR2	CLR1	CLR0

DATA

Port n data register for pins PIOn_0 to PIOn_11

Offset: 0x3ffc, reset: 0, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				DATA11 rw	DATA10 rw	DATA9 rw	DATA8 rw	DATA7 rw	DATA6 rw	DATA5 rw	DATA4 rw	DATA3 rw	DATA2 rw	DATA1 rw	DATA0 rw

Toggle Fields

DATA0

Bit 0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA1

Bit 1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA2

Bit 2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA3

Bit 3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA4

Bit 4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA5

Bit 5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA6

Bit 6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA7

Bit 7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA8

Bit 8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA9

Bit 9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA10

Bit 10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

DATA11

Bit 11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0..

RESERVED

Bits 12-31: Reserved.

DIR

Data direction register for port n

Offset: 0x8000, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IO11 rw	IO10 rw	IO9 rw	IO8 rw	IO7 rw	IO6 rw	IO5 rw	IO4 rw	IO3 rw	IO2 rw	IO1 rw	IO0 rw

Toggle Fields

IO0

Bit 0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO1

Bit 1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO2

Bit 2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO3

Bit 3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO4

Bit 4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO5

Bit 5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO6

Bit 6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO7

Bit 7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO8

Bit 8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO9

Bit 9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO10

Bit 10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

IO11

Bit 11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output..

RESERVED

Bits 12-31: Reserved.

IS

Interrupt sense register for port n

Offset: 0x8004, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				ISENSE11 rw	ISENSE10 rw	ISENSE9 rw	ISENSE8 rw	ISENSE7 rw	ISENSE6 rw	ISENSE5 rw	ISENSE4 rw	ISENSE3 rw	ISENSE2 rw	ISENSE1 rw	ISENSE0 rw

Toggle Fields

ISENSE0

Bit 0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE1

Bit 1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE2

Bit 2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE3

Bit 3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE4

Bit 4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE5

Bit 5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE6

Bit 6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE7

Bit 7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE8

Bit 8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE9

Bit 9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive..

ISENSE10

ISENSE11

RESERVED

Bits 12-31: Reserved.

IBE

Interrupt both edges register for port n

Offset: 0x8008, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IBE11 rw	IBE10 rw	IBE9 rw	IBE8 rw	IBE7 rw	IBE6 rw	IBE5 rw	IBE4 rw	IBE3 rw	IBE2 rw	IBE1 rw	IBE0 rw

Toggle Fields

IBE0

Bit 0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE1

Bit 1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE2

Bit 2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE3

Bit 3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE4

Bit 4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE5

Bit 5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE6

Bit 6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE7

Bit 7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE8

Bit 8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE9

Bit 9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE10

Bit 10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

IBE11

Bit 11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt..

RESERVED

Bits 12-31: Reserved.

IEV

Interrupt event register for port n

Offset: 0x800c, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				IEV11 rw	IEV10 rw	IEV9 rw	IEV8 rw	IEV7 rw	IEV6 rw	IEV5 rw	IEV4 rw	IEV3 rw	IEV2 rw	IEV1 rw	IEV0 rw

Toggle Fields

IEV0

IEV1

IEV2

IEV3

IEV4

IEV5

IEV6

IEV7

IEV8

IEV9

IEV10

IEV11

RESERVED

Bits 12-31: Reserved.

IE

Interrupt mask register for port n

Offset: 0x8010, reset: 0x00, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				MASK11 rw	MASK10 rw	MASK9 rw	MASK8 rw	MASK7 rw	MASK6 rw	MASK5 rw	MASK4 rw	MASK3 rw	MASK2 rw	MASK1 rw	MASK0 rw

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked..

RESERVED

Bits 12-31: Reserved.

RIS

Raw interrupt status register for port n

Offset: 0x8014, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				RAWST11 r	RAWST10 r	RAWST9 r	RAWST8 r	RAWST7 r	RAWST6 r	RAWST5 r	RAWST4 r	RAWST3 r	RAWST2 r	RAWST1 r	RAWST0 r

Toggle Fields

RAWST0

Bit 0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST1

Bit 1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST2

Bit 2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST3

Bit 3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST4

Bit 4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST5

Bit 5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST6

Bit 6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST7

Bit 7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST8

Bit 8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST9

Bit 9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST10

Bit 10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RAWST11

Bit 11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x..

RESERVED

Bits 12-31: Reserved.

MIS

Masked interrupt status register for port n

Offset: 0x8018, reset: 0x00, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r				MASK11 r	MASK10 r	MASK9 r	MASK8 r	MASK7 r	MASK6 r	MASK5 r	MASK4 r	MASK3 r	MASK2 r	MASK1 r	MASK0 r

Toggle Fields

MASK0

Bit 0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK1

Bit 1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK2

Bit 2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK3

Bit 3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK4

Bit 4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK5

Bit 5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK6

Bit 6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK7

Bit 7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK8

Bit 8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK9

Bit 9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK10

Bit 10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

MASK11

Bit 11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x..

RESERVED

Bits 12-31: Reserved.

IC

Interrupt clear register for port n

Offset: 0x801c, reset: 0x00, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w				CLR11 w	CLR10 w	CLR9 w	CLR8 w	CLR7 w	CLR6 w	CLR5 w	CLR4 w	CLR3 w	CLR2 w	CLR1 w	CLR0 w

Toggle Fields

CLR0

CLR1

CLR2

CLR3

CLR4

CLR5

CLR6

CLR7

CLR8

CLR9

CLR10

CLR11

RESERVED

Bits 12-31: Reserved.

I2C

0x40000000: I2C-bus controller

8/54 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	7	6	5	4	3	2	1	0
0x0	CONSET	RESERVED	RESERVED		I2EN	STA	STO	SI	AA	RESERVED
0x4	STAT	RESERVED	RESERVED	Status					RESERVED
0x8	DAT	RESERVED	RESERVED	Data
0xc	ADR0	RESERVED	RESERVED	Address							GC
0x10	SCLH	RESERVED	SCLH
0x14	SCLL	RESERVED	SCLL
0x18	CONCLR	RESERVED	RESERVED		I2ENC	STAC	RESERVED	SIC	AAC	RESERVED
0x1c	MMCTRL	RESERVED	RESERVED						MATCH_ALL	ENA_SCL	MM_ENA
0x20	ADR[1]	RESERVED	RESERVED	Address							GC
0x24	ADR[2]	RESERVED	RESERVED	Address							GC
0x28	ADR[3]	RESERVED	RESERVED	Address							GC
0x2c	DATA_BUFFER	RESERVED	RESERVED	Data
0x30	MASK[0]	RESERVED	RESERVED	MASK							RESERVED
0x34	MASK[1]	RESERVED	RESERVED	MASK							RESERVED
0x38	MASK[2]	RESERVED	RESERVED	MASK							RESERVED
0x3c	MASK[3]	RESERVED	RESERVED	MASK							RESERVED

CONSET

I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.

Offset: 0x0, reset: 0x00, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw									I2EN rw	STA rw	STO rw	SI rw	AA rw	RESERVED rw

Toggle Fields

RESERVED

Bits 0-1: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined..

AA

Bit 2: Assert acknowledge flag..

SI

Bit 3: I2C interrupt flag..

STO

Bit 4: STOP flag..

STA

Bit 5: START flag..

I2EN

Bit 6: I2C interface enable..

RESERVED

Bits 7-31: Reserved. The value read from a reserved bit is not defined..

STAT

I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.

Offset: 0x4, reset: 0xF8, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								Status r					RESERVED r

Toggle Fields

RESERVED

Bits 0-2: These bits are unused and are always 0..

Status

Bits 3-7: These bits give the actual status information about the I 2C interface..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

DAT

I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

Offset: 0x8, reset: 0x00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Data rw

Toggle Fields

Data

Bits 0-7: This register holds data values that have been received or are to be transmitted..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

ADR0

I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Offset: 0xc, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Address rw							GC rw

Toggle Fields

GC

Bit 0: General Call enable bit..

Address

Bits 1-7: The I2C device address for slave mode..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

SCLH

SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.

Offset: 0x10, reset: 0x04, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw

Toggle Fields

SCLH

Bits 0-15: Count for SCL HIGH time period selection..

RESERVED

Bits 16-31: Reserved. The value read from a reserved bit is not defined..

SCLL

SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.

Offset: 0x14, reset: 0x04, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLL rw

Toggle Fields

SCLL

Bits 0-15: Count for SCL low time period selection..

RESERVED

Bits 16-31: Reserved. The value read from a reserved bit is not defined..

CONCLR

I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.

Offset: 0x18, reset: 0, access: write-only

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w									I2ENC w	STAC w	RESERVED w	SIC w	AAC w	RESERVED w

Toggle Fields

RESERVED

Bits 0-1: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined..

AAC

Bit 2: Assert acknowledge Clear bit..

SIC

Bit 3: I2C interrupt Clear bit..

RESERVED

Bit 4: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined..

STAC

Bit 5: START flag Clear bit..

I2ENC

Bit 6: I2C interface Disable bit..

RESERVED

Bit 7: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

MMCTRL

Monitor mode control register.

Offset: 0x1c, reset: 0x00, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw													MATCH_ALL rw	ENA_SCL rw	MM_ENA rw

Toggle Fields

MM_ENA

Bit 0: Monitor mode enable..

Allowed values:
0: DISABLED: Monitor mode disabled.
1: ENABLED: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.

ENA_SCL

Bit 1: SCL output enable..

Allowed values:
0: HIGH: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.
1: NORMAL: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]

MATCH_ALL

Bit 2: Select interrupt register match..

Allowed values:
0: MATCH: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.
1: ANYINT: When this bit is set to 1 and the I 2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.

RESERVED

Bits 3-31: Reserved. The value read from reserved bits is not defined..

ADR[1]

I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Offset: 0x20, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Address rw							GC rw

Toggle Fields

GC

Bit 0: General Call enable bit..

Address

Bits 1-7: The I2C device address for slave mode..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

ADR[2]

Offset: 0x24, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Address rw							GC rw

Toggle Fields

GC

Bit 0: General Call enable bit..

Address

Bits 1-7: The I2C device address for slave mode..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

ADR[3]

Offset: 0x28, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Address rw							GC rw

Toggle Fields

GC

Bit 0: General Call enable bit..

Address

Bits 1-7: The I2C device address for slave mode..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

DATA_BUFFER

Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.

Offset: 0x2c, reset: 0x00, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								Data r

Toggle Fields

Data

Bits 0-7: This register holds contents of the 8 MSBs of the I2DAT shift register..

RESERVED

Bits 8-31: Reserved. The value read from a reserved bit is not defined..

MASK[0]

I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).

Offset: 0x30, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								MASK rw							RESERVED rw

Toggle Fields

RESERVED

Bit 0: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0..

MASK

Bits 1-7: Mask bits..

RESERVED

Bits 8-31: Reserved. The value read from reserved bits is undefined..

MASK[1]

I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).

Offset: 0x34, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								MASK rw							RESERVED rw

Toggle Fields

RESERVED

Bit 0: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0..

MASK

Bits 1-7: Mask bits..

RESERVED

Bits 8-31: Reserved. The value read from reserved bits is undefined..

MASK[2]

I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).

Offset: 0x38, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								MASK rw							RESERVED rw

Toggle Fields

RESERVED

Bit 0: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0..

MASK

Bits 1-7: Mask bits..

RESERVED

Bits 8-31: Reserved. The value read from reserved bits is undefined..

MASK[3]

I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).

Offset: 0x3c, reset: 0x00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								MASK rw							RESERVED rw

Toggle Fields

RESERVED

Bit 0: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0..

MASK

Bits 1-7: Mask bits..

RESERVED

Bits 8-31: Reserved. The value read from reserved bits is undefined..

IOCON

0x40044000: I/O configuration

176/272 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	10	9	7	6	5	4	2	1
0x0	PIO2_6	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x8	PIO2_0	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xc	RESET_PIO0_0	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x10	PIO0_1	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x14	PIO1_8	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x1c	PIO0_2	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x20	PIO2_7	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x24	PIO2_8	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x28	PIO2_1	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x2c	PIO0_3	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x30	PIO0_4	RESERVED	RESERVED		I2CMODE	RESERVED				FUNC
0x34	PIO0_5	RESERVED	RESERVED		I2CMODE	RESERVED				FUNC
0x38	PIO1_9	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x3c	PIO3_4	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x40	PIO2_4	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x44	PIO2_5	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x48	PIO3_5	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x4c	PIO0_6	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x50	PIO0_7	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x54	PIO2_9	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x58	PIO2_10	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x5c	PIO2_2	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x60	PIO0_8	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x64	PIO0_9	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x68	SWCLK_PIO0_10	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x6c	PIO1_10	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x70	PIO2_11	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x74	R_PIO0_11	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x78	R_PIO1_0	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x7c	R_PIO1_1	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x80	R_PIO1_2	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x84	PIO3_0	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x88	PIO3_1	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x8c	PIO2_3	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0x90	SWDIO_PIO1_3	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x94	PIO1_4	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x98	PIO1_11	RESERVED	RESERVED	OD	RESERVED	ADMODE	RESERVED	HYS	MODE	FUNC
0x9c	PIO3_2	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xa0	PIO1_5	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xa4	PIO1_6	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xa8	PIO1_7	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xac	PIO3_3	RESERVED	RESERVED	OD	RESERVED			HYS	MODE	FUNC
0xb0	SCK0_LOC	RESERVED	RESERVED								SCKLOC
0xb4	DSR_LOC	RESERVED	RESERVED								DSRLOC
0xb8	DCD_LOC	RESERVED	RESERVED								DCDLOC
0xbc	RI_LOC	RESERVED	RESERVED								RILOC

PIO2_6

I/O configuration for pin PIO2_6

Offset: 0x0, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_6.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0x0: INACTIVE_NO_PULL_DO: Inactive (no pull-down/pull-up resistor enabled)
0x1: PULL_DOWN_RESISTOR_E: Pull-down resistor enabled
0x2: PULL_UP_RESISTOR_ENA: Pull-up resistor enabled
0x3: REPEATER_MODE: Repeater mode

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_0

I/O configuration for pin PIO2_0/DTR/SSEL1

Offset: 0x8, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO2: Select function PIO2_0.
0x1: DTR_: Select function DTR.
0x2: SSEL: Select function SSEL1 (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

RESET_PIO0_0

I/O configuration for pin RESET/PIO0_0

Offset: 0xc, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: RES: Selects function RESET.
0x1: PIO: Selects function PIO0_0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_1

I/O configuration for pin PIO0_1/CLKOUT/ CT32B0_MAT2/USB_FTOGGLE

Offset: 0x10, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_1.
0x1: CLK: Selects function CLKOUT.
0x2: CT3: Selects function CT32B0_MAT2.
0x3: USB: Selects function USB_FTOGGLE (function not available on all parts)

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_8

I/O configuration for pin PIO1_8/CT16B1_CAP0

Offset: 0x14, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_8.
0x1: CT1: Selects function CT16B1_CAP0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_2

I/O configuration for pin PIO0_2/SSEL0/ CT16B0_CAP0

Offset: 0x1c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_2.
0x1: SSE: Selects function SSEL0.
0x2: CT1: Selects function CT16B0_CAP0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_7

I/O configuration for pin PIO2_7

Offset: 0x20, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_7.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_8

I/O configuration for pin PIO2_8

Offset: 0x24, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_8.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_1

I/O configuration for pin PIO2_1/DSR/SCK1

Offset: 0x28, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_1.
0x1: DSR_: Select function DSR.
0x2: SCK1: Select function SCK1 (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_3

I/O configuration for pin PIO0_3/USB_VBUS

Offset: 0x2c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_3.
0x1: USB: Selects function USB_VBUS (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_4

I/O configuration for pin PIO0_4/SCL

Offset: 0x30, reset: 0x00, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw						I2CMODE rw		RESERVED rw					FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_4 (open-drain pin).
0x1: SELECTS_I2C_FUNCTION: Selects I2C function SCL (open-drain pin).

RESERVED

Bits 3-7: Reserved.

I2CMODE

Bits 8-9: Selects I2C mode. Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)..

Allowed values:
0x0: STANDARDFAST_: Standard mode/ Fast-mode I2C
0x1: STANDARDIO: Standard I/O functionality
0x2: FAST_MODE_PLUS_I2C: Fast-mode Plus I2C
0x3: RESERVED: Reserved

RESERVED

Bits 10-31: Reserved.

PIO0_5

I/O configuration for pin PIO0_5/SDA

Offset: 0x34, reset: 0x00, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw						I2CMODE rw		RESERVED rw					FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_5 (open-drain pin).
0x1: SELECTS_I2C_FUNCTION: Selects I2C function SDA (open-drain pin).

RESERVED

Bits 3-7: Reserved.

I2CMODE

Bits 8-9: Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)..

Allowed values:
0x0: STANDARDFAST: Standard mode/ Fast-mode I2C
0x1: STANDARDIO: Standard I/O functionality
0x2: FAST_MODE_PLUS_I2C: Fast-mode Plus I2C
0x3: RESERVED: Reserved

RESERVED

Bits 10-31: Reserved.

PIO1_9

I/O configuration for pin PIO1_9/CT16B1_MAT0

Offset: 0x38, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_9.
0x1: CT1: Selects function CT16B1_MAT0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_4

I/O configuration for pin PIO3_4

Offset: 0x3c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_4.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_4

I/O configuration for pin PIO2_4

Offset: 0x40, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_4.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_5

I/O configuration for pin PIO2_5

Offset: 0x44, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_5.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_5

I/O configuration for pin PIO3_5

Offset: 0x48, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_5.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_6

I/O configuration for pin PIO0_6/USB_CONNECT/SCK

Offset: 0x4c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_6.
0x1: USB: Selects function USB_CONNECT (function not available on all parts).
0x2: SCK: Selects function SCK0 (only if pin PIO0_6/ USB_CONNECT/ SCK0 selected in Table 139).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_7

I/O configuration for pin PIO0_7/CTS

Offset: 0x50, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_7.
0x1: CTS_: Select function CTS.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_9

I/O configuration for pin PIO2_9

Offset: 0x54, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_9.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_10

I/O configuration for pin PIO2_10

Offset: 0x58, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_10.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_2

I/O configuration for pin PIO2_2/DCD/MISO1

Offset: 0x5c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_2.
0x1: DCD_: Select function DCD.
0x2: MISO: Select function MISO1 (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_8

I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0

Offset: 0x60, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_8.
0x1: MIS: Selects function MISO0.
0x2: CT1: Selects function CT16B0_MAT0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO0_9

I/O configuration for pin PIO0_9/MOSI0/ CT16B0_MAT1/SWO

Offset: 0x64, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO0_9.
0x1: MOS: Selects function MOSI0.
0x2: CT1: Selects function CT16B0_MAT1.
0x3: SWO: Selects function SWO

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

SWCLK_PIO0_10

I/O configuration for pin SWCLK/PIO0_10/ SCK/CT16B0_MAT2

Offset: 0x68, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: SWC: Selects function SWCLK.
0x1: PIO: Selects function PIO0_10.
0x2: SCK: Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 139).
0x3: CT1: Selects function CT16B0_MAT2.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_10

I/O configuration for pin PIO1_10/AD6/ CT16B1_MAT1

Offset: 0x6c, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_10.
0x1: AD6: Selects function AD6.
0x2: CT1: Selects function CT16B1_MAT1.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_11

I/O configuration for pin PIO2_11/SCK

Offset: 0x70, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_11.
0x1: SCK: Selects function SCK0 (only if pin PIO2_11/SCK0 selected in Table 139)

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

R_PIO0_11

I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3

Offset: 0x74, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: R_: Selects function R. This function is reserved. Select one of the alternate functions below.
0x1: PIO: Selects function PIO0_11.
0x2: AD0: Selects function AD0.
0x3: CT3: Selects function CT32B0_MAT3.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

R_PIO1_0

I/O configuration for pin R/PIO1_0/AD1/ CT32B1_CAP0

Offset: 0x78, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: R_: Selects function R. This function is reserved. Select one of the alternate functions below.
0x1: PIO: Selects function PIO1_0.
0x2: AD1: Selects function AD1.
0x3: CT3: Selects function CT32B1_CAP0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

R_PIO1_1

I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0

Offset: 0x7c, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: R_: Selects function R. This function is reserved. Select one of the alternate functions below.
0x1: PIO: Selects function PIO1_1.
0x2: AD2: Selects function AD2.
0x3: CT3: Selects function CT32B1_MAT0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

R_PIO1_2

I/O configuration for pin R/PIO1_2/AD3/ CT32B1_MAT1

Offset: 0x80, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: R_: Selects function R. This function is reserved. Select one of the alternate functions below.
0x1: PIO: Selects function PIO1_2.
0x2: AD3: Selects function AD3.
0x3: CT3: Selects function CT32B1_MAT1.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_0

I/O configuration for pin PIO3_0/DTR

Offset: 0x84, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_0.
0x1: DTR: Selects function DTR (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_1

I/O configuration for pin PIO3_1/DSR

Offset: 0x88, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_1.
0x1: DSR: Selects function DSR (function not available on all parts, must also be configured in the corresponding DSR_LOC register).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO2_3

I/O configuration for pin PIO2_3/RI/MOSI1

Offset: 0x8c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO2_3.
0x1: RI_: Selects function RI.
0x2: MOS: Selects function MOSI1 (function not available on all parts).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

SWDIO_PIO1_3

I/O configuration for pin SWDIO/PIO1_3/AD4/ CT32B1_MAT2

Offset: 0x90, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: SWD: Selects function SWDIO.
0x1: PIO: Selects function PIO1_3.
0x2: AD4: Selects function AD4.
0x3: CT3: Selects function CT32B1_MAT2.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_4

I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3

Offset: 0x94, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. This pin functions as WAKEUP pin if the LPC13xx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_4.
0x1: AD5: Selects function AD5.
0x2: CT3: Selects function CT32B1_MAT3.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_11

I/O configuration for pin PIO1_11/AD7

Offset: 0x98, reset: 0xD0, access: read-write

5/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw		ADMODE rw	RESERVED rw	HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_11.
0x1: AD7: Selects function AD7.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bit 6: Reserved.

ADMODE

Bit 7: Selects Analog/Digital mode.

Allowed values:
0: ANALOG_INPUT_MODE: Analog input mode
1: DIGITAL_FUNCTIONAL_M: Digital functional mode

RESERVED

Bits 8-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_2

I/O configuration for pin PIO3_2/DCD

Offset: 0x9c, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_2.
0x1: DCD: Selects function DCD (function not available on all parts, must also be configured in the corresponding DCD_LOC register).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_5

I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0

Offset: 0xa0, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_5.
0x1: RTS: Selects function RTS.
0x2: CT3: Selects function CT32B0_CAP0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_6

I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0

Offset: 0xa4, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_6.
0x1: RXD: Selects function RXD.
0x2: CT3: Selects function CT32B0_MAT0.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO1_7

I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1

Offset: 0xa8, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO1_7.
0x1: TXD: Selects function TXD.
0x2: CT3: Selects function CT32B0_MAT1.

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

PIO3_3

I/O configuration for pin PIO3_3/RI

Offset: 0xac, reset: 0xD0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw					OD rw	RESERVED rw				HYS rw	MODE rw		FUNC rw

Toggle Fields

FUNC

Bits 0-2: Selects pin function. All other values are reserved..

Allowed values:
0x0: PIO: Selects function PIO3_3.
0x1: RI_: Selects function RI (function not available on all parts, must also be configured in the corresponding RI_LOC register).

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control).

HYS

Bit 5: Hysteresis.

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 6-9: Reserved.

OD

Bit 10: Selects pseudo open-drain mode..

Allowed values:
0: STANDARD_GPIO_OUTPUT: Standard GPIO output
1: OPEN_DRAIN_OUTPUT: Open-drain output

RESERVED

Bits 11-31: Reserved.

SCK0_LOC

SCK0 pin location register

Offset: 0xb0, reset: 0, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SCKLOC rw

Toggle Fields

SCKLOC

Bits 0-1: Selects pin location for SCK0 pin..

Allowed values:
0x0: SELECTS_SCK0_FUNCTION0: Selects SCK0 function for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 121).
0x1: SELECTS_SCK0_FUNCTION1: Selects SCK0 function for pin PIO2_11/SCK0 (see Table 123
0x2: SELECTS_SCK0_FUNCTION2: Selects SCK0 function for pin PIO0_6/USB_CONNECT/SCK0 (see Table 114).
0x3: RESERVED_: Reserved.

RESERVED

Bits 2-31: Reserved.

DSR_LOC

DSR pin location select register

Offset: 0xb4, reset: 0, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														DSRLOC rw

Toggle Fields

DSRLOC

Bits 0-1: Selects pin location for DSR0 pin (this register is only used for parts LPC1311/01 and LPC1313/01)..

Allowed values:
0x0: SELECTS_DSR_FUNCTION_0: Selects DSR function in pin location PIO2_1/DSR/SCK1.
0x1: SELECTS_DSR_FUNCTION_1: Selects DSR function in pin location PIO3_1/DSR.
0x2: RESERVED_2: Reserved.
0x3: RESERVED_3: Reserved.

RESERVED

Bits 2-31: Reserved..

DCD_LOC

DCD pin location select register

Offset: 0xb8, reset: 0, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														DCDLOC rw

Toggle Fields

DCDLOC

Bits 0-1: Selects pin location for DCD pin (this register is only used for parts LPC1311/01 and LPC1313/01)..

Allowed values:
0x0: SELECTS_DCD_FUNCTION: Selects DCD function in pin location PIO2_2/DCD/MISO1.
0x1: SELECTS_DCD_FUNCTIO: Selects DCD function in pin location PIO3_2/DCD.
0x2: RESERVED_2: Reserved.
0x3: RESERVED_3: Reserved.

RESERVED

Bits 2-31: Reserved..

RI_LOC

RI pin location register

Offset: 0xbc, reset: 0, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														RILOC rw

Toggle Fields

RILOC

Bits 0-1: Selects pin location for RI pin (this register is only used for parts LPC1311/01 and LPC1313/01).

Allowed values:
0x0: SELECTS_RI_FUNCTION_0: Selects RI function in pin location PIO2_3/RI/MOSI1.
0x1: SELECTS_RI_FUNCTION_1: Selects RI function in pin location PIO3_3/RI.
0x2: RESERVED_2: Reserved.
0x3: RESERVED_3: Reserved.

RESERVED

Bits 2-31: Reserved..

PMU

0x40038000: Power Management Unit (PMU)

4/14 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	11	10	9	8	7	1	0
0x0	PCON	RESERVED	RESERVED	DPDFLAG	RESERVED		SLEEPFLAG	RESERVED	DPDEN	RESERVED
0x4	GPREG[0]	GPDATA	GPDATA
0x8	GPREG[1]	GPDATA	GPDATA
0xc	GPREG[2]	GPDATA	GPDATA
0x10	GPREG[3]	GPDATA	GPDATA
0x14	GPREG4	GPDATA	GPDATA		WAKEUPHYS	RESERVED

PCON

Power control register

Offset: 0x0, reset: 0x0, access: read-write

3/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				DPDFLAG rw	RESERVED rw		SLEEPFLAG rw	RESERVED rw						DPDEN rw	RESERVED rw

Toggle Fields

RESERVED

Bit 0: Reserved. Do not write 1 to this bit..

DPDEN

Bit 1: Deep power-down mode enable.

Allowed values:
0: SLEEP_DEEPSLEEP: ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M3 core turned off).
1: DEEPPOWERDOWN: ARM WFI will enter Deep-power down mode (ARM Cortex-M3 core powered-down).

RESERVED

Bits 2-7: Reserved. Do not write ones to this bit..

SLEEPFLAG

Bit 8: Sleep mode flag.

Allowed values:
0: NO_POWER_DOWN_: Read: No power-down mode entered. LPC13xx is in Run mode. Write: No effect.
1: POWERDOWN: Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.

RESERVED

Bits 9-10: Reserved. Do not write ones to this bit..

DPDFLAG

Bit 11: Deep power-down flag.

Allowed values:
0: NO_DEEPPOWERDOWN: Read: Deep power-down mode not entered. Write: No effect.
1: DEEPPOWERDOWN: Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.

RESERVED

Bits 12-31: Reserved. Do not write ones to this bit..

GPREG[0]

General purpose register

Offset: 0x4, reset: 0x0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDATA rw

Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[1]

General purpose register

Offset: 0x8, reset: 0x0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDATA rw

Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[2]

General purpose register

Offset: 0xc, reset: 0x0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDATA rw

Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[3]

General purpose register

Offset: 0x10, reset: 0x0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDATA rw

Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG4

General purpose register 4

Offset: 0x14, reset: 0x0, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDATA rw					WAKEUPHYS rw	RESERVED rw

Toggle Fields

RESERVED

Bits 0-9: Reserved. Do not write ones to this bit..

WAKEUPHYS

Bit 10: WAKEUP pin hysteresis enable.

Allowed values:
0: DISABLED: Hysteresis for WAKUP pin disabled.
1: ENABLED: Hysteresis for WAKEUP pin enabled.

GPDATA

Bits 11-31: Data retained during Deep power-down mode..

SSP0

0x40040000: SSP0/1

23/39 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	7	6	5	4	3	2	1	0
0x0	CR0	RESERVED	SCR	CPHA	CPOL	FRF		DSS
0x4	CR1	RESERVED	RESERVED					SOD	MS	SSE	LBM
0x8	DR	RESERVED	DATA
0xc	SR	RESERVED	RESERVED				BSY	RFF	RNE	TNF	TFE
0x10	CPSR	RESERVED	RESERVED	CPSDVSR
0x14	IMSC	RESERVED	RESERVED					TXIM	RXIM	RTIM	RORIM
0x18	RIS	RESERVED	RESERVED					TXRIS	RXRIS	RTRIS	RORRIS
0x1c	MIS	RESERVED	RESERVED					TXMIS	RXMIS	RTMIS	RORMIS
0x20	ICR	RESERVED	RESERVED							RTIC	RORIC

CR0

Control Register 0. Selects the serial clock rate, bus type, and data size.

Offset: 0x0, reset: 0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCR rw								CPHA rw	CPOL rw	FRF rw		DSS rw

Toggle Fields

DSS

Bits 0-3: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used..

Allowed values:
0x3: 4_BIT_TRANSFER: 4-bit transfer
0x4: 5_BIT_TRANSFER: 5-bit transfer
0x5: 6_BIT_TRANSFER: 6-bit transfer
0x6: 7_BIT_TRANSFER: 7-bit transfer
0x7: 8_BIT_TRANSFER: 8-bit transfer
0x8: 9_BIT_TRANSFER: 9-bit transfer
0x9: 10_BIT_TRANSFER: 10-bit transfer
0xA: 11_BIT_TRANSFER: 11-bit transfer
0xB: 12_BIT_TRANSFER: 12-bit transfer
0xC: 13_BIT_TRANSFER: 13-bit transfer
0xD: 14_BIT_TRANSFER: 14-bit transfer
0xE: 15_BIT_TRANSFER: 15-bit transfer
0xF: 16_BIT_TRANSFER: 16-bit transfer

FRF

Bits 4-5: Frame Format..

Allowed values:
0x0: SPI: SPI
0x1: TI: TI
0x2: MICROWIRE: Microwire
0x3: THIS_COMBINATION_IS_: This combination is not supported and should not be used.

CPOL

Bit 6: Clock Out Polarity. This bit is only used in SPI mode..

Allowed values:
0: LOW: SSP controller maintains the bus clock low between frames.
1: HIGH: SSP controller maintains the bus clock high between frames.

CPHA

Bit 7: Clock Out Phase. This bit is only used in SPI mode..

Allowed values:
0: FIRSTCLOCK: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.
1: SECONDCLOK: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.

SCR

Bits 8-15: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR x [SCR+1])..

RESERVED

Bits 16-31: Reserved..

CR1

Control Register 1. Selects master/slave and other modes.

Offset: 0x4, reset: 0, access: read-write

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												SOD rw	MS rw	SSE rw	LBM rw

Toggle Fields

LBM

Bit 0: Loop Back Mode..

Allowed values:
0: NORMAL: During normal operation.
1: OUTPUT: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).

SSE

Bit 1: SSP Enable..

Allowed values:
0: DISABLED: The SSP controller is disabled.
1: ENABLED: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.

MS

Bit 2: Master/Slave Mode.This bit can only be written when the SSE bit is 0..

Allowed values:
0: MASTER: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
1: SLAVE: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.

SOD

Bit 3: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DR

Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.

Offset: 0x8, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle Fields

DATA

Bits 0-15: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s..

RESERVED

Bits 16-31: Reserved..

SR

Status Register.

Offset: 0xc, reset: 0x00000003, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r											BSY r	RFF r	RNE r	TNF r	TFE r

Toggle Fields

TFE

Bit 0: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not..

TNF

Bit 1: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not..

RNE

Bit 2: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not..

RFF

Bit 3: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not..

BSY

Bit 4: Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty..

RESERVED

Bits 5-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CPSR

Clock Prescale Register.

Offset: 0x10, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								CPSDVSR rw

Toggle Fields

CPSDVSR

Bits 0-7: This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0..

RESERVED

Bits 8-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

IMSC

Interrupt Mask Set and Clear Register.

Offset: 0x14, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												TXIM rw	RXIM rw	RTIM rw	RORIM rw

Toggle Fields

RORIM

Bit 0: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs..

RTIM

Bit 1: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])..

RXIM

Bit 2: Software should set this bit to enable interrupt when the Rx FIFO is at least half full..

TXIM

Bit 3: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RIS

Raw Interrupt Status Register.

Offset: 0x18, reset: 0x00000008, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r												TXRIS r	RXRIS r	RTRIS r	RORRIS r

Toggle Fields

RORRIS

Bit 0: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs..

RTRIS

Bit 1: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])..

RXRIS

Bit 2: This bit is 1 if the Rx FIFO is at least half full..

TXRIS

Bit 3: This bit is 1 if the Tx FIFO is at least half empty..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MIS

Masked Interrupt Status Register.

Offset: 0x1c, reset: 0, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r												TXMIS r	RXMIS r	RTMIS r	RORMIS r

Toggle Fields

RORMIS

Bit 0: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled..

RTMIS

Bit 1: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])..

RXMIS

Bit 2: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled..

TXMIS

Bit 3: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

ICR

SSPICR Interrupt Clear Register.

Offset: 0x20, reset: 0, access: write-only

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w														RTIC w	RORIC w

Toggle Fields

RORIC

Bit 0: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt..

RTIC

Bit 1: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])..

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

SSP1

0x40058000: SSP0/1

23/39 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	7	6	5	4	3	2	1	0
0x0	CR0	RESERVED	SCR	CPHA	CPOL	FRF		DSS
0x4	CR1	RESERVED	RESERVED					SOD	MS	SSE	LBM
0x8	DR	RESERVED	DATA
0xc	SR	RESERVED	RESERVED				BSY	RFF	RNE	TNF	TFE
0x10	CPSR	RESERVED	RESERVED	CPSDVSR
0x14	IMSC	RESERVED	RESERVED					TXIM	RXIM	RTIM	RORIM
0x18	RIS	RESERVED	RESERVED					TXRIS	RXRIS	RTRIS	RORRIS
0x1c	MIS	RESERVED	RESERVED					TXMIS	RXMIS	RTMIS	RORMIS
0x20	ICR	RESERVED	RESERVED							RTIC	RORIC

CR0

Control Register 0. Selects the serial clock rate, bus type, and data size.

Offset: 0x0, reset: 0, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCR rw								CPHA rw	CPOL rw	FRF rw		DSS rw

Toggle Fields

DSS

Bits 0-3: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used..

FRF

Bits 4-5: Frame Format..

Allowed values:
0x0: SPI: SPI
0x1: TI: TI
0x2: MICROWIRE: Microwire
0x3: THIS_COMBINATION_IS_: This combination is not supported and should not be used.

CPOL

Bit 6: Clock Out Polarity. This bit is only used in SPI mode..

Allowed values:
0: LOW: SSP controller maintains the bus clock low between frames.
1: HIGH: SSP controller maintains the bus clock high between frames.

CPHA

Bit 7: Clock Out Phase. This bit is only used in SPI mode..

SCR

RESERVED

Bits 16-31: Reserved..

CR1

Control Register 1. Selects master/slave and other modes.

Offset: 0x4, reset: 0, access: read-write

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												SOD rw	MS rw	SSE rw	LBM rw

Toggle Fields

LBM

Bit 0: Loop Back Mode..

Allowed values:
0: NORMAL: During normal operation.
1: OUTPUT: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).

SSE

Bit 1: SSP Enable..

MS

Bit 2: Master/Slave Mode.This bit can only be written when the SSE bit is 0..

SOD

Bit 3: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DR

Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.

Offset: 0x8, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle Fields

DATA

RESERVED

Bits 16-31: Reserved..

SR

Status Register.

Offset: 0xc, reset: 0x00000003, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r											BSY r	RFF r	RNE r	TNF r	TFE r

Toggle Fields

TFE

Bit 0: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not..

TNF

Bit 1: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not..

RNE

Bit 2: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not..

RFF

Bit 3: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not..

BSY

Bit 4: Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty..

RESERVED

Bits 5-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CPSR

Clock Prescale Register.

Offset: 0x10, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								CPSDVSR rw

Toggle Fields

CPSDVSR

Bits 0-7: This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0..

RESERVED

Bits 8-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

IMSC

Interrupt Mask Set and Clear Register.

Offset: 0x14, reset: 0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw												TXIM rw	RXIM rw	RTIM rw	RORIM rw

Toggle Fields

RORIM

RTIM

RXIM

Bit 2: Software should set this bit to enable interrupt when the Rx FIFO is at least half full..

TXIM

Bit 3: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RIS

Raw Interrupt Status Register.

Offset: 0x18, reset: 0x00000008, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r												TXRIS r	RXRIS r	RTRIS r	RORRIS r

Toggle Fields

RORRIS

Bit 0: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs..

RTRIS

RXRIS

Bit 2: This bit is 1 if the Rx FIFO is at least half full..

TXRIS

Bit 3: This bit is 1 if the Tx FIFO is at least half empty..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

MIS

Masked Interrupt Status Register.

Offset: 0x1c, reset: 0, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r												TXMIS r	RXMIS r	RTMIS r	RORMIS r

Toggle Fields

RORMIS

Bit 0: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled..

RTMIS

RXMIS

Bit 2: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled..

TXMIS

Bit 3: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled..

RESERVED

Bits 4-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

ICR

SSPICR Interrupt Clear Register.

Offset: 0x20, reset: 0, access: write-only

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w														RTIC w	RORIC w

Toggle Fields

RORIC

Bit 0: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt..

RTIC

RESERVED

Bits 2-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

SYSCON

0x40048000: System configuration

159/338 fields covered. Toggle Registers

Show register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SYSMEMREMAP	RESERVED																RESERVED														MAP
0x4	PRESETCTRL	RESERVED																													SSP1_RST_N	I2C_RST_N	SSP0_RST_N
0x8	SYSPLLCTRL	RESERVED																RESERVED									PSEL		MSEL
0xc	SYSPLLSTAT	RESERVED																RESERVED															LOCK
0x10	USBPLLCTRL	RESERVED																RESERVED									PSEL		MSEL
0x14	USBPLLSTAT	RESERVED																RESERVED															LOCK
0x20	SYSOSCCTRL	RESERVED																RESERVED														FREQRANGE	BYPASS
0x24	WDTOSCCTRL	RESERVED																RESERVED							FREQSEL				DIVSEL
0x28	IRCCTRL	RESERVED																RESERVED								TRIM
0x30	SYSRESSTAT	RESERVED																RESERVED											SYSRST	BOD	WDT	EXTRST	POR
0x40	SYSPLLCLKSEL	RESERVED																RESERVED														SEL
0x44	SYSPLLCLKUEN	RESERVED																RESERVED															ENA
0x48	USBPLLCLKSEL	RESERVED																RESERVED														SEL
0x4c	USBPLLCLKUEN	RESERVED																RESERVED															ENA
0x70	MAINCLKSEL	RESERVED																RESERVED														SEL
0x74	MAINCLKUEN	RESERVED																RESERVED															ENA
0x78	SYSAHBCLKDIV	RESERVED																RESERVED								DIV
0x80	SYSAHBCLKCTRL	RESERVED															IOCON	WDT	USB_REG	ADC	UART	SSP	CT32B1	CT32B0	CT16B1	CT16B0	GPIO	I2C	FLASHARRAY	FLASHREG	RAM	ROM	SYS
0x94	SSP0CLKDIV	RESERVED																RESERVED								DIV
0x98	UARTCLKDIV	RESERVED																RESERVED								DIV
0x9c	SSP1CLKDIV	RESERVED																RESERVED								DIV
0xac	TRACECLKDIV	RESERVED																RESERVED								DIV
0xb0	SYSTICKCLKDIV	RESERVED																RESERVED								DIV
0xc0	USBCLKSEL	RESERVED																RESERVED														SEL
0xc4	USBCLKUEN	RESERVED																RESERVED															ENA
0xc8	USBCLKDIV	RESERVED																RESERVED								DIV
0xd0	WDTCLKSEL	RESERVED																RESERVED														SEL
0xd4	WDTCLKUEN	RESERVED																RESERVED															ENA
0xd8	WDTCLKDIV	RESERVED																RESERVED								DIV
0xe0	CLKOUTCLKSEL	RESERVED																RESERVED														SEL
0xe4	CLKOUTUEN	RESERVED																RESERVED															ENA
0xe8	CLKOUTDIV	RESERVED																RESERVED								DIV
0x100	PIOPORCAP0	CAPPIO2_7	CAPPIO2_6	CAPPIO2_5	CAPPIO2_4	CAPPIO2_3	CAPPIO2_2	CAPPIO2_1	CAPPIO2_0	CAPPIO1_11	CAPPIO1_10	CAPPIO1_9	CAPPIO1_8	CAPPIO1_7	CAPPIO1_6	CAPPIO1_5	CAPPIO1_4	CAPPIO1_3	CAPPIO1_2	CAPPIO1_1	CAPPIO1_0	CAPPIO0_11	CAPPIO0_10	CAPPIO0_9	CAPPIO0_8	CAPPIO0_7	CAPPIO0_6	CAPPIO0_5	CAPPIO0_4	CAPPIO0_3	CAPPIO0_2	CAPPIO0_1	CAPPIO0_0
0x104	PIOPORCAP1	RESERVED																RESERVED						CAPPIO3_5	CAPPIO3_4	CAPPIO3_3	CAPPIO3_2	CAPPIO3_1	CAPPIO3_0	CAPPIO2_11	CAPPIO2_10	CAPPIO2_9	CAPPIO2_8
0x150	BODCTRL	RESERVED																RESERVED											BODRSTENA	BODINTVAL		BODRSTLEV
0x154	SYSTCKCAL	RESERVED						CAL										CAL
0x200	STARTAPRP0	APRPIO2_7	APRPIO2_6	APRPIO2_5	APRPIO2_4	APRPIO2_3	APRPIO2_2	APRPIO2_1	APRPIO2_0	APRPIO1_11	APRPIO1_10	APRPIO1_9	APRPIO1_8	APRPIO1_7	APRPIO1_6	APRPIO1_5	APRPIO1_4	APRPIO1_3	APRPIO1_2	APRPIO1_1	APRPIO1_0	APRPIO0_11	APRPIO0_10	APRPIO0_9	APRPIO0_8	APRPIO0_7	APRPIO0_6	APRPIO0_5	APRPIO0_4	APRPIO0_3	APRPIO0_2	APRPIO0_1	APRPIO0_0
0x204	STARTERP0	ERPIO2_7	ERPIO2_6	ERPIO2_5	ERPIO2_4	ERPIO2_3	ERPIO2_2	ERPIO2_1	ERPIO2_0	ERPIO1_11	ERPIO1_10	ERPIO1_9	ERPIO1_8	ERPIO1_7	ERPIO1_6	ERPIO1_5	ERPIO1_4	ERPIO1_3	ERPIO1_2	ERPIO1_1	ERPIO1_0	ERPIO0_11	ERPIO0_10	ERPIO0_9	ERPIO0_8	ERPIO0_7	ERPIO0_6	ERPIO0_5	ERPIO0_4	ERPIO0_3	ERPIO0_2	ERPIO0_1	ERPIO0_0
0x208	STARTRSRP0CLR	RSRPIO2_7	RSRPIO2_6	RSRPIO2_5	RSRPIO2_4	RSRPIO2_3	RSRPIO2_2	RSRPIO2_1	RSRPIO2_0	RSRPIO1_11	RSRPIO1_10	RSRPIO1_9	RSRPIO1_8	RSRPIO1_7	RSRPIO1_6	RSRPIO1_5	RSRPIO1_4	RSRPIO1_3	RSRPIO1_2	RSRPIO1_1	RSRPIO1_0	RSRPIO0_11	RSRPIO0_10	RSRPIO0_9	RSRPIO0_8	RSRPIO0_7	RSRPIO0_6	RSRPIO0_5	RSRPIO0_4	RSRPIO0_3	RSRPIO0_2	RSRPIO0_1	RSRPIO0_0
0x20c	STARTSRP0	SRPIO2_7	SRPIO2_6	SRPIO2_5	SRPIO2_4	SRPIO2_3	SRPIO2_2	SRPIO2_1	SRPIO2_0	SRPIO1_11	SRPIO1_10	SRPIO1_9	SRPIO1_8	SRPIO1_7	SRPIO1_6	SRPIO1_5	SRPIO1_4	SRPIO1_3	SRPIO1_2	SRPIO1_1	SRPIO1_0	SRPIO0_11	SRPIO0_10	SRPIO0_9	SRPIO0_8	SRPIO0_7	SRPIO0_6	SRPIO0_5	SRPIO0_4	SRPIO0_3	SRPIO0_2	SRPIO0_1	SRPIO0_0
0x210	STARTAPRP1	RESERVED																RESERVED								APRPIO3_3	APRPIO3_2	APRPIO3_1	APRPIO3_0	APRPIO2_11	APRPIO2_10	APRPIO2_9	APRPIO2_8
0x214	STARTERP1	RESERVED																RESERVED								ERPIO3_3	ERPIO3_2	ERPIO3_1	ERPIO3_0	ERPIO2_11	ERPIO2_10	ERPIO2_9	ERPIO2_8
0x218	STARTRSRP1CLR	RESERVED																RESERVED								RSRPIO3_3	RSRPIO3_2	RSRPIO3_1	RSRPIO3_0	RSRPIO2_11	RSRPIO2_10	RSRPIO2_9	RSRPIO2_8
0x21c	STARTSRP1	RESERVED																RESERVED								SRPIO3_3	SRPIO3_2	SRPIO3_1	SRPIO3_0	SRPIO2_11	SRPIO2_10	SRPIO2_9	SRPIO2_8
0x230	PDSLEEPCFG	RESERVED																RESERVED				FIXEDVAL2					WDTOSC_PD	FIXEDVAL1		BOD_PD	FIXEDVAL0
0x234	PDAWAKECFG	RESERVED																RESERVED				FIXEDVAL1	USBPAD_PD	FIXEDVAL0	USBPLL_PD	SYSPLL_PD	WDTOSC_PD	SYSOSC_PD	ADC_PD	BOD_PD	FLASH_PD	IRC_PD	IRCOUT_PD
0x238	PDRUNCFG	RESERVED																RESERVED				FIXEDVAL1	USBPAD_PD	FIXEDVAL0	USBPLL_PD	SYSPLL_PD	WDTOSC_PD	SYSOSC_PD	ADC_PD	BOD_PD	FLASH_PD	IRC_PD	IRCOUT_PD
0x3f4	DEVICE_ID	DEVICEID																DEVICEID

SYSMEMREMAP

System memory remap

Offset: 0x0, reset: 0x00000002, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														MAP rw

Toggle Fields

MAP

Bits 0-1: System memory remap.

Allowed values:
0x0: BOOT_LOADER_MODE_IN: Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
0x1: USER_RAM_MODE_INTER: User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
0x2: USER_FLASH_MODE_INT: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.

RESERVED

Bits 2-31: Reserved.

PRESETCTRL

Peripheral reset control

Offset: 0x4, reset: 0x00000000, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													SSP1_RST_N rw	I2C_RST_N rw	SSP0_RST_N rw

Toggle Fields

SSP0_RST_N

Bit 0: SSP0 reset control.

Allowed values:
0: RESET_SSP0_: Reset SSP0.
1: DE_ASSERT_SSP0_RESET: De-assert SSP0 reset.

I2C_RST_N

Bit 1: I2C reset control.

Allowed values:
0: RESET_I2C_: Reset I2C.
1: DE_ASSET_I2C_RESET_: De-asset I2C reset.

SSP1_RST_N

Bit 2: SPISP1 reset control.

Allowed values:
0: RESET_THE_SPISP1_: Reset the SPISP1.
1: DE_ASSERT_SPISP1_RES: De-assert SPISP1 reset.

RESERVED

Bits 23-31: Reserved.

SYSPLLCTRL

System PLL control

Offset: 0x8, reset: 0x00000000, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw									PSEL rw		MSEL rw

Toggle Fields

MSEL

Bits 0-4: Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32..

PSEL

Bits 5-6: Post divider ratio P. The division ratio is 2 x P..

Allowed values:
0x0: P_EQ_1: P = 1
0x1: P_EQ_2: P = 2
0x2: P_EQ_4: P = 4
0x3: P_EQ_8: P = 8

RESERVED

Bits 7-31: Reserved. Do not write ones to reserved bits..

SYSPLLSTAT

System PLL status

Offset: 0xc, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r															LOCK r

Toggle Fields

LOCK

Bit 0: PLL lock status.

Allowed values:
0: PLL_NOT_LOCKED: PLL not locked
1: PLL_LOCKED: PLL locked

RESERVED

Bits 1-31: Reserved.

USBPLLCTRL

USB PLL control

Offset: 0x10, reset: 0x00000000, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw									PSEL rw		MSEL rw

Toggle Fields

MSEL

Bits 0-4: Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32..

PSEL

Bits 5-6: Post divider ratio P. The division ratio is 2 x P..

Allowed values:
0x0: P_EQ_1: P = 1
0x1: P_EQ_2: P = 2
0x2: P_EQ_4: P = 4
0x3: P_EQ_8: P = 8

RESERVED

Bits 7-31: Reserved. Do not write ones to reserved bits..

USBPLLSTAT

USB PLL status

Offset: 0x14, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r															LOCK r

Toggle Fields

LOCK

Bit 0: PLL lock status.

Allowed values:
0: PLL_NOT_LOCKED: PLL not locked
1: PLL_LOCKED: PLL locked

RESERVED

Bits 1-31: Reserved.

SYSOSCCTRL

System oscillator control

Offset: 0x20, reset: 0x00000000, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														FREQRANGE rw	BYPASS rw

Toggle Fields

BYPASS

Bit 0: Bypass system oscillator.

Allowed values:
0: OSCILLATOR_IS_NOT_BY: Oscillator is not bypassed.
1: BYPASS_ENABLED_PLL_: Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins.

FREQRANGE

Bit 1: Determines frequency range for Low-power oscillator..

Allowed values:
0: 1__20_MHZ_FREQUENCY: 1 - 20 MHz frequency range.
1: 15__25_MHZ_FREQUENC: 15 - 25 MHz frequency range

RESERVED

Bits 2-31: Reserved.

WDTOSCCTRL

Watchdog oscillator control

Offset: 0x24, reset: 0x00000000, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw							FREQSEL rw				DIVSEL rw

Toggle Fields

DIVSEL

Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana (2 x (1 + DIVSEL)). 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64.

FREQSEL

Bits 5-8: Select watchdog oscillator analog output frequency (Fclkana)..

Allowed values:
0x1: 0_5_MHZ: 0.5 MHz
0x2: 0_8_MHZ: 0.8 MHz
0x3: 1_1_MHZ: 1.1 MHz
0x4: 1_4_MHZ: 1.4 MHz
0x5: 1_6_MHZ: 1.6 MHz
0x6: 1_8_MHZ: 1.8 MHz
0x7: 2_0_MHZ: 2.0 MHz
0x8: 2_2_MHZ: 2.2 MHz
0x9: 2_4_MHZ: 2.4 MHz
0xA: 2_6_MHZ: 2.6 MHz
0xB: 2_7_MHZ: 2.7 MHz
0xC: 2_9_MHZ: 2.9 MHz
0xD: 3_1_MHZ: 3.1 MHz
0xE: 3_2_MHZ: 3.2 MHz
0xF: 3_4_MHZ: 3.4 MHz

RESERVED

Bits 9-31: Reserved.

IRCCTRL

IRC control

Offset: 0x28, reset: 0x00000080, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								TRIM rw

Toggle Fields

TRIM

Bits 0-7: Trim value.

RESERVED

Bits 8-31: Reserved.

SYSRESSTAT

System reset status register

Offset: 0x30, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r											SYSRST r	BOD r	WDT r	EXTRST r	POR r

Toggle Fields

POR

Bit 0: POR reset status.

Allowed values:
0: NO_POR_DETECTED: No POR detected
1: POR_DETECTED: POR detected

EXTRST

Bit 1: Status of the external RESET pin.

Allowed values:
0: NO_RESET_EVENT_DETEC: No RESET event detected
1: RESET_DETECTED: RESET detected

WDT

Bit 2: Status of the Watchdog reset.

Allowed values:
0: NO_WDT_RESET_DETECTE: No WDT reset detected
1: WDT_RESET_DETECTED: WDT reset detected

BOD

Bit 3: Status of the Brown-out detect reset.

Allowed values:
0: NO_BOD_RESET_DETECTE: No BOD reset detected
1: BOD_RESET_DETECTED: BOD reset detected

SYSRST

Bit 4: Status of the software system reset. The ARM software reset has the same effect as the hardware reset using the RESET pin..

Allowed values:
0: NO_SYSTEM_RESET_DETE: No System reset detected
1: SYSTEM_RESET_DETECTE: System reset detected

RESERVED

Bits 5-31: Reserved.

SYSPLLCLKSEL

System PLL clock source select

Offset: 0x40, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: System PLL clock source.

Allowed values:
0x0: IRC_OSCILLATOR: IRC oscillator
0x1: SYSTEM_OSCILLATOR: System oscillator
0x2: RESERVED: Reserved
0x3: RESERVED: Reserved

RESERVED

Bits 2-31: Reserved.

SYSPLLCLKUEN

System PLL clock source update enable

Offset: 0x44, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable system PLL clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

USBPLLCLKSEL

USB PLL clock source select

Offset: 0x48, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: USB PLL clock source.

Allowed values:
0x0: IRC_THE_USB_PLL_CLO: IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation.
0x1: SYSTEM_OSCILLATOR: System oscillator
0x2: RESERVED: Reserved
0x3: RESERVED: Reserved

RESERVED

Bits 2-31: Reserved.

USBPLLCLKUEN

USB PLL clock source update enable

Offset: 0x4c, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable USB PLL clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

MAINCLKSEL

Main clock source select

Offset: 0x70, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: Clock source for main clock.

Allowed values:
0x0: IRC_OSCILLATOR: IRC oscillator
0x1: INPUT_CLOCK_TO_SYSTE: Input clock to system PLL
0x2: WDT_OSCILLATOR: WDT oscillator
0x3: SYSTEM_PLL_CLOCK_OUT: System PLL clock out

RESERVED

Bits 2-31: Reserved.

MAINCLKUEN

Main clock source update enable

Offset: 0x74, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable main clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

SYSAHBCLKDIV

System AHB clock divider

Offset: 0x78, reset: 0x00000001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

SYSAHBCLKCTRL

System AHB clock control

Offset: 0x80, reset: 0x0000485F, access: read-write

18/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw															IOCON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDT rw	USB_REG rw	ADC rw	UART rw	SSP rw	CT32B1 rw	CT32B0 rw	CT16B1 rw	CT16B0 rw	GPIO rw	I2C rw	FLASHARRAY rw	FLASHREG rw	RAM rw	ROM rw	SYS rw

Toggle Fields

SYS

Bit 0: Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M3 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only..

Allowed values:
0: RESERVED: Reserved
1: ENABLED: Enabled

ROM

Bit 1: Enables clock for ROM..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

RAM

Bit 2: Enables clock for RAM..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

FLASHREG

Bit 3: Enables clock for flash register interface..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

FLASHARRAY

Bit 4: Enables clock for flash array access..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

I2C

Bit 5: Enables clock for I2C..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

GPIO

Bit 6: Enables clock for GPIO..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

CT16B0

Bit 7: Enables clock for 16-bit counter/timer 0..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

CT16B1

Bit 8: Enables clock for 16-bit counter/timer 1..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

CT32B0

Bit 9: Enables clock for 32-bit counter/timer 0..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

CT32B1

Bit 10: Enables clock for 32-bit counter/timer 1..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

SSP

Bit 11: Enables clock for SSP..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

UART

Bit 12: Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

ADC

Bit 13: Enables clock for ADC..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

USB_REG

Bit 14: Enables clock for USB_REG..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

WDT

Bit 15: Enables clock for WDT..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

IOCON

Bit 16: Enables clock for IO configuration block..

Allowed values:
0: DISABLED: Disabled
1: ENABLED: Enabled

RESERVED

Bits 17-31: Reserved.

SSP1

Bit 18: Enables clock for SPISP1..

Allowed values:
0: DISABLE: Disable
1: ENABLE: Enable

RESERVED

Bits 19-31: Reserved.

SSP0CLKDIV

SSP clock divder

Offset: 0x94, reset: 0x00000001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: SSP_PCLK clock divider values. 0: Disable SSP0_PCLK. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

UARTCLKDIV

UART clock divder

Offset: 0x98, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

SSP1CLKDIV

SPISP1 clock divder

Offset: 0x9c, reset: 0x000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

TRACECLKDIV

ARM trace clock divider

Offset: 0xac, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

SYSTICKCLKDIV

SYSTICK clock divder

Offset: 0xb0, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

USBCLKSEL

USB clock source select

Offset: 0xc0, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: USB clock source.

Allowed values:
0x0: USB_PLL_OUT: USB PLL out
0x1: MAIN_CLOCK: Main clock
0x2: RESERVED: Reserved
0x3: RESERVED: Reserved

RESERVED

Bits 2-31: Reserved.

USBCLKUEN

USB clock source update enable

Offset: 0xc4, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable USB clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

USBCLKDIV

USB clock source divider

Offset: 0xc8, reset: 0x00000001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: USB clock divider values. 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

WDTCLKSEL

WDT clock source select

Offset: 0xd0, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: WDT clock source.

Allowed values:
0x0: IRC_OSCILLATOR: IRC oscillator
0x1: MAIN_CLOCK: Main clock
0x2: WATCHDOG_OSCILLATOR: Watchdog oscillator
0x3: RESERVED: Reserved

RESERVED

Bits 2-31: Reserved.

WDTCLKUEN

WDT clock source update enable

Offset: 0xd4, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable WDT clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

WDTCLKDIV

WDT clock divider

Offset: 0xd8, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: WDT clock divider values. 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

CLKOUTCLKSEL

CLKOUT clock source select

Offset: 0xe0, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw														SEL rw

Toggle Fields

SEL

Bits 0-1: CLKOUT clock source.

Allowed values:
0x0: IRC_OSCILLATOR: IRC oscillator
0x1: SYSTEM_OSCILLATOR: System oscillator
0x2: WATCHDOG_OSCILLATOR: Watchdog oscillator
0x3: MAIN_CLOCK: Main clock

RESERVED

Bits 2-31: Reserved.

CLKOUTUEN

CLKOUT clock source update enable

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw															ENA rw

Toggle Fields

ENA

Bit 0: Enable CLKOUT clock source update.

Allowed values:
0: NO_CHANGE: No change
1: UPDATE_CLOCK_SOURCE: Update clock source

RESERVED

Bits 1-31: Reserved.

CLKOUTDIV

CLKOUT clock divider

Offset: 0xe8, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DIV rw

Toggle Fields

DIV

Bits 0-7: Clock divider values. 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255..

RESERVED

Bits 8-31: Reserved.

PIOPORCAP0

POR captured PIO status 0

Offset: 0x100, reset: 0, access: read-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CAPPIO2_7 r	CAPPIO2_6 r	CAPPIO2_5 r	CAPPIO2_4 r	CAPPIO2_3 r	CAPPIO2_2 r	CAPPIO2_1 r	CAPPIO2_0 r	CAPPIO1_11 r	CAPPIO1_10 r	CAPPIO1_9 r	CAPPIO1_8 r	CAPPIO1_7 r	CAPPIO1_6 r	CAPPIO1_5 r	CAPPIO1_4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAPPIO1_3 r	CAPPIO1_2 r	CAPPIO1_1 r	CAPPIO1_0 r	CAPPIO0_11 r	CAPPIO0_10 r	CAPPIO0_9 r	CAPPIO0_8 r	CAPPIO0_7 r	CAPPIO0_6 r	CAPPIO0_5 r	CAPPIO0_4 r	CAPPIO0_3 r	CAPPIO0_2 r	CAPPIO0_1 r	CAPPIO0_0 r

Toggle Fields

CAPPIO0_0

Bit 0: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_1

Bit 1: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_2

Bit 2: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_3

Bit 3: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_4

Bit 4: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_5

Bit 5: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_6

Bit 6: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_7

Bit 7: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_8

Bit 8: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_9

Bit 9: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_10

Bit 10: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO0_11

Bit 11: Raw reset status input PIO0_11 to PIO0_0.

CAPPIO1_0

Bit 12: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_1

Bit 13: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_2

Bit 14: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_3

Bit 15: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_4

Bit 16: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_5

Bit 17: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_6

Bit 18: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_7

Bit 19: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_8

Bit 20: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_9

Bit 21: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_10

Bit 22: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO1_11

Bit 23: Raw reset status input PIO1_11 to PIO1_0.

CAPPIO2_0

Bit 24: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_1

Bit 25: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_2

Bit 26: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_3

Bit 27: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_4

Bit 28: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_5

Bit 29: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_6

Bit 30: Raw reset status input PIO2_7 to PIO2_0.

CAPPIO2_7

Bit 31: Raw reset status input PIO2_7 to PIO2_0.

PIOPORCAP1

POR captured PIO status 1

Offset: 0x104, reset: 0, access: read-only

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r						CAPPIO3_5 r	CAPPIO3_4 r	CAPPIO3_3 r	CAPPIO3_2 r	CAPPIO3_1 r	CAPPIO3_0 r	CAPPIO2_11 r	CAPPIO2_10 r	CAPPIO2_9 r	CAPPIO2_8 r

Toggle Fields

CAPPIO2_8

Bit 0: Raw reset status input PIO2_8.

CAPPIO2_9

Bit 1: Raw reset status input PIO2_9.

CAPPIO2_10

Bit 2: Raw reset status input PIO2_10.

CAPPIO2_11

Bit 3: Raw reset status input PIO2_11.

CAPPIO3_0

Bit 4: Raw reset status input PIO3_0.

CAPPIO3_1

Bit 5: Raw reset status input PIO3_1.

CAPPIO3_2

Bit 6: Raw reset status input PIO3_2.

CAPPIO3_3

Bit 7: Raw reset status input PIO3_3.

CAPPIO3_4

Bit 8: Raw reset status input PIO3_4.

CAPPIO3_5

Bit 9: Raw reset status input PIO3_5.

RESERVED

Bits 10-31: Reserved.

BODCTRL

BOD control

Offset: 0x150, reset: 0x00000000, access: read-write

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											BODRSTENA rw	BODINTVAL rw		BODRSTLEV rw

Toggle Fields

BODRSTLEV

Bits 0-1: BOD reset level. Trip values x/y refer to the LPC1300/LPC1300L series..

Allowed values:
0x0: LEVEL0: The reset assertion threshold voltage is 1.49 V/1.46 V; the reset de-assertion threshold voltage is 1.64 V/1.63 V.
0x1: LEVEL1: The reset assertion threshold voltage is -/2.06 V; the reset de-assertion threshold voltage is -/2.15 V.
0x2: LEVEL2: The reset assertion threshold voltage is -/2.35 V; the reset de-assertion threshold voltage is -/2.43 V.
0x3: LEVEL3: The reset assertion threshold voltage is -/2.63 V; the reset de-assertion threshold voltage is -/2.71 V.

BODINTVAL

Bits 2-3: BOD interrupt level. Trip values x/y refer to the LPC1300/LPC1300L series..

Allowed values:
0x0: LEVEL0: The interrupt assertion threshold voltage is 1.69 V/1.65 V; the interrupt de-assertion threshold voltage is 1.84 V/1.8 V.
0x1: LEVEL1: The interrupt assertion threshold voltage is 2.29 V/2.22 V; the interrupt de-assertion threshold voltage is 2.44 V/2.35 V.
0x2: LEVEL2: The interrupt assertion threshold voltage is 2.59 V/ 2.52 V; the interrupt de-assertion threshold voltage is 2.74 V/2.66 V.
0x3: LEVEL3: The interrupt assertion threshold voltage is 2.87 V/2.80 V; the interrupt de-assertion threshold voltage is 2.98 V/2.90 V.

BODRSTENA

Bit 4: BOD reset enable.

Allowed values:
0: DISABLE_RESET_FUNCTI: Disable reset function.
1: ENABLE_RESET_FUNCTIO: Enable reset function.

RESERVED

Bits 5-31: Reserved.

SYSTCKCAL

System tick counter calibration

Offset: 0x154, reset: 0x00000004, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw						CAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CAL rw

Toggle Fields

CAL

Bits 0-25: System tick timer calibration value.

RESERVED

Bits 26-31: Reserved.

STARTAPRP0

Start logic edge control register 0; bottom 32 interrupts

Offset: 0x200, reset: 0, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
APRPIO2_7 rw	APRPIO2_6 rw	APRPIO2_5 rw	APRPIO2_4 rw	APRPIO2_3 rw	APRPIO2_2 rw	APRPIO2_1 rw	APRPIO2_0 rw	APRPIO1_11 rw	APRPIO1_10 rw	APRPIO1_9 rw	APRPIO1_8 rw	APRPIO1_7 rw	APRPIO1_6 rw	APRPIO1_5 rw	APRPIO1_4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
APRPIO1_3 rw	APRPIO1_2 rw	APRPIO1_1 rw	APRPIO1_0 rw	APRPIO0_11 rw	APRPIO0_10 rw	APRPIO0_9 rw	APRPIO0_8 rw	APRPIO0_7 rw	APRPIO0_6 rw	APRPIO0_5 rw	APRPIO0_4 rw	APRPIO0_3 rw	APRPIO0_2 rw	APRPIO0_1 rw	APRPIO0_0 rw

Toggle Fields

APRPIO0_0

Bit 0: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_1

Bit 1: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_2

Bit 2: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_3

Bit 3: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_4

Bit 4: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_5

Bit 5: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_6

Bit 6: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_7

Bit 7: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_8

Bit 8: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_9

Bit 9: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_10

Bit 10: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO0_11

Bit 11: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_0

Bit 12: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_1

Bit 13: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_2

Bit 14: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_3

Bit 15: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_4

Bit 16: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_5

Bit 17: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_6

Bit 18: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_7

Bit 19: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_8

Bit 20: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_9

Bit 21: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_10

Bit 22: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO1_11

Bit 23: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge..

APRPIO2_0

Bit 24: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_1

Bit 25: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_2

Bit 26: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_3

Bit 27: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_4

Bit 28: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_5

Bit 29: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_6

Bit 30: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

APRPIO2_7

Bit 31: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge..

STARTERP0

Start logic signal enable register 0; bottom 32 interrupts

Offset: 0x204, reset: 0, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ERPIO2_7 rw	ERPIO2_6 rw	ERPIO2_5 rw	ERPIO2_4 rw	ERPIO2_3 rw	ERPIO2_2 rw	ERPIO2_1 rw	ERPIO2_0 rw	ERPIO1_11 rw	ERPIO1_10 rw	ERPIO1_9 rw	ERPIO1_8 rw	ERPIO1_7 rw	ERPIO1_6 rw	ERPIO1_5 rw	ERPIO1_4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERPIO1_3 rw	ERPIO1_2 rw	ERPIO1_1 rw	ERPIO1_0 rw	ERPIO0_11 rw	ERPIO0_10 rw	ERPIO0_9 rw	ERPIO0_8 rw	ERPIO0_7 rw	ERPIO0_6 rw	ERPIO0_5 rw	ERPIO0_4 rw	ERPIO0_3 rw	ERPIO0_2 rw	ERPIO0_1 rw	ERPIO0_0 rw

Toggle Fields

ERPIO0_0

Bit 0: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_1

Bit 1: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_2

Bit 2: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_3

Bit 3: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_4

Bit 4: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_5

Bit 5: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_6

Bit 6: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_7

Bit 7: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_8

Bit 8: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_9

Bit 9: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_10

Bit 10: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO0_11

Bit 11: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled..

ERPIO1_0

Bit 12: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_1

Bit 13: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_2

Bit 14: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_3

Bit 15: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_4

Bit 16: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_5

Bit 17: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_6

Bit 18: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_7

Bit 19: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_8

Bit 20: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_9

Bit 21: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_10

Bit 22: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO1_11

Bit 23: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled..

ERPIO2_0

Bit 24: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_1

Bit 25: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_2

Bit 26: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_3

Bit 27: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_4

Bit 28: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_5

Bit 29: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_6

Bit 30: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

ERPIO2_7

Bit 31: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled..

STARTRSRP0CLR

Start logic reset register 0; bottom 32 interrupts

Offset: 0x208, reset: 0, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RSRPIO2_7 w	RSRPIO2_6 w	RSRPIO2_5 w	RSRPIO2_4 w	RSRPIO2_3 w	RSRPIO2_2 w	RSRPIO2_1 w	RSRPIO2_0 w	RSRPIO1_11 w	RSRPIO1_10 w	RSRPIO1_9 w	RSRPIO1_8 w	RSRPIO1_7 w	RSRPIO1_6 w	RSRPIO1_5 w	RSRPIO1_4 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSRPIO1_3 w	RSRPIO1_2 w	RSRPIO1_1 w	RSRPIO1_0 w	RSRPIO0_11 w	RSRPIO0_10 w	RSRPIO0_9 w	RSRPIO0_8 w	RSRPIO0_7 w	RSRPIO0_6 w	RSRPIO0_5 w	RSRPIO0_4 w	RSRPIO0_3 w	RSRPIO0_2 w	RSRPIO0_1 w	RSRPIO0_0 w

Toggle Fields

RSRPIO0_0

Bit 0: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_1

Bit 1: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_2

Bit 2: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_3

Bit 3: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_4

Bit 4: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_5

Bit 5: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_6

Bit 6: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_7

Bit 7: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_8

Bit 8: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_9

Bit 9: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_10

Bit 10: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO0_11

Bit 11: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_0

Bit 12: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_1

Bit 13: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_2

Bit 14: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_3

Bit 15: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_4

Bit 16: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_5

Bit 17: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_6

Bit 18: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_7

Bit 19: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_8

Bit 20: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_9

Bit 21: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_10

Bit 22: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO1_11

Bit 23: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_0

Bit 24: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_1

Bit 25: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_2

Bit 26: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_3

Bit 27: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_4

Bit 28: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_5

Bit 29: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_6

Bit 30: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

RSRPIO2_7

Bit 31: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal..

STARTSRP0

Start logic status register 0; bottom 32 interrupts

Offset: 0x20c, reset: 0, access: read-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRPIO2_7 r	SRPIO2_6 r	SRPIO2_5 r	SRPIO2_4 r	SRPIO2_3 r	SRPIO2_2 r	SRPIO2_1 r	SRPIO2_0 r	SRPIO1_11 r	SRPIO1_10 r	SRPIO1_9 r	SRPIO1_8 r	SRPIO1_7 r	SRPIO1_6 r	SRPIO1_5 r	SRPIO1_4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRPIO1_3 r	SRPIO1_2 r	SRPIO1_1 r	SRPIO1_0 r	SRPIO0_11 r	SRPIO0_10 r	SRPIO0_9 r	SRPIO0_8 r	SRPIO0_7 r	SRPIO0_6 r	SRPIO0_5 r	SRPIO0_4 r	SRPIO0_3 r	SRPIO0_2 r	SRPIO0_1 r	SRPIO0_0 r

Toggle Fields

SRPIO0_0

Bit 0: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_1

Bit 1: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_2

Bit 2: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_3

Bit 3: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_4

Bit 4: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_5

Bit 5: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_6

Bit 6: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_7

Bit 7: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_8

Bit 8: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_9

Bit 9: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_10

Bit 10: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO0_11

Bit 11: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_0

Bit 12: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_1

Bit 13: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_2

Bit 14: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_3

Bit 15: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_4

Bit 16: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_5

Bit 17: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_6

Bit 18: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_7

Bit 19: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_8

Bit 20: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_9

Bit 21: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_10

Bit 22: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO1_11

Bit 23: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_0

Bit 24: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_1

Bit 25: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_2

Bit 26: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_3

Bit 27: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_4

Bit 28: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_5

Bit 29: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_6

Bit 30: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_7

Bit 31: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending..

STARTAPRP1

Start logic edge control register 1; top 8 interrupts

Offset: 0x210, reset: 0, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								APRPIO3_3 rw	APRPIO3_2 rw	APRPIO3_1 rw	APRPIO3_0 rw	APRPIO2_11 rw	APRPIO2_10 rw	APRPIO2_9 rw	APRPIO2_8 rw

Toggle Fields

APRPIO2_8

Bit 0: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge..

APRPIO2_9

Bit 1: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge..

APRPIO2_10

Bit 2: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge..

APRPIO2_11

Bit 3: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge..

APRPIO3_0

Bit 4: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge..

APRPIO3_1

Bit 5: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge..

APRPIO3_2

Bit 6: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge..

APRPIO3_3

Bit 7: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge..

RESERVED

Bits 8-31: Reserved.

STARTERP1

Start logic signal enable register 1; top 8 interrupts

Offset: 0x214, reset: 0, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								ERPIO3_3 rw	ERPIO3_2 rw	ERPIO3_1 rw	ERPIO3_0 rw	ERPIO2_11 rw	ERPIO2_10 rw	ERPIO2_9 rw	ERPIO2_8 rw

Toggle Fields

ERPIO2_8

Bit 0: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled..

ERPIO2_9

Bit 1: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled..

ERPIO2_10

Bit 2: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled..

ERPIO2_11

Bit 3: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled..

ERPIO3_0

Bit 4: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled..

ERPIO3_1

Bit 5: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled..

ERPIO3_2

Bit 6: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled..

ERPIO3_3

Bit 7: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled..

RESERVED

Bits 8-31: Reserved.

STARTRSRP1CLR

Start logic reset register 1; top 8 interrupts

Offset: 0x218, reset: 0, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w								RSRPIO3_3 w	RSRPIO3_2 w	RSRPIO3_1 w	RSRPIO3_0 w	RSRPIO2_11 w	RSRPIO2_10 w	RSRPIO2_9 w	RSRPIO2_8 w

Toggle Fields

RSRPIO2_8

Bit 0: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO2_9

Bit 1: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO2_10

Bit 2: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO2_11

Bit 3: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO3_0

Bit 4: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO3_1

Bit 5: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO3_2

Bit 6: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal..

RSRPIO3_3

Bit 7: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal..

RESERVED

Bits 8-31: Reserved.

STARTSRP1

Start logic status register 1; top 8 interrupts

Offset: 0x21c, reset: 0, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								SRPIO3_3 r	SRPIO3_2 r	SRPIO3_1 r	SRPIO3_0 r	SRPIO2_11 r	SRPIO2_10 r	SRPIO2_9 r	SRPIO2_8 r

Toggle Fields

SRPIO2_8

Bit 0: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_9

Bit 1: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_10

Bit 2: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO2_11

Bit 3: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending..

SRPIO3_0

Bit 4: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending..

SRPIO3_1

Bit 5: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending..

SRPIO3_2

Bit 6: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending..

SRPIO3_3

Bit 7: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending..

RESERVED

Bits 8-31: Reserved.

PDSLEEPCFG

Power-down states in Deep-sleep mode

Offset: 0x230, reset: 0x00000000, access: read-write

2/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				FIXEDVAL2 rw					WDTOSC_PD rw	FIXEDVAL1 rw		BOD_PD rw	FIXEDVAL0 rw

Toggle Fields

FIXEDVAL0

Bits 0-2: Reserved. Always write these bits as 111..

BOD_PD

Bit 3: BOD power-down control in Deep-sleep mode, see Table 49..

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FIXEDVAL1

Bits 4-5: Reserved. Always write these bits as 11..

WDTOSC_PD

Bit 6: Watchdog oscillator power control in Deep-sleep mode, see Table 49..

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FIXEDVAL2

Bits 7-11: Reserved. Always write these bits as 11111..

RESERVED

Bits 12-31: Reserved.

PDAWAKECFG

Power-down states after wake-up from Deep-sleep mode

Offset: 0x234, reset: 0x0000FDF0, access: read-write

10/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				FIXEDVAL1 rw	USBPAD_PD rw	FIXEDVAL0 rw	USBPLL_PD rw	SYSPLL_PD rw	WDTOSC_PD rw	SYSOSC_PD rw	ADC_PD rw	BOD_PD rw	FLASH_PD rw	IRC_PD rw	IRCOUT_PD rw

Toggle Fields

IRCOUT_PD

Bit 0: IRC oscillator output wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

IRC_PD

Bit 1: IRC oscillator power-down wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FLASH_PD

Bit 2: Flash wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

BOD_PD

Bit 3: BOD wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

ADC_PD

Bit 4: ADC wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

SYSOSC_PD

Bit 5: System oscillator wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

WDTOSC_PD

Bit 6: Watchdog oscillator wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

SYSPLL_PD

Bit 7: System PLL wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

USBPLL_PD

Bit 8: USB PLL wake-up configuration.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FIXEDVAL0

Bit 9: Reserved. Always write this bit as 0..

USBPAD_PD

Bit 10: USB pad wake-up configuration.

Allowed values:
0: USB_PHY_POWERED: USB PHY powered
1: USB_PHY_POWERED_DOWN: USB PHY powered down

FIXEDVAL1

Bit 11: Reserved. Always write this bit as 1..

RESERVED

Bits 12-31: Reserved.

PDRUNCFG

Power-down configuration register

Offset: 0x238, reset: 0x0000FDF0, access: read-write

10/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw				FIXEDVAL1 rw	USBPAD_PD rw	FIXEDVAL0 rw	USBPLL_PD rw	SYSPLL_PD rw	WDTOSC_PD rw	SYSOSC_PD rw	ADC_PD rw	BOD_PD rw	FLASH_PD rw	IRC_PD rw	IRCOUT_PD rw

Toggle Fields

IRCOUT_PD

Bit 0: IRC oscillator output power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

IRC_PD

Bit 1: IRC oscillator power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FLASH_PD

Bit 2: Flash power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

BOD_PD

Bit 3: BOD power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

ADC_PD

Bit 4: ADC power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

SYSOSC_PD

Bit 5: System oscillator power-down[1].

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

WDTOSC_PD

Bit 6: Watchdog oscillator power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

SYSPLL_PD

Bit 7: System PLL power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

USBPLL_PD

Bit 8: USB PLL power-down.

Allowed values:
0: POWERED: Powered
1: POWERED_DOWN: Powered down

FIXEDVAL0

Bit 9: Reserved. Always write this bit as 0..

USBPAD_PD

Bit 10: USB pad power-down configuration.

Allowed values:
0: USB_PHY_POWERED: USB PHY powered
1: USB_PHY_POWERED_DOWN: USB PHY powered down (suspend mode)

FIXEDVAL1

Bit 11: Reserved. Always write this bit as 1..

RESERVED

Bits 12-31: Reserved.

DEVICE_ID

Device ID

Offset: 0x3f4, reset: 0, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DEVICEID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEVICEID r

Toggle Fields

DEVICEID

Bits 0-31: Device ID for LPC13xx parts: 0x2C42 502B = LPC1311FHN33 0x2C40 102B = LPC1313FHN33 0x2C40 102B = LPC1313FBD48 0x3D01 402B = LPC1342FHN33 0x3D00 002B = LPC1343FHN33 0x3D00 002B = LPC1343FBD48 0x1816 902B = LPC1311FHN33/01 0x1830 102B = LPC1313FHN33/01 0x1830 102B = LPC1313FBD48/01.

UART

0x40008000: UART

55/90 fields covered. Toggle Registers

Show register map

Offset	Name	31	15	9	8	7	6	5	4	3	2	1	0
0x0	DLL	RESERVED	RESERVED			DLLSB
0x0	RBR	RESERVED	RESERVED			RBR
0x0	THR	RESERVED	RESERVED			THR
0x4	DLM	RESERVED	RESERVED			DLMSB
0x4	IER	RESERVED	RESERVED	ABTOINTEN	ABEOINTEN	RESERVED					RXLIE	THREIE	RBRIE
0x8	FCR	RESERVED	RESERVED			RXTLVL		RESERVED			TXFIFOR	RXFIFOR	FIFOEN
0x8	IIR	RESERVED	RESERVED	ABTOINT	ABEOINT	FIFOEN		RESERVED		INTID			INTSTATUS
0xc	LCR	RESERVED	RESERVED			DLAB	BC	PS		PE	SBS	WLS
0x10	MCR	RESERVED	RESERVED			CTSEN	RTSEN	RESERVED	LMS	RESERVED		RTSCTRL	DTRCTRL
0x14	LSR	RESERVED	RESERVED			RXFE	TEMT	THRE	BI	FE	PE	OE	RDR
0x18	MSR	RESERVED	RESERVED			DCD	RI	DSR	CTS	DELTADCD	TERI	DELTADSR	DELTACTS
0x1c	SCR	RESERVED	RESERVED			Pad
0x20	ACR	RESERVED	RESERVED	ABTOINTCLR	ABEOINTCLR	RESERVED					AUTORESTART	MODE	START
0x28	FDR	RESERVED	RESERVED			MULVAL				DIVADDVAL
0x30	TER	RESERVED	RESERVED			TXEN	RESERVED
0x4c	RS485CTRL	RESERVED	RESERVED					OINV	DCTRL	SEL	AADEN	RXDIS	NMMEN
0x50	RS485ADRMATCH	RESERVED	RESERVED			ADRMATCH
0x54	RS485DLY	RESERVED	RESERVED			DLY

DLL

Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.

Offset: 0x0, reset: 0x01, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DLLSB rw

Toggle Fields

DLLSB

Bits 0-7: The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART..

RESERVED

Bits 8-31: Reserved.

RBR

Receiver Buffer Register. Contains the next received character to be read. When DLAB=0.

Offset: 0x0, reset: 0, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								RBR r

Toggle Fields

RBR

Bits 0-7: The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO..

RESERVED

Bits 8-31: Reserved.

THR

Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0.

Offset: 0x0, reset: 0, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w								THR w

Toggle Fields

THR

Bits 0-7: Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available..

RESERVED

Bits 8-31: Reserved.

DLM

Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.

Offset: 0x4, reset: 0x00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DLMSB rw

Toggle Fields

DLMSB

Bits 0-7: The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART..

RESERVED

Bits 8-31: Reserved.

IER

Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0.

Offset: 0x4, reset: 0x00, access: read-write

5/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw						ABTOINTEN rw	ABEOINTEN rw	RESERVED rw					RXLIE rw	THREIE rw	RBRIE rw

Toggle Fields

RBRIE

Bit 0: Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt..

Allowed values:
0: DISABLE: Disable the RDA interrupt.
1: ENABLE: Enable the RDA interrupt.

THREIE

Bit 1: Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]..

Allowed values:
0: DISABLE: Disable the THRE interrupt.
1: ENABLE: Enable the THRE interrupt.

RXLIE

Bit 2: Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]..

Allowed values:
0: DISABLE: Disable the RX line status interrupts.
1: ENABLE: Enable the RX line status interrupts.

RESERVED

Bit 3: Reserved.

RESERVED

Bits 4-6: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RESERVED

Bit 7: Reserved.

ABEOINTEN

Bit 8: Enables the end of auto-baud interrupt..

Allowed values:
0: DISABLE: Disable end of auto-baud Interrupt.
1: ENABLE: Enable end of auto-baud Interrupt.

ABTOINTEN

Bit 9: Enables the auto-baud time-out interrupt..

Allowed values:
0: DISABLE: Disable auto-baud time-out Interrupt.
1: ENABLE: Enable auto-baud time-out Interrupt.

RESERVED

Bits 10-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FCR

FIFO Control Register. Controls UART FIFO usage and modes.

Offset: 0x8, reset: 0x00, access: write-only

4/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w								RXTLVL w		RESERVED w			TXFIFOR w	RXFIFOR w	FIFOEN w

Toggle Fields

FIFOEN

Bit 0: FIFO Enable.

Allowed values:
0: DISABLED: UART FIFOs are disabled. Must not be used in the application.
1: ENABLED: Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs.

RXFIFOR

Bit 1: RX FIFO Reset.

Allowed values:
0: NOACTION: No impact on either of UART FIFOs.
1: CLEAR: Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing.

TXFIFOR

Bit 2: TX FIFO Reset.

Allowed values:
0: NOACTION: No impact on either of UART FIFOs.
1: CLEAR: Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing.

RESERVED

Bit 3: Reserved.

RESERVED

Bits 4-5: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RXTLVL

Bits 6-7: RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated..

Allowed values:
0x0: TRIGGER_LEVEL_0_1_C: Trigger level 0 (1 character or 0x01).
0x1: TRIGGER_LEVEL_1_4_C: Trigger level 1 (4 characters or 0x04).
0x2: TRIGGER_LEVEL_2_8_C: Trigger level 2 (8 characters or 0x08).
0x3: TRIGGER_LEVEL_3_14_: Trigger level 3 (14 characters or 0x0E).

RESERVED

Bits 8-31: Reserved.

IIR

Interrupt ID Register. Identifies which interrupt(s) are pending.

Offset: 0x8, reset: 0x01, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r						ABTOINT r	ABEOINT r	FIFOEN r		RESERVED r		INTID r			INTSTATUS r

Toggle Fields

INTSTATUS

Bit 0: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]..

Allowed values:
0: INT: At least one interrupt is pending.
1: NOINT: No interrupt is pending.

INTID

Bits 1-3: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)..

Allowed values:
0x3: RECEIVE: 1 - Receive Line Status (RLS).
0x2: RDA: 2a - Receive Data Available (RDA).
0x6: CTIMEOUT: 2b - Character Time-out Indicator (CTI).
0x1: THRE: 3 - THRE Interrupt.
0x0: MODEM: 4 - Modem interrupt.

RESERVED

Bits 4-5: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FIFOEN

Bits 6-7: These bits are equivalent to FCR[0]..

ABEOINT

Bit 8: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled..

ABTOINT

Bit 9: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled..

RESERVED

Bits 10-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

LCR

Line Control Register. Contains controls for frame formatting and break generation.

Offset: 0xc, reset: 0x00, access: read-write

6/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DLAB rw	BC rw	PS rw		PE rw	SBS rw	WLS rw

Toggle Fields

WLS

Bits 0-1: Word Length Select.

Allowed values:
0x0: 5_BIT_CHARACTER_LENG: 5-bit character length.
0x1: 6_BIT_CHARACTER_LENG: 6-bit character length.
0x2: 7_BIT_CHARACTER_LENG: 7-bit character length.
0x3: 8_BIT_CHARACTER_LENG: 8-bit character length.

SBS

Bit 2: Stop Bit Select.

Allowed values:
0: 1_STOP_BIT_: 1 stop bit.
1: 2_STOP_BITS_1_5_IF_: 2 stop bits (1.5 if LCR[1:0]=00).

PE

Bit 3: Parity Enable.

Allowed values:
0: DISABLE_PARITY_GENER: Disable parity generation and checking.
1: ENABLE_PARITY_GENERA: Enable parity generation and checking.

PS

Bits 4-5: Parity Select.

Allowed values:
0x0: ODD_PARITY_NUMBER_O: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
0x1: EVEN_PARITY_NUMBER_: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
0x2: FORCED_1_STICK_PARIT: Forced 1 stick parity.
0x3: FORCED_0_STICK_PARIT: Forced 0 stick parity.

BC

Bit 6: Break Control.

Allowed values:
0: DISABLE_BREAK_TRANSM: Disable break transmission.
1: ENABLE_BREAK_TRANSMI: Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high.

DLAB

Bit 7: Divisor Latch Access Bit (DLAB).

Allowed values:
0: DISABLE_ACCESS_TO_DI: Disable access to Divisor Latches.
1: ENABLE_ACCESS_TO_DIV: Enable access to Divisor Latches.

RESERVED

Bits 8-31: Reserved.

MCR

Modem control register

Offset: 0x10, reset: 0x00, access: read-write

2/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								CTSEN rw	RTSEN rw	RESERVED rw	LMS rw	RESERVED rw		RTSCTRL rw	DTRCTRL rw

Toggle Fields

DTRCTRL

Bit 0: Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active..

RTSCTRL

Bit 1: Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active..

RESERVED

Bits 2-3: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

LMS

Bit 4: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR..

RESERVED

Bit 5: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RTSEN

Bit 6: RTS enable.

Allowed values:
0: DISABLE_AUTO_RTS_FLO: Disable auto-rts flow control.
1: ENABLE_AUTO_RTS_FLOW: Enable auto-rts flow control.

CTSEN

Bit 7: CTS enable.

Allowed values:
0: DISABLE_AUTO_CTS_FLO: Disable auto-cts flow control.
1: ENABLE_AUTO_CTS_FLOW: Enable auto-cts flow control.

RESERVED

Bits 8-31: Reserved.

LSR

Line Status Register. Contains flags for transmit and receive status, including line errors.

Offset: 0x14, reset: 0x60, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								RXFE r	TEMT r	THRE r	BI r	FE r	PE r	OE r	RDR r

Toggle Fields

RDR

Bit 0: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty..

Allowed values:
0: RBR_IS_EMPTY_: RBR is empty.
1: RBR_CONTAINS_VALID: RBR contains valid data.

OE

Bit 1: Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost..

Allowed values:
0: INACTIVE: Overrun error status is inactive.
1: ACTIVE: Overrun error status is active.

PE

Bit 2: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO..

Allowed values:
0: INACTIVE: Parity error status is inactive.
1: ACTIVE: Parity error status is active.

FE

Bit 3: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO..

Allowed values:
0: INACTIVE: Framing error status is inactive.
1: ACTIVE: Framing error status is active.

BI

Bit 4: Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO..

Allowed values:
0: INACTIVE: Break interrupt status is inactive.
1: ACTIVE: Break interrupt status is active.

THRE

Bit 5: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write..

Allowed values:
0: VALID: THR contains valid data.
1: EMPTY: THR is empty.

TEMT

Bit 6: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data..

Allowed values:
0: VALID: THR and/or the TSR contains valid data.
1: EMPTY: THR and the TSR are empty.

RXFE

Bit 7: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO..

Allowed values:
0: NOERROR: RBR contains no UART RX errors or FCR[0]=0.
1: ERRORS: UART RBR contains at least one UART RX error.

RESERVED

Bits 8-31: Reserved.

MSR

Modem status register

Offset: 0x18, reset: 0x00, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								DCD r	RI r	DSR r	CTS r	DELTADCD r	TERI r	DELTADSR r	DELTACTS r

Toggle Fields

DELTACTS

Bit 0: Set upon state change of input CTS. Cleared on a MSR read..

Allowed values:
0: NO_STATE_CHANGE: No change detected on modem input CTS.
1: STATE_CHANGE_DETECTE: State change detected on modem input CTS.

DELTADSR

Bit 1: Set upon state change of input DSR. Cleared on a MSR read..

Allowed values:
0: NO_STATE_CHANGE: No change detected on modem input DSR.
1: STATE_CHANGE_DETECTE: State change detected on modem input DSR.

TERI

Bit 2: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read..

Allowed values:
0: NO_STATE_CHANGE: No change detected on modem input, RI.
1: LOW_TO_HIGH_TRANSITI: Low-to-high transition detected on RI.

DELTADCD

Bit 3: Set upon state change of input DCD. Cleared on a MSR read..

Allowed values:
0: NO_STATE_CHANGE: No change detected on modem input DCD.
1: STATE_CHANGE_DETECTE: State change detected on modem input DCD.

CTS

Bit 4: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode..

DSR

Bit 5: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode..

RI

Bit 6: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode..

DCD

Bit 7: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode..

RESERVED

Bits 8-31: Reserved.

SCR

Scratch Pad Register. Eight-bit temporary storage for software.

Offset: 0x1c, reset: 0x00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								Pad rw

Toggle Fields

Pad

Bits 0-7: A readable, writable byte..

RESERVED

Bits 8-31: Reserved.

ACR

Auto-baud Control Register. Contains controls for the auto-baud feature.

Offset: 0x20, reset: 0x00, access: read-write

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw						ABTOINTCLR rw	ABEOINTCLR rw	RESERVED rw					AUTORESTART rw	MODE rw	START rw

Toggle Fields

START

Bit 0: This bit is automatically cleared after auto-baud completion..

Allowed values:
0: AUTO_BAUD_STOP_AUTO: Auto-baud stop (auto-baud is not running).
1: AUTO_BAUD_START_AUT: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.

MODE

Bit 1: Auto-baud mode select bit..

Allowed values:
0: MODE_0_: Mode 0.
1: MODE_1_: Mode 1.

AUTORESTART

Bit 2: Auto restart.

Allowed values:
0: NO_RESTART: No restart
1: RESTART_IN_CASE_OF_T: Restart in case of time-out (counter restarts at next UART Rx falling edge)

RESERVED

Bits 3-7: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

ABEOINTCLR

Bit 8: End of auto-baud interrupt clear bit (write only accessible)..

Allowed values:
0: NOACTION: Writing a 0 has no impact.
1: CLEAR: Writing a 1 will clear the corresponding interrupt in the IIR.

ABTOINTCLR

Bit 9: Auto-baud time-out interrupt clear bit (write only accessible)..

Allowed values:
0: NOACTION: Writing a 0 has no impact.
1: CLEAR: Writing a 1 will clear the corresponding interrupt in the IIR.

RESERVED

Bits 10-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

FDR

Fractional Divider Register. Generates a clock input for the baud rate divider.

Offset: 0x28, reset: 0x10, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								MULVAL rw				DIVADDVAL rw

Toggle Fields

DIVADDVAL

Bits 0-3: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate..

MULVAL

Bits 4-7: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not..

RESERVED

Bits 8-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TER

Transmit Enable Register. Turns off UART transmitter for use with software flow control.

Offset: 0x30, reset: 0x80, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								TXEN rw	RESERVED rw

Toggle Fields

RESERVED

Bits 0-6: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TXEN

Bit 7: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character..

RESERVED

Bits 8-31: Reserved.

RS485CTRL

RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.

Offset: 0x4c, reset: 0x00, access: read-write

6/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw										OINV rw	DCTRL rw	SEL rw	AADEN rw	RXDIS rw	NMMEN rw

Toggle Fields

NMMEN

Bit 0: NMM enable.

Allowed values:
0: DISABLED: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
1: ENABLED: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.

RXDIS

Bit 1: Receiver enable.

Allowed values:
0: ENABLED: The receiver is enabled.
1: DISABLED: The receiver is disabled.

AADEN

Bit 2: AAD enable.

Allowed values:
0: DISABLED: Auto Address Detect (AAD) is disabled.
1: ENABLED: Auto Address Detect (AAD) is enabled.

SEL

Bit 3: Direction control pins select.

Allowed values:
0: RTS: If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.
1: DTR: If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.

DCTRL

Bit 4: Direction control enable.

Allowed values:
0: DISABLE_AUTO_DIRECTI: Disable Auto Direction Control.
1: ENABLE_AUTO_DIRECTIO: Enable Auto Direction Control.

OINV

Bit 5: This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin..

Allowed values:
0: LOW: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
1: HIGH: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.

RESERVED

Bits 6-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RS485ADRMATCH

RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.

Offset: 0x50, reset: 0x00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								ADRMATCH rw

Toggle Fields

ADRMATCH

Bits 0-7: Contains the address match value..

RESERVED

Bits 8-31: Reserved.

RS485DLY

RS-485/EIA-485 direction control delay.

Offset: 0x54, reset: 0x00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw								DLY rw

Toggle Fields

DLY

Bits 0-7: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter..

RESERVED

Bits 8-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

USB

0x40020000: USB device

27/81 fields covered. Toggle Registers

Show register map

Offset	Name	31	23	15	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DEVINTST	RESERVED		RESERVED	TxENDPKT	RxENDPKT	CD_FULL	CC_EMPTY	DEV_STAT	EP7	EP6	EP5	EP4	EP3	EP2	EP1	EP0	FRAME
0x4	DEVINTEN	RESERVED		RESERVED	TXENDPKT_EN	RXENDPKT_EN	CD_FULL_EN	CC_EMPTY_EN	DEV_STAT_EN	EP7_EN	EP6_EN	EP5_EN	EP4_EN	EP3_EN	EP2_EN	EP1_EN	EP0_EN	FRAME_EN
0x8	DEVINTCTRL	RESERVED		RESERVED	TXENDPKT_CLR	RXENDPKT_CLR	CD_FULL_CLR	CC_EMPTY_CLR	DEV_STAT_CLR	EP7_CLR	EP6_CLR	EP5_CLR	EP4_CLR	EP3_CLR	EP2_CLR	EP1_CLR	EP0_CLR	FRAME_CLR
0xc	DEVINTSET	RESERVED		RESERVED	TXENDPKT_SET	RXENDPKT_SET	CD_FULL_SET	CC_EMPTY_SET	DEV_STAT_SET	EP7_SET	EP6_SET	EP5_SET	EP4_SET	EP3_SET	EP2_SET	EP1_SET	EP0_SET	FRAME_SET
0x10	CMDCODE	RESERVED	CODE_WDATA	CMD_PHASE							RESERVED
0x14	CMDDATA	RESERVED		RESERVED							CMD_RDATA
0x18	RXDATA	RX_DATA		RX_DATA
0x1c	TXDATA	TX_DATA		TX_DATA
0x20	RXPLEN	RESERVED		RESERVED				DV	PKT_LNGTH
0x24	TXPLENn	RESERVED		RESERVED					PKT_LNGTH
0x28	CTRL	RESERVED		RESERVED									LOG_ENDPOINT				WR_EN	RD_EN
0x2c	DEVFIQSEL	RESERVED		RESERVED												BULKIN	BULKOUT	FRAME

DEVINTST

USB Device Interrupt Status

Offset: 0x0, reset: 0x00000010, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r		TxENDPKT r	RxENDPKT r	CD_FULL r	CC_EMPTY r	DEV_STAT r	EP7 r	EP6 r	EP5 r	EP4 r	EP3 r	EP2 r	EP1 r	EP0 r	FRAME r

Toggle Fields

FRAME

Bit 0: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0 = no interrupt. 1 = interrupt pending..

EP0

Bit 1: USB core interrupt for physical endpoint 0. 0 = no interrupt. 1 = interrupt pending..

EP1

Bit 2: USB core interrupt for physical endpoint 1. 0 = no interrupt. 1 = interrupt pending..

EP2

Bit 3: USB core interrupt for physical endpoint 2. 0 = no interrupt. 1 = interrupt pending..

EP3

Bit 4: USB core interrupt for physical endpoint 3. 0 = no interrupt. 1 = interrupt pending..

EP4

Bit 5: USB core interrupt for physical endpoint 4. 0 = no interrupt. 1 = interrupt pending..

EP5

Bit 6: USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending..

EP6

Bit 7: USB core interrupt for physical endpoint 6. 0 = no interrupt. 1 = interrupt pending..

EP7

Bit 8: USB core interrupt for physical endpoint 7. 0 = no interrupt. 1 = interrupt pending..

DEV_STAT

Bit 9: Set when USB Bus reset, USB suspend change, or Connect change event occurs. Refer to Section 10.11.7. 0 = no interrupt. 1 = interrupt pending..

CC_EMPTY

Bit 10: The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt. 1 = interrupt pending..

CD_FULL

Bit 11: Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt. 1 = interrupt pending..

RxENDPKT

Bit 12: The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt. 1 = interrupt pending..

TxENDPKT

Bit 13: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt. 1 = interrupt pending..

RESERVED

Bits 14-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DEVINTEN

USB Device Interrupt Enable

Offset: 0x4, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw		TXENDPKT_EN rw	RXENDPKT_EN rw	CD_FULL_EN rw	CC_EMPTY_EN rw	DEV_STAT_EN rw	EP7_EN rw	EP6_EN rw	EP5_EN rw	EP4_EN rw	EP3_EN rw	EP2_EN rw	EP1_EN rw	EP0_EN rw	FRAME_EN rw

Toggle Fields

FRAME_EN

Bit 0: Frame interrupt . For isochronous packet transfers. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP0_EN

Bit 1: USB core interrupt for physical endpoint 0. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP1_EN

Bit 2: USB core interrupt for physical endpoint 1. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP2_EN

Bit 3: USB core interrupt for physical endpoint 2. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP3_EN

Bit 4: USB core interrupt for physical endpoint 3. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP4_EN

Bit 5: USB core interrupt for physical endpoint 4. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP5_EN

Bit 6: USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending..

EP6_EN

Bit 7: USB core interrupt for physical endpoint 6. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

EP7_EN

Bit 8: USB core interrupt for physical endpoint 7. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

DEV_STAT_EN

Bit 9: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

CC_EMPTY_EN

Bit 10: The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

CD_FULL_EN

Bit 11: Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

RXENDPKT_EN

Bit 12: The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

TXENDPKT_EN

Bit 13: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set..

RESERVED

Bits 14-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DEVINTCTRL

USB Device Interrupt Clear

Offset: 0x8, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w		TXENDPKT_CLR w	RXENDPKT_CLR w	CD_FULL_CLR w	CC_EMPTY_CLR w	DEV_STAT_CLR w	EP7_CLR w	EP6_CLR w	EP5_CLR w	EP4_CLR w	EP3_CLR w	EP2_CLR w	EP1_CLR w	EP0_CLR w	FRAME_CLR w

Toggle Fields

FRAME_CLR

Bit 0: Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP0_CLR

Bit 1: USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP1_CLR

Bit 2: USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP2_CLR

Bit 3: USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP3_CLR

Bit 4: USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP4_CLR

Bit 5: USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP5_CLR

Bit 6: USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP6_CLR

Bit 7: USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

EP7_CLR

Bit 8: USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

DEV_STAT_CLR

Bit 9: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

CC_EMPTY_CLR

Bit 10: The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

CD_FULL_CLR

Bit 11: Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

RXENDPKT_CLR

Bit 12: The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

TXENDPKT_CLR

Bit 13: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared..

RESERVED

Bits 14-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DEVINTSET

USB Device Interrupt Set

Offset: 0xc, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w		TXENDPKT_SET w	RXENDPKT_SET w	CD_FULL_SET w	CC_EMPTY_SET w	DEV_STAT_SET w	EP7_SET w	EP6_SET w	EP5_SET w	EP4_SET w	EP3_SET w	EP2_SET w	EP1_SET w	EP0_SET w	FRAME_SET w

Toggle Fields

FRAME_SET

Bit 0: Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP0_SET

Bit 1: USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP1_SET

Bit 2: USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP2_SET

Bit 3: USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP3_SET

Bit 4: USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP4_SET

Bit 5: USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP5_SET

Bit 6: USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP6_SET

Bit 7: USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

EP7_SET

Bit 8: USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

DEV_STAT_SET

Bit 9: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

CC_EMPTY_SET

Bit 10: The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

CD_FULL_SET

Bit 11: Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

RXENDPKT_SET

Bit 12: The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set..

TXENDPKT_SET

RESERVED

Bits 14-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CMDCODE

USB Command Code

Offset: 0x10, reset: 0x00000000, access: write-only

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w								CODE_WDATA w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMD_PHASE w								RESERVED w

Toggle Fields

RESERVED

Bits 0-7: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CMD_PHASE

Bits 8-15: Command phase action.

Allowed values:
0x01: WRITE: Write
0x02: READ: Read
0x05: COMMAND: Command

CODE_WDATA

Bits 16-23: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)..

RESERVED

Bits 24-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CMDDATA

USB Command Data

Offset: 0x14, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r								CMD_RDATA r

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CMD_RDATA

Bits 0-7: Command Read Data..

RESERVED

Bits 8-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

RXDATA

USB Receive Data

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RX_DATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_DATA r

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RX_DATA

Bits 0-31: Data received..

TXDATA

USB Transmit Data

Offset: 0x1c, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TX_DATA w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TX_DATA w

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TX_DATA

Bits 0-31: Transmit Data..

RXPLEN

USB Receive Packet Length

Offset: 0x20, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED r					DV r	PKT_LNGTH r

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PKT_LNGTH

Bits 0-9: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt..

DV

Bit 10: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet..

Allowed values:
0: DATA_IS_INVALID_: Data is invalid.
1: DATA_IS_VALID_: Data is valid.

RESERVED

Bits 11-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

TXPLENn

USB Transmit Packet Length

Offset: 0x24, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w						PKT_LNGTH w

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PKT_LNGTH

Bits 0-9: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt..

RESERVED

Bits 10-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

CTRL

USB Control

Offset: 0x28, reset: 0x00000000, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw										LOG_ENDPOINT rw				WR_EN rw	RD_EN rw

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RD_EN

Bit 0: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData..

Allowed values:
0: READ_MODE_IS_DISABLE: Read mode is disabled.
1: READ_MODE_IS_ENABLED: Read mode is enabled.

WR_EN

Bit 1: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent..

Allowed values:
0: WRITE_MODE_IS_DISABL: Write mode is disabled.
1: WRITE_MODE_IS_ENABLE: Write mode is enabled.

LOG_ENDPOINT

Bits 2-5: Logical Endpoint number..

RESERVED

Bits 6-31: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined..

DEVFIQSEL

USB Device FIQ select

Offset: 0x2c, reset: 0x00, access: write-only

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w													BULKIN w	BULKOUT w	FRAME w

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FRAME

Bit 0: This interrupt comes from a 1 KHz free running clock resynchronized on the incoming SoF tokens. This is to be used for isochronous packet transfer..

Allowed values:
0: LOWPRIORITY: FRAME interrupt will be routed to the low-priority interrupt line IRQ.
1: HIGHPRIORITY: FRAME interrupt will be routed to the high-priority interrupt line FIQ.

BULKOUT

Bit 1: Interrupt routing for bulk out endpoints For logical endpoint 3 (physical endpoints 6 and 7) only..

Allowed values:
0: LOWPRIORITY: BULKOUT interrupt will be routed to the low-priority interrupt line IRQ.
1: HIGHPRIORITY: BULKOUT interrupt will be routed to the high-priority interrupt line FIQ.

BULKIN

Bit 2: Interrupt routing for bulk in endpoints For logical endpoint 3 (physical endpoints 6 and 7) only..

Allowed values:
0: LOWPRIORITY: BULKIN interrupt will be routed to the low-priority interrupt line IRQ.
1: HIGHPRIORITY: BULKIN interrupt will be routed to the high-priority interrupt line FIQ.

RESERVED

Bits 3-31: Reserved.

WWDT

0x40004000: Windowed WatchDog Timer (WWDT)

5/16 fields covered. Toggle Registers

Show register map

Offset	Name	31	23	15	9	7	4	3	2	1	0
0x0	MOD	RESERVED		RESERVED			WDPROTECT	WDINT	WDTOF	WDRESET	WDEN
0x4	TC	RESERVED	Count	Count
0x8	FEED	RESERVED		RESERVED		Feed
0xc	TV	RESERVED	Count	Count
0x14	WARNINT	RESERVED		RESERVED	WARNINT
0x18	WINDOW	RESERVED	WINDOW	WINDOW

MOD

Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.

Offset: 0x0, reset: 0, access: read-write

3/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw											WDPROTECT rw	WDINT rw	WDTOF rw	WDRESET rw	WDEN rw

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WDEN

Bit 0: Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to watchdog oscillator before setting this bit to one..

Allowed values:
0: STOP: The watchdog timer is stopped.
1: RUN: The watchdog timer is running.

WDRESET

Bit 1: Watchdog reset enable bit. This bit is Set Only..

Allowed values:
0: RESET: A watchdog timeout will not cause a chip reset.
1: INTERRUPT: A watchdog timeout will cause a chip reset.

WDTOF

Bit 2: Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1..

WDINT

Bit 3: Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software..

WDPROTECT

Bit 4: Watchdog update mode. This bit is Set Only..

Allowed values:
0: ANYTIME: The watchdog reload value (WDTC) can be changed at any time.
1: MATCH: The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1.

RESERVED

Bits 5-31: Reserved. Read value is undefined, only zero should be written..

TC

Watchdog timer constant register. This register determines the time-out value.

Offset: 0x4, reset: 0xFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw								Count rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Count rw

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Count

Bits 0-23: Watchdog time-out interval..

RESERVED

Bits 24-31: Reserved. Read value is undefined, only zero should be written..

FEED

Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.

Offset: 0x8, reset: 0, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED w								Feed w

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Feed

Bits 0-7: Feed value should be 0xAA followed by 0x55..

RESERVED

Bits 8-31: Reserved.

TV

Watchdog timer value register. This register reads out the current value of the Watchdog timer.

Offset: 0xc, reset: 0xFF, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED r								Count r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Count r

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Count

Bits 0-23: Counter timer value..

RESERVED

Bits 24-31: Reserved. Read value is undefined, only zero should be written..

WARNINT

Watchdog Warning Interrupt compare value.

Offset: 0x14, reset: 0, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED rw						WARNINT rw

Toggle Fields

WARNINT

Bits 0-9: Watchdog warning interrupt compare value..

RESERVED

Bits 10-31: Reserved. Read value is undefined, only zero should be written..

WINDOW

Watchdog Window compare value.

Offset: 0x18, reset: 0xFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED rw								WINDOW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WINDOW rw

Toggle Fields

WINDOW

Bits 0-23: Watchdog window value..

RESERVED

Bits 24-31: Reserved. Read value is undefined, only zero should be written..