0x400a0000: LPC5411x 12-bit ADC controller (ADC)
121/176 fields covered. Toggle Registers
Offset | Name | 31 |
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1 |
0 |
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0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | INSEL | ||||||||||||||||||||||||||||||||
0x8 | SEQ_CTRL[A] | ||||||||||||||||||||||||||||||||
0xc | SEQ_CTRL[B] | ||||||||||||||||||||||||||||||||
0x10 | SEQ_GDAT[A] | ||||||||||||||||||||||||||||||||
0x14 | SEQ_GDAT[B] | ||||||||||||||||||||||||||||||||
0x20 | DAT[[0]] | ||||||||||||||||||||||||||||||||
0x24 | DAT[[1]] | ||||||||||||||||||||||||||||||||
0x28 | DAT[[2]] | ||||||||||||||||||||||||||||||||
0x2c | DAT[[3]] | ||||||||||||||||||||||||||||||||
0x30 | DAT[[4]] | ||||||||||||||||||||||||||||||||
0x34 | DAT[[5]] | ||||||||||||||||||||||||||||||||
0x38 | DAT[[6]] | ||||||||||||||||||||||||||||||||
0x3c | DAT[[7]] | ||||||||||||||||||||||||||||||||
0x40 | DAT[[8]] | ||||||||||||||||||||||||||||||||
0x44 | DAT[[9]] | ||||||||||||||||||||||||||||||||
0x48 | DAT[[10]] | ||||||||||||||||||||||||||||||||
0x4c | DAT[[11]] | ||||||||||||||||||||||||||||||||
0x50 | THR0_LOW | ||||||||||||||||||||||||||||||||
0x54 | THR1_LOW | ||||||||||||||||||||||||||||||||
0x58 | THR0_HIGH | ||||||||||||||||||||||||||||||||
0x5c | THR1_HIGH | ||||||||||||||||||||||||||||||||
0x60 | CHAN_THRSEL | ||||||||||||||||||||||||||||||||
0x64 | INTEN | ||||||||||||||||||||||||||||||||
0x68 | FLAGS | ||||||||||||||||||||||||||||||||
0x6c | STARTUP | ||||||||||||||||||||||||||||||||
0x70 | CALIB |
ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.
Offset: 0x0, reset: 0x600, access: read-write
3/5 fields covered.
Bits 0-7: In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode..
Bit 8: Select clock mode..
Allowed values:
0: SYNCHRONOUS_MODE: Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.
0x1: ASYNCHRONOUS_MODE: Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
Bits 9-10: The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution.
Allowed values:
0: RESOLUTION_6_BIT: 6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
0x1: RESOLUTION_8_BIT: 8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
0x2: RESOLUTION_10_BIT: 10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
0x3: RESOLUTION_12_BIT: 12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
Bit 11: Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application..
Allowed values:
0: CALIBRATE: Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed.
0x1: BYPASS_CALIBRATION: Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
Bits 12-14: Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. See Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks..
Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0.
Offset: 0x4, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.
Offset: 0x8, reset: 0, access: read-write
5/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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SEQ_ENA
rw |
MODE
rw |
LOWPRIO
rw |
SINGLESTEP
rw |
BURST
rw |
START
rw |
SYNCBYPASS
rw |
TRIGPOL
rw |
TRIGGER
rw |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGGER
rw |
CHANNELS
rw |
Bits 0-11: Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write..
Bits 12-17: Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write..
Bit 18: Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write..
Allowed values:
0: NEGATIVE_EDGE: Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
0x1: POSITIVE_EDGE: Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
Bit 19: Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period..
Allowed values:
0: ENABLE_TRIGGER_SYNCH: Enable trigger synchronization. The hardware trigger bypass is not enabled.
0x1: BYPASS_TRIGGER_SYNCH: Bypass trigger synchronization. The hardware trigger bypass is enabled.
Bit 26: Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero..
Bit 27: Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared..
Bit 28: When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit..
Bit 29: Set priority for sequence A..
Allowed values:
0: LOW_PRIORITY: Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
0x1: HIGH_PRIORITY: High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.
Bit 30: Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below..
Allowed values:
0: END_OF_CONVERSION: End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.
0x1: END_OF_SEQUENCE: End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
Bit 31: Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled..
Allowed values:
0: DISABLED: Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
0x1: ENABLED: Enabled. Sequence n is enabled.
ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.
Offset: 0xc, reset: 0, access: read-write
5/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SEQ_ENA
rw |
MODE
rw |
LOWPRIO
rw |
SINGLESTEP
rw |
BURST
rw |
START
rw |
SYNCBYPASS
rw |
TRIGPOL
rw |
TRIGGER
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGGER
rw |
CHANNELS
rw |
Bits 0-11: Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write..
Bits 12-17: Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write..
Bit 18: Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write..
Allowed values:
0: NEGATIVE_EDGE: Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
0x1: POSITIVE_EDGE: Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
Bit 19: Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period..
Allowed values:
0: ENABLE_TRIGGER_SYNCH: Enable trigger synchronization. The hardware trigger bypass is not enabled.
0x1: BYPASS_TRIGGER_SYNCH: Bypass trigger synchronization. The hardware trigger bypass is enabled.
Bit 26: Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero..
Bit 27: Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared..
Bit 28: When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit..
Bit 29: Set priority for sequence A..
Allowed values:
0: LOW_PRIORITY: Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
0x1: HIGH_PRIORITY: High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.
Bit 30: Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below..
Allowed values:
0: END_OF_CONVERSION: End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.
0x1: END_OF_SEQUENCE: End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
Bit 31: Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled..
Allowed values:
0: DISABLED: Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
0x1: ENABLED: Enabled. Sequence n is enabled.
ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.
Offset: 0x10, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHN
r |
THCMPCROSS
r |
THCMPRANGE
r |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read..
Bit 30: This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)..
Bit 31: This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)..
ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.
Offset: 0x14, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHN
r |
THCMPCROSS
r |
THCMPRANGE
r |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read..
Bit 30: This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)..
Bit 31: This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x20, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x24, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x28, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x2c, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x30, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x34, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x38, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x3c, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x40, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x44, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x48, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
Offset: 0x4c, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAVALID
r |
OVERRUN
r |
CHANNEL
r |
THCMPCROSS
r |
THCMPRANGE
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT
r |
Bits 4-15: This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP..
Bits 16-17: Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved..
Bits 18-19: Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold..
Bit 30: This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
Bit 31: This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled..
ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRLOW
rw |
ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
Offset: 0x54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRLOW
rw |
ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
Offset: 0x58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRHIGH
rw |
ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRHIGH
rw |
ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel
Offset: 0x60, reset: 0, access: read-write
1/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH11_THRSEL
rw |
CH10_THRSEL
rw |
CH9_THRSEL
rw |
CH8_THRSEL
rw |
CH7_THRSEL
rw |
CH6_THRSEL
rw |
CH5_THRSEL
rw |
CH4_THRSEL
rw |
CH3_THRSEL
rw |
CH2_THRSEL
rw |
CH1_THRSEL
rw |
CH0_THRSEL
rw |
Bit 0: Threshold select for channel 0..
Allowed values:
0: THRESHOLD0: Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
0x1: THRESHOLD1: Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
Offset: 0x64, reset: 0, access: read-write
4/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADCMPINTEN11
rw |
ADCMPINTEN10
rw |
ADCMPINTEN9
rw |
ADCMPINTEN8
rw |
ADCMPINTEN7
rw |
ADCMPINTEN6
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCMPINTEN6
rw |
ADCMPINTEN5
rw |
ADCMPINTEN4
rw |
ADCMPINTEN3
rw |
ADCMPINTEN2
rw |
ADCMPINTEN1
rw |
ADCMPINTEN0
rw |
OVR_INTEN
rw |
SEQB_INTEN
rw |
SEQA_INTEN
rw |
Bit 0: Sequence A interrupt enable..
Allowed values:
0: DISABLED: Disabled. The sequence A interrupt/DMA trigger is disabled.
0x1: ENABLED: Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.
Bit 1: Sequence B interrupt enable..
Allowed values:
0: DISABLED: Disabled. The sequence B interrupt/DMA trigger is disabled.
0x1: ENABLED: Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.
Bit 2: Overrun interrupt enable..
Allowed values:
0: DISABLED: Disabled. The overrun interrupt is disabled.
0x1: ENABLED: Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.
ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
Offset: 0x68, reset: 0, access: read-write
18/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OVR_INT
r |
THCMP_INT
r |
SEQB_INT
r |
SEQA_INT
r |
SEQB_OVR
r |
SEQA_OVR
r |
OVERRUN11
r |
OVERRUN10
r |
OVERRUN9
r |
OVERRUN8
r |
OVERRUN7
r |
OVERRUN6
r |
OVERRUN5
r |
OVERRUN4
r |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVERRUN3
r |
OVERRUN2
r |
OVERRUN1
r |
OVERRUN0
r |
THCMP11
rw |
THCMP10
rw |
THCMP9
rw |
THCMP8
rw |
THCMP7
rw |
THCMP6
rw |
THCMP5
rw |
THCMP4
rw |
THCMP3
rw |
THCMP2
rw |
THCMP1
rw |
THCMP0
rw |
Bit 28: Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register..
Bit 29: Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register..
Bit 30: Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits..
Bit 31: Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers..
ADC Startup register.
Offset: 0x6c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_INIT
rw |
ADC_ENA
rw |
Bit 1: ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is required if a calibration is not performed. It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required. It should not be set during the same write that sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically when the 'dummy' conversion cycle completes..
ADC Calibration register.
Offset: 0x70, reset: 0x2, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CALVALUE
rw |
CALREQD
rw |
CALIB
rw |
Bit 1: Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration..
0x40040000: LPC5411x Asynchronous system configuration (ASYNC_SYSCON)
1/9 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ASYNCPRESETCTRL | ||||||||||||||||||||||||||||||||
0x4 | ASYNCPRESETCTRLSET | ||||||||||||||||||||||||||||||||
0x8 | ASYNCPRESETCTRLCLR | ||||||||||||||||||||||||||||||||
0x10 | ASYNCAPBCLKCTRL | ||||||||||||||||||||||||||||||||
0x14 | ASYNCAPBCLKCTRLSET | ||||||||||||||||||||||||||||||||
0x18 | ASYNCAPBCLKCTRLCLR | ||||||||||||||||||||||||||||||||
0x20 | ASYNCAPBCLKSELA |
Async peripheral reset control
Offset: 0x0, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTIMER4
rw |
CTIMER3
rw |
Set bits in ASYNCPRESETCTRL
Offset: 0x4, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARST_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARST_SET
w |
Clear bits in ASYNCPRESETCTRL
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARST_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARST_CLR
w |
Async peripheral clock control
Offset: 0x10, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTIMER4
rw |
CTIMER3
rw |
Set bits in ASYNCAPBCLKCTRL
Offset: 0x14, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACLK_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACLK_SET
w |
Clear bits in ASYNCAPBCLKCTRL
Offset: 0x18, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACLK_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACLK_CLR
w |
Async APB clock source select A
Offset: 0x20, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
0x4009d000: LPC5460x Controller Area Network Flexible Data
30/209 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xc | DBTP | ||||||||||||||||||||||||||||||||
0x10 | TEST | ||||||||||||||||||||||||||||||||
0x18 | CCCR | ||||||||||||||||||||||||||||||||
0x1c | NBTP | ||||||||||||||||||||||||||||||||
0x20 | TSCC | ||||||||||||||||||||||||||||||||
0x24 | TSCV | ||||||||||||||||||||||||||||||||
0x28 | TOCC | ||||||||||||||||||||||||||||||||
0x2c | TOCV | ||||||||||||||||||||||||||||||||
0x40 | ECR | ||||||||||||||||||||||||||||||||
0x44 | PSR | ||||||||||||||||||||||||||||||||
0x48 | TDCR | ||||||||||||||||||||||||||||||||
0x50 | IR | ||||||||||||||||||||||||||||||||
0x54 | IE | ||||||||||||||||||||||||||||||||
0x58 | ILS | ||||||||||||||||||||||||||||||||
0x5c | ILE | ||||||||||||||||||||||||||||||||
0x80 | GFC | ||||||||||||||||||||||||||||||||
0x84 | SIDFC | ||||||||||||||||||||||||||||||||
0x88 | XIDFC | ||||||||||||||||||||||||||||||||
0x90 | XIDAM | ||||||||||||||||||||||||||||||||
0x94 | HPMS | ||||||||||||||||||||||||||||||||
0x98 | NDAT1 | ||||||||||||||||||||||||||||||||
0x9c | NDAT2 | ||||||||||||||||||||||||||||||||
0xa0 | RXF0C | ||||||||||||||||||||||||||||||||
0xa4 | RXF0S | ||||||||||||||||||||||||||||||||
0xa8 | RXF0A | ||||||||||||||||||||||||||||||||
0xac | RXBC | ||||||||||||||||||||||||||||||||
0xb0 | RXF1C | ||||||||||||||||||||||||||||||||
0xb4 | RXF1S | ||||||||||||||||||||||||||||||||
0xb8 | RXF1A | ||||||||||||||||||||||||||||||||
0xbc | RXESC | ||||||||||||||||||||||||||||||||
0xc0 | TXBC | ||||||||||||||||||||||||||||||||
0xc4 | TXFQS | ||||||||||||||||||||||||||||||||
0xc8 | TXESC | ||||||||||||||||||||||||||||||||
0xcc | TXBRP | ||||||||||||||||||||||||||||||||
0xd0 | TXBAR | ||||||||||||||||||||||||||||||||
0xd4 | TXBCR | ||||||||||||||||||||||||||||||||
0xd8 | TXBTO | ||||||||||||||||||||||||||||||||
0xdc | TXBCF | ||||||||||||||||||||||||||||||||
0xe0 | TXBTIE | ||||||||||||||||||||||||||||||||
0xe4 | TXBCIE | ||||||||||||||||||||||||||||||||
0xf0 | TXEFC | ||||||||||||||||||||||||||||||||
0xf4 | TXEFS | ||||||||||||||||||||||||||||||||
0xf8 | TXEFA | ||||||||||||||||||||||||||||||||
0x200 | MRBA | ||||||||||||||||||||||||||||||||
0x400 | ETSCC | ||||||||||||||||||||||||||||||||
0x600 | ETSCV |
Test Register
Offset: 0x10, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX
rw |
TX
rw |
LBCK
rw |
Nominal Bit Timing and Prescaler Register
Offset: 0x1c, reset: 0x6000A03, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NSJW
rw |
NBRP
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NTSEG1
rw |
NTSEG2
rw |
Timestamp Counter Configuration
Offset: 0x20, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSS
rw |
Timestamp Counter Value
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSC
rw |
Timeout Counter Configuration
Offset: 0x28, reset: 0xFFFF0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TOP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOS
rw |
ETOC
rw |
Timeout Counter Value
Offset: 0x2c, reset: 0xFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOC
r |
Error Counter Register
Offset: 0x40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RP
r |
REC
r |
TEC
r |
Transmitter Delay Compensator Register
Offset: 0x48, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDCO
rw |
TDCF
rw |
Interrupt Register
Offset: 0x50, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARA
rw |
PED
rw |
PEA
rw |
WDI
rw |
BO
rw |
EW
rw |
EP
rw |
ELO
rw |
BEU
rw |
BEC
rw |
DRX
rw |
TOO
rw |
MRAF
rw |
TSW
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFL
rw |
TEFF
rw |
TEFW
rw |
TEFN
rw |
TFE
rw |
TCF
rw |
TC
rw |
HPM
rw |
RF1L
rw |
RF1F
rw |
RF1W
rw |
RF1N
rw |
RF0L
rw |
RF0F
rw |
RF0W
rw |
RF0N
rw |
Interrupt Enable
Offset: 0x54, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARAE
rw |
PEDE
rw |
PEAE
rw |
WDIE
rw |
BOE
rw |
EWE
rw |
EPE
rw |
ELOE
rw |
BEUE
rw |
BECE
rw |
DRXE
rw |
TOOE
rw |
MRAFE
rw |
TSWE
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFLE
rw |
TEFFE
rw |
TEFWE
rw |
TEFNE
rw |
TFEE
rw |
TCFE
rw |
TCE
rw |
HPME
rw |
RF1LE
rw |
RF1FE
rw |
RF1WE
rw |
RF1NE
rw |
RF0LE
rw |
RF0FE
rw |
RF0WE
rw |
RF0NE
rw |
Interrupt Line Select
Offset: 0x58, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARAL
rw |
PEDL
rw |
PEAL
rw |
WDIL
rw |
BOL
rw |
EWL
rw |
EPL
rw |
ELOL
rw |
BEUL
rw |
BECL
rw |
DRXL
rw |
TOOL
rw |
MRAFL
rw |
TSWL
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFLL
rw |
TEFFL
rw |
TEFWL
rw |
TEFNL
rw |
TFEL
rw |
TCFL
rw |
TCL
rw |
HPML
rw |
RF1LL
rw |
RF1FL
rw |
RF1WL
rw |
RF1NL
rw |
RF0LL
rw |
RF0FL
rw |
RF0WL
rw |
RF0NL
rw |
Interrupt Line Enable
Offset: 0x5c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EINT1
rw |
EINT0
rw |
Global Filter Configuration
Offset: 0x80, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ANFS
rw |
ANFE
rw |
RRFS
rw |
RRFE
rw |
Standard ID Filter Configuration
Offset: 0x84, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLSSA
rw |
Extended ID Filter Configuration
Offset: 0x88, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLESA
rw |
Extended ID AND Mask
Offset: 0x90, reset: 0x1FFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EIDM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EIDM
rw |
High Priority Message Status
Offset: 0x94, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLST
r |
FIDX
r |
MSI
r |
BIDX
r |
New Data 1
Offset: 0x98, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ND
rw |
New Data 2
Offset: 0x9c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ND
rw |
Rx FIFO 0 Configuration
Offset: 0xa0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
F0OM
rw |
F0WM
rw |
F0S
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F0SA
rw |
Rx FIFO 0 Acknowledge
Offset: 0xa8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F0AI
rw |
Rx Buffer Configuration
Offset: 0xac, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBSA
rw |
Rx FIFO 1 Configuration
Offset: 0xb0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
F1OM
rw |
F1WM
rw |
F1S
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F1SA
rw |
Rx FIFO 1 Acknowledge
Offset: 0xb8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F1AI
rw |
Rx Buffer and FIFO Element Size Configuration
Offset: 0xbc, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBDS
rw |
F1DS
rw |
F0DS
rw |
Tx Buffer Configuration
Offset: 0xc0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TFQM
rw |
TFQS
rw |
NDTB
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBSA
rw |
Tx FIFO/Queue Status
Offset: 0xc4, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TFQF
rw |
TFQPI
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TFGI
rw |
Tx Buffer Element Size Configuration
Offset: 0xc8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBDS
rw |
Tx Buffer Request Pending
Offset: 0xcc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRP
rw |
Tx Buffer Add Request
Offset: 0xd0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AR
rw |
Tx Buffer Cancellation Request
Offset: 0xd4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CR
rw |
Tx Buffer Transmission Occurred
Offset: 0xd8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
Tx Buffer Cancellation Finished
Offset: 0xdc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
Tx Buffer Transmission Interrupt Enable
Offset: 0xe0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TIE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIE
rw |
Tx Buffer Cancellation Finished Interrupt Enable
Offset: 0xe4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CFIE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CFIE
rw |
Tx Event FIFO Configuration
Offset: 0xf0, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EFWM
rw |
EFS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFSA
rw |
Tx Event FIFO Acknowledge
Offset: 0xf8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFAI
rw |
CAN Message RAM Base Address
Offset: 0x200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
External Timestamp Counter Configuration
Offset: 0x400, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETCE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETCP
rw |
External Timestamp Counter Value
Offset: 0x600, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETSC
rw |
0x4009e000: LPC5460x Controller Area Network Flexible Data
30/209 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xc | DBTP | ||||||||||||||||||||||||||||||||
0x10 | TEST | ||||||||||||||||||||||||||||||||
0x18 | CCCR | ||||||||||||||||||||||||||||||||
0x1c | NBTP | ||||||||||||||||||||||||||||||||
0x20 | TSCC | ||||||||||||||||||||||||||||||||
0x24 | TSCV | ||||||||||||||||||||||||||||||||
0x28 | TOCC | ||||||||||||||||||||||||||||||||
0x2c | TOCV | ||||||||||||||||||||||||||||||||
0x40 | ECR | ||||||||||||||||||||||||||||||||
0x44 | PSR | ||||||||||||||||||||||||||||||||
0x48 | TDCR | ||||||||||||||||||||||||||||||||
0x50 | IR | ||||||||||||||||||||||||||||||||
0x54 | IE | ||||||||||||||||||||||||||||||||
0x58 | ILS | ||||||||||||||||||||||||||||||||
0x5c | ILE | ||||||||||||||||||||||||||||||||
0x80 | GFC | ||||||||||||||||||||||||||||||||
0x84 | SIDFC | ||||||||||||||||||||||||||||||||
0x88 | XIDFC | ||||||||||||||||||||||||||||||||
0x90 | XIDAM | ||||||||||||||||||||||||||||||||
0x94 | HPMS | ||||||||||||||||||||||||||||||||
0x98 | NDAT1 | ||||||||||||||||||||||||||||||||
0x9c | NDAT2 | ||||||||||||||||||||||||||||||||
0xa0 | RXF0C | ||||||||||||||||||||||||||||||||
0xa4 | RXF0S | ||||||||||||||||||||||||||||||||
0xa8 | RXF0A | ||||||||||||||||||||||||||||||||
0xac | RXBC | ||||||||||||||||||||||||||||||||
0xb0 | RXF1C | ||||||||||||||||||||||||||||||||
0xb4 | RXF1S | ||||||||||||||||||||||||||||||||
0xb8 | RXF1A | ||||||||||||||||||||||||||||||||
0xbc | RXESC | ||||||||||||||||||||||||||||||||
0xc0 | TXBC | ||||||||||||||||||||||||||||||||
0xc4 | TXFQS | ||||||||||||||||||||||||||||||||
0xc8 | TXESC | ||||||||||||||||||||||||||||||||
0xcc | TXBRP | ||||||||||||||||||||||||||||||||
0xd0 | TXBAR | ||||||||||||||||||||||||||||||||
0xd4 | TXBCR | ||||||||||||||||||||||||||||||||
0xd8 | TXBTO | ||||||||||||||||||||||||||||||||
0xdc | TXBCF | ||||||||||||||||||||||||||||||||
0xe0 | TXBTIE | ||||||||||||||||||||||||||||||||
0xe4 | TXBCIE | ||||||||||||||||||||||||||||||||
0xf0 | TXEFC | ||||||||||||||||||||||||||||||||
0xf4 | TXEFS | ||||||||||||||||||||||||||||||||
0xf8 | TXEFA | ||||||||||||||||||||||||||||||||
0x200 | MRBA | ||||||||||||||||||||||||||||||||
0x400 | ETSCC | ||||||||||||||||||||||||||||||||
0x600 | ETSCV |
Test Register
Offset: 0x10, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX
rw |
TX
rw |
LBCK
rw |
Nominal Bit Timing and Prescaler Register
Offset: 0x1c, reset: 0x6000A03, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NSJW
rw |
NBRP
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NTSEG1
rw |
NTSEG2
rw |
Timestamp Counter Configuration
Offset: 0x20, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSS
rw |
Timestamp Counter Value
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSC
rw |
Timeout Counter Configuration
Offset: 0x28, reset: 0xFFFF0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TOP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOS
rw |
ETOC
rw |
Timeout Counter Value
Offset: 0x2c, reset: 0xFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOC
r |
Error Counter Register
Offset: 0x40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RP
r |
REC
r |
TEC
r |
Transmitter Delay Compensator Register
Offset: 0x48, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDCO
rw |
TDCF
rw |
Interrupt Register
Offset: 0x50, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARA
rw |
PED
rw |
PEA
rw |
WDI
rw |
BO
rw |
EW
rw |
EP
rw |
ELO
rw |
BEU
rw |
BEC
rw |
DRX
rw |
TOO
rw |
MRAF
rw |
TSW
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFL
rw |
TEFF
rw |
TEFW
rw |
TEFN
rw |
TFE
rw |
TCF
rw |
TC
rw |
HPM
rw |
RF1L
rw |
RF1F
rw |
RF1W
rw |
RF1N
rw |
RF0L
rw |
RF0F
rw |
RF0W
rw |
RF0N
rw |
Interrupt Enable
Offset: 0x54, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARAE
rw |
PEDE
rw |
PEAE
rw |
WDIE
rw |
BOE
rw |
EWE
rw |
EPE
rw |
ELOE
rw |
BEUE
rw |
BECE
rw |
DRXE
rw |
TOOE
rw |
MRAFE
rw |
TSWE
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFLE
rw |
TEFFE
rw |
TEFWE
rw |
TEFNE
rw |
TFEE
rw |
TCFE
rw |
TCE
rw |
HPME
rw |
RF1LE
rw |
RF1FE
rw |
RF1WE
rw |
RF1NE
rw |
RF0LE
rw |
RF0FE
rw |
RF0WE
rw |
RF0NE
rw |
Interrupt Line Select
Offset: 0x58, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARAL
rw |
PEDL
rw |
PEAL
rw |
WDIL
rw |
BOL
rw |
EWL
rw |
EPL
rw |
ELOL
rw |
BEUL
rw |
BECL
rw |
DRXL
rw |
TOOL
rw |
MRAFL
rw |
TSWL
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEFLL
rw |
TEFFL
rw |
TEFWL
rw |
TEFNL
rw |
TFEL
rw |
TCFL
rw |
TCL
rw |
HPML
rw |
RF1LL
rw |
RF1FL
rw |
RF1WL
rw |
RF1NL
rw |
RF0LL
rw |
RF0FL
rw |
RF0WL
rw |
RF0NL
rw |
Interrupt Line Enable
Offset: 0x5c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EINT1
rw |
EINT0
rw |
Global Filter Configuration
Offset: 0x80, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ANFS
rw |
ANFE
rw |
RRFS
rw |
RRFE
rw |
Standard ID Filter Configuration
Offset: 0x84, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLSSA
rw |
Extended ID Filter Configuration
Offset: 0x88, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLESA
rw |
Extended ID AND Mask
Offset: 0x90, reset: 0x1FFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EIDM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EIDM
rw |
High Priority Message Status
Offset: 0x94, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLST
r |
FIDX
r |
MSI
r |
BIDX
r |
New Data 1
Offset: 0x98, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ND
rw |
New Data 2
Offset: 0x9c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ND
rw |
Rx FIFO 0 Configuration
Offset: 0xa0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
F0OM
rw |
F0WM
rw |
F0S
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F0SA
rw |
Rx FIFO 0 Acknowledge
Offset: 0xa8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F0AI
rw |
Rx Buffer Configuration
Offset: 0xac, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBSA
rw |
Rx FIFO 1 Configuration
Offset: 0xb0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
F1OM
rw |
F1WM
rw |
F1S
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F1SA
rw |
Rx FIFO 1 Acknowledge
Offset: 0xb8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F1AI
rw |
Rx Buffer and FIFO Element Size Configuration
Offset: 0xbc, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBDS
rw |
F1DS
rw |
F0DS
rw |
Tx Buffer Configuration
Offset: 0xc0, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TFQM
rw |
TFQS
rw |
NDTB
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBSA
rw |
Tx FIFO/Queue Status
Offset: 0xc4, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TFQF
rw |
TFQPI
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TFGI
rw |
Tx Buffer Element Size Configuration
Offset: 0xc8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBDS
rw |
Tx Buffer Request Pending
Offset: 0xcc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRP
rw |
Tx Buffer Add Request
Offset: 0xd0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AR
rw |
Tx Buffer Cancellation Request
Offset: 0xd4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CR
rw |
Tx Buffer Transmission Occurred
Offset: 0xd8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
Tx Buffer Cancellation Finished
Offset: 0xdc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
Tx Buffer Transmission Interrupt Enable
Offset: 0xe0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TIE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIE
rw |
Tx Buffer Cancellation Finished Interrupt Enable
Offset: 0xe4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CFIE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CFIE
rw |
Tx Event FIFO Configuration
Offset: 0xf0, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EFWM
rw |
EFS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFSA
rw |
Tx Event FIFO Acknowledge
Offset: 0xf8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFAI
rw |
CAN Message RAM Base Address
Offset: 0x200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
External Timestamp Counter Configuration
Offset: 0x400, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETCE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETCP
rw |
External Timestamp Counter Value
Offset: 0x600, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETSC
rw |
0x40095000: LPC5411x CRC engine
1/11 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODE | ||||||||||||||||||||||||||||||||
0x4 | SEED | ||||||||||||||||||||||||||||||||
0x8 | DATA | ||||||||||||||||||||||||||||||||
0x8 | DATA16 | ||||||||||||||||||||||||||||||||
0x8 | DATA32 | ||||||||||||||||||||||||||||||||
0x8 | DATA8 | ||||||||||||||||||||||||||||||||
0x8 | SUM |
CRC mode
Offset: 0x0, reset: 0, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPL_SUM
rw |
BIT_RVS_SUM
rw |
CMPL_WR
rw |
BIT_RVS_WR
rw |
CRC_POLY
rw |
CRC seed
Offset: 0x4, reset: 65535, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRC_SEED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_SEED
rw |
Data written to this register will be taken to perform CRC calculation with selected bit order and 1’s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRC_WR_DATA
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_WR_DATA
w |
Data register - half-word sized
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA16
w |
Data register - word sized
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA32
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA32
w |
Data register - byte sized
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA8
w |
The most recent CRC sum can be read through this register with selected bit order and 1’s complement post-processes.
Offset: 0x8, reset: 65535, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRC_SUM
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_SUM
r |
0x40008000: LPC5411x Standard counter/timers (CTIMER0 to 4)
17/69 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IR | ||||||||||||||||||||||||||||||||
0x4 | TCR | ||||||||||||||||||||||||||||||||
0x8 | TC | ||||||||||||||||||||||||||||||||
0xc | PR | ||||||||||||||||||||||||||||||||
0x10 | PC | ||||||||||||||||||||||||||||||||
0x14 | MCR | ||||||||||||||||||||||||||||||||
0x18 | MR[[0]] | ||||||||||||||||||||||||||||||||
0x1c | MR[[1]] | ||||||||||||||||||||||||||||||||
0x20 | MR[[2]] | ||||||||||||||||||||||||||||||||
0x24 | MR[[3]] | ||||||||||||||||||||||||||||||||
0x28 | CCR | ||||||||||||||||||||||||||||||||
0x2c | CR[[0]] | ||||||||||||||||||||||||||||||||
0x30 | CR[[1]] | ||||||||||||||||||||||||||||||||
0x34 | CR[[2]] | ||||||||||||||||||||||||||||||||
0x38 | CR[[3]] | ||||||||||||||||||||||||||||||||
0x3c | EMR | ||||||||||||||||||||||||||||||||
0x70 | CTCR | ||||||||||||||||||||||||||||||||
0x74 | PWMC | ||||||||||||||||||||||||||||||||
0x78 | MSR[[0]] | ||||||||||||||||||||||||||||||||
0x7c | MSR[[1]] | ||||||||||||||||||||||||||||||||
0x80 | MSR[[2]] | ||||||||||||||||||||||||||||||||
0x84 | MSR[[3]] |
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
Offset: 0x4, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRST
rw |
CEN
rw |
Timer Counter
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCVAL
rw |
Prescale Register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRVAL
rw |
Prescale Counter
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCVAL
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
External Match Register. The EMR controls the match function and the external match pins.
Offset: 0x3c, reset: 0, access: read-write
4/8 fields covered.
Bit 0: External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 1: External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 2: External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 3: External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Offset: 0x70, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELCC
rw |
ENCC
rw |
CINSEL
rw |
CTMODE
rw |
Bits 0-1: Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register..
Allowed values:
0: TIMER: Timer Mode. Incremented every rising APB bus clock edge.
0x1: COUNTER_RISING_EDGE: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: COUNTER_FALLING_EDGE: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: COUNTER_DUAL_EDGE: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Bits 2-3: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer..
Allowed values:
0: CHANNEL_0: Channel 0. CAPn.0 for CTIMERn
0x1: CHANNEL_1: Channel 1. CAPn.1 for CTIMERn
0x2: CHANNEL_2: Channel 2. CAPn.2 for CTIMERn
0x3: CHANNEL_3: Channel 3. CAPn.3 for CTIMERn
Bits 5-7: Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved..
Allowed values:
0: CHANNEL_0_RISING: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1: CHANNEL_0_FALLING: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2: CHANNEL_1_RISING: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3: CHANNEL_1_FALLING: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4: CHANNEL_2_RISING: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5: CHANNEL_2_FALLING: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
Offset: 0x74, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMEN3
rw |
PWMEN2
rw |
PWMEN1
rw |
PWMEN0
rw |
Match Shadow Register
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
0x40009000: LPC5411x Standard counter/timers (CTIMER0 to 4)
17/69 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IR | ||||||||||||||||||||||||||||||||
0x4 | TCR | ||||||||||||||||||||||||||||||||
0x8 | TC | ||||||||||||||||||||||||||||||||
0xc | PR | ||||||||||||||||||||||||||||||||
0x10 | PC | ||||||||||||||||||||||||||||||||
0x14 | MCR | ||||||||||||||||||||||||||||||||
0x18 | MR[[0]] | ||||||||||||||||||||||||||||||||
0x1c | MR[[1]] | ||||||||||||||||||||||||||||||||
0x20 | MR[[2]] | ||||||||||||||||||||||||||||||||
0x24 | MR[[3]] | ||||||||||||||||||||||||||||||||
0x28 | CCR | ||||||||||||||||||||||||||||||||
0x2c | CR[[0]] | ||||||||||||||||||||||||||||||||
0x30 | CR[[1]] | ||||||||||||||||||||||||||||||||
0x34 | CR[[2]] | ||||||||||||||||||||||||||||||||
0x38 | CR[[3]] | ||||||||||||||||||||||||||||||||
0x3c | EMR | ||||||||||||||||||||||||||||||||
0x70 | CTCR | ||||||||||||||||||||||||||||||||
0x74 | PWMC | ||||||||||||||||||||||||||||||||
0x78 | MSR[[0]] | ||||||||||||||||||||||||||||||||
0x7c | MSR[[1]] | ||||||||||||||||||||||||||||||||
0x80 | MSR[[2]] | ||||||||||||||||||||||||||||||||
0x84 | MSR[[3]] |
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
Offset: 0x4, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRST
rw |
CEN
rw |
Timer Counter
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCVAL
rw |
Prescale Register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRVAL
rw |
Prescale Counter
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCVAL
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
External Match Register. The EMR controls the match function and the external match pins.
Offset: 0x3c, reset: 0, access: read-write
4/8 fields covered.
Bit 0: External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 1: External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 2: External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 3: External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Offset: 0x70, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELCC
rw |
ENCC
rw |
CINSEL
rw |
CTMODE
rw |
Bits 0-1: Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register..
Allowed values:
0: TIMER: Timer Mode. Incremented every rising APB bus clock edge.
0x1: COUNTER_RISING_EDGE: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: COUNTER_FALLING_EDGE: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: COUNTER_DUAL_EDGE: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Bits 2-3: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer..
Allowed values:
0: CHANNEL_0: Channel 0. CAPn.0 for CTIMERn
0x1: CHANNEL_1: Channel 1. CAPn.1 for CTIMERn
0x2: CHANNEL_2: Channel 2. CAPn.2 for CTIMERn
0x3: CHANNEL_3: Channel 3. CAPn.3 for CTIMERn
Bits 5-7: Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved..
Allowed values:
0: CHANNEL_0_RISING: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1: CHANNEL_0_FALLING: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2: CHANNEL_1_RISING: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3: CHANNEL_1_FALLING: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4: CHANNEL_2_RISING: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5: CHANNEL_2_FALLING: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
Offset: 0x74, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMEN3
rw |
PWMEN2
rw |
PWMEN1
rw |
PWMEN0
rw |
Match Shadow Register
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
0x40028000: LPC5411x Standard counter/timers (CTIMER0 to 4)
17/69 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IR | ||||||||||||||||||||||||||||||||
0x4 | TCR | ||||||||||||||||||||||||||||||||
0x8 | TC | ||||||||||||||||||||||||||||||||
0xc | PR | ||||||||||||||||||||||||||||||||
0x10 | PC | ||||||||||||||||||||||||||||||||
0x14 | MCR | ||||||||||||||||||||||||||||||||
0x18 | MR[[0]] | ||||||||||||||||||||||||||||||||
0x1c | MR[[1]] | ||||||||||||||||||||||||||||||||
0x20 | MR[[2]] | ||||||||||||||||||||||||||||||||
0x24 | MR[[3]] | ||||||||||||||||||||||||||||||||
0x28 | CCR | ||||||||||||||||||||||||||||||||
0x2c | CR[[0]] | ||||||||||||||||||||||||||||||||
0x30 | CR[[1]] | ||||||||||||||||||||||||||||||||
0x34 | CR[[2]] | ||||||||||||||||||||||||||||||||
0x38 | CR[[3]] | ||||||||||||||||||||||||||||||||
0x3c | EMR | ||||||||||||||||||||||||||||||||
0x70 | CTCR | ||||||||||||||||||||||||||||||||
0x74 | PWMC | ||||||||||||||||||||||||||||||||
0x78 | MSR[[0]] | ||||||||||||||||||||||||||||||||
0x7c | MSR[[1]] | ||||||||||||||||||||||||||||||||
0x80 | MSR[[2]] | ||||||||||||||||||||||||||||||||
0x84 | MSR[[3]] |
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
Offset: 0x4, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRST
rw |
CEN
rw |
Timer Counter
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCVAL
rw |
Prescale Register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRVAL
rw |
Prescale Counter
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCVAL
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
External Match Register. The EMR controls the match function and the external match pins.
Offset: 0x3c, reset: 0, access: read-write
4/8 fields covered.
Bit 0: External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 1: External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 2: External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 3: External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Offset: 0x70, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELCC
rw |
ENCC
rw |
CINSEL
rw |
CTMODE
rw |
Bits 0-1: Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register..
Allowed values:
0: TIMER: Timer Mode. Incremented every rising APB bus clock edge.
0x1: COUNTER_RISING_EDGE: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: COUNTER_FALLING_EDGE: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: COUNTER_DUAL_EDGE: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Bits 2-3: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer..
Allowed values:
0: CHANNEL_0: Channel 0. CAPn.0 for CTIMERn
0x1: CHANNEL_1: Channel 1. CAPn.1 for CTIMERn
0x2: CHANNEL_2: Channel 2. CAPn.2 for CTIMERn
0x3: CHANNEL_3: Channel 3. CAPn.3 for CTIMERn
Bits 5-7: Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved..
Allowed values:
0: CHANNEL_0_RISING: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1: CHANNEL_0_FALLING: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2: CHANNEL_1_RISING: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3: CHANNEL_1_FALLING: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4: CHANNEL_2_RISING: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5: CHANNEL_2_FALLING: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
Offset: 0x74, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMEN3
rw |
PWMEN2
rw |
PWMEN1
rw |
PWMEN0
rw |
Match Shadow Register
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
0x40048000: LPC5411x Standard counter/timers (CTIMER0 to 4)
17/69 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IR | ||||||||||||||||||||||||||||||||
0x4 | TCR | ||||||||||||||||||||||||||||||||
0x8 | TC | ||||||||||||||||||||||||||||||||
0xc | PR | ||||||||||||||||||||||||||||||||
0x10 | PC | ||||||||||||||||||||||||||||||||
0x14 | MCR | ||||||||||||||||||||||||||||||||
0x18 | MR[[0]] | ||||||||||||||||||||||||||||||||
0x1c | MR[[1]] | ||||||||||||||||||||||||||||||||
0x20 | MR[[2]] | ||||||||||||||||||||||||||||||||
0x24 | MR[[3]] | ||||||||||||||||||||||||||||||||
0x28 | CCR | ||||||||||||||||||||||||||||||||
0x2c | CR[[0]] | ||||||||||||||||||||||||||||||||
0x30 | CR[[1]] | ||||||||||||||||||||||||||||||||
0x34 | CR[[2]] | ||||||||||||||||||||||||||||||||
0x38 | CR[[3]] | ||||||||||||||||||||||||||||||||
0x3c | EMR | ||||||||||||||||||||||||||||||||
0x70 | CTCR | ||||||||||||||||||||||||||||||||
0x74 | PWMC | ||||||||||||||||||||||||||||||||
0x78 | MSR[[0]] | ||||||||||||||||||||||||||||||||
0x7c | MSR[[1]] | ||||||||||||||||||||||||||||||||
0x80 | MSR[[2]] | ||||||||||||||||||||||||||||||||
0x84 | MSR[[3]] |
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
Offset: 0x4, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRST
rw |
CEN
rw |
Timer Counter
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCVAL
rw |
Prescale Register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRVAL
rw |
Prescale Counter
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCVAL
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
External Match Register. The EMR controls the match function and the external match pins.
Offset: 0x3c, reset: 0, access: read-write
4/8 fields covered.
Bit 0: External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 1: External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 2: External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 3: External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Offset: 0x70, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELCC
rw |
ENCC
rw |
CINSEL
rw |
CTMODE
rw |
Bits 0-1: Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register..
Allowed values:
0: TIMER: Timer Mode. Incremented every rising APB bus clock edge.
0x1: COUNTER_RISING_EDGE: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: COUNTER_FALLING_EDGE: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: COUNTER_DUAL_EDGE: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Bits 2-3: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer..
Allowed values:
0: CHANNEL_0: Channel 0. CAPn.0 for CTIMERn
0x1: CHANNEL_1: Channel 1. CAPn.1 for CTIMERn
0x2: CHANNEL_2: Channel 2. CAPn.2 for CTIMERn
0x3: CHANNEL_3: Channel 3. CAPn.3 for CTIMERn
Bits 5-7: Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved..
Allowed values:
0: CHANNEL_0_RISING: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1: CHANNEL_0_FALLING: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2: CHANNEL_1_RISING: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3: CHANNEL_1_FALLING: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4: CHANNEL_2_RISING: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5: CHANNEL_2_FALLING: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
Offset: 0x74, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMEN3
rw |
PWMEN2
rw |
PWMEN1
rw |
PWMEN0
rw |
Match Shadow Register
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
0x40049000: LPC5411x Standard counter/timers (CTIMER0 to 4)
17/69 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IR | ||||||||||||||||||||||||||||||||
0x4 | TCR | ||||||||||||||||||||||||||||||||
0x8 | TC | ||||||||||||||||||||||||||||||||
0xc | PR | ||||||||||||||||||||||||||||||||
0x10 | PC | ||||||||||||||||||||||||||||||||
0x14 | MCR | ||||||||||||||||||||||||||||||||
0x18 | MR[[0]] | ||||||||||||||||||||||||||||||||
0x1c | MR[[1]] | ||||||||||||||||||||||||||||||||
0x20 | MR[[2]] | ||||||||||||||||||||||||||||||||
0x24 | MR[[3]] | ||||||||||||||||||||||||||||||||
0x28 | CCR | ||||||||||||||||||||||||||||||||
0x2c | CR[[0]] | ||||||||||||||||||||||||||||||||
0x30 | CR[[1]] | ||||||||||||||||||||||||||||||||
0x34 | CR[[2]] | ||||||||||||||||||||||||||||||||
0x38 | CR[[3]] | ||||||||||||||||||||||||||||||||
0x3c | EMR | ||||||||||||||||||||||||||||||||
0x70 | CTCR | ||||||||||||||||||||||||||||||||
0x74 | PWMC | ||||||||||||||||||||||||||||||||
0x78 | MSR[[0]] | ||||||||||||||||||||||||||||||||
0x7c | MSR[[1]] | ||||||||||||||||||||||||||||||||
0x80 | MSR[[2]] | ||||||||||||||||||||||||||||||||
0x84 | MSR[[3]] |
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
Offset: 0x4, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRST
rw |
CEN
rw |
Timer Counter
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCVAL
rw |
Prescale Register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRVAL
rw |
Prescale Counter
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCVAL
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCH
rw |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP
r |
External Match Register. The EMR controls the match function and the external match pins.
Offset: 0x3c, reset: 0, access: read-write
4/8 fields covered.
Bit 0: External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 1: External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 2: External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bit 3: External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH..
Bits 4-5: External Match Control 0. Determines the functionality of External Match 0..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 6-7: External Match Control 1. Determines the functionality of External Match 1..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 8-9: External Match Control 2. Determines the functionality of External Match 2..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Bits 10-11: External Match Control 3. Determines the functionality of External Match 3..
Allowed values:
0: DO_NOTHING: Do Nothing.
0x1: CLEAR: Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2: SET: Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3: TOGGLE: Toggle. Toggle the corresponding External Match bit/output.
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Offset: 0x70, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELCC
rw |
ENCC
rw |
CINSEL
rw |
CTMODE
rw |
Bits 0-1: Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register..
Allowed values:
0: TIMER: Timer Mode. Incremented every rising APB bus clock edge.
0x1: COUNTER_RISING_EDGE: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2: COUNTER_FALLING_EDGE: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3: COUNTER_DUAL_EDGE: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Bits 2-3: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer..
Allowed values:
0: CHANNEL_0: Channel 0. CAPn.0 for CTIMERn
0x1: CHANNEL_1: Channel 1. CAPn.1 for CTIMERn
0x2: CHANNEL_2: Channel 2. CAPn.2 for CTIMERn
0x3: CHANNEL_3: Channel 3. CAPn.3 for CTIMERn
Bits 5-7: Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved..
Allowed values:
0: CHANNEL_0_RISING: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1: CHANNEL_0_FALLING: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2: CHANNEL_1_RISING: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3: CHANNEL_1_FALLING: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4: CHANNEL_2_RISING: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5: CHANNEL_2_FALLING: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
Offset: 0x74, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMEN3
rw |
PWMEN2
rw |
PWMEN1
rw |
PWMEN0
rw |
Match Shadow Register
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
Match Shadow Register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SHADOWW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHADOWW
rw |
0x40082000: LPC5411x DMA controller
545/646 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | INTSTAT | ||||||||||||||||||||||||||||||||
0x8 | SRAMBASE | ||||||||||||||||||||||||||||||||
0x20 | ENABLESET0 | ||||||||||||||||||||||||||||||||
0x28 | ENABLECLR0 | ||||||||||||||||||||||||||||||||
0x30 | ACTIVE0 | ||||||||||||||||||||||||||||||||
0x38 | BUSY0 | ||||||||||||||||||||||||||||||||
0x40 | ERRINT0 | ||||||||||||||||||||||||||||||||
0x48 | INTENSET0 | ||||||||||||||||||||||||||||||||
0x50 | INTENCLR0 | ||||||||||||||||||||||||||||||||
0x58 | INTA0 | ||||||||||||||||||||||||||||||||
0x60 | INTB0 | ||||||||||||||||||||||||||||||||
0x68 | SETVALID0 | ||||||||||||||||||||||||||||||||
0x70 | SETTRIG0 | ||||||||||||||||||||||||||||||||
0x78 | ABORT0 | ||||||||||||||||||||||||||||||||
0x400 | CFG [0] | ||||||||||||||||||||||||||||||||
0x404 | CTLSTAT [0] | ||||||||||||||||||||||||||||||||
0x408 | XFERCFG [0] | ||||||||||||||||||||||||||||||||
0x410 | CFG [1] | ||||||||||||||||||||||||||||||||
0x414 | CTLSTAT [1] | ||||||||||||||||||||||||||||||||
0x418 | XFERCFG [1] | ||||||||||||||||||||||||||||||||
0x420 | CFG [2] | ||||||||||||||||||||||||||||||||
0x424 | CTLSTAT [2] | ||||||||||||||||||||||||||||||||
0x428 | XFERCFG [2] | ||||||||||||||||||||||||||||||||
0x430 | CFG [3] | ||||||||||||||||||||||||||||||||
0x434 | CTLSTAT [3] | ||||||||||||||||||||||||||||||||
0x438 | XFERCFG [3] | ||||||||||||||||||||||||||||||||
0x440 | CFG [4] | ||||||||||||||||||||||||||||||||
0x444 | CTLSTAT [4] | ||||||||||||||||||||||||||||||||
0x448 | XFERCFG [4] | ||||||||||||||||||||||||||||||||
0x450 | CFG [5] | ||||||||||||||||||||||||||||||||
0x454 | CTLSTAT [5] | ||||||||||||||||||||||||||||||||
0x458 | XFERCFG [5] | ||||||||||||||||||||||||||||||||
0x460 | CFG [6] | ||||||||||||||||||||||||||||||||
0x464 | CTLSTAT [6] | ||||||||||||||||||||||||||||||||
0x468 | XFERCFG [6] | ||||||||||||||||||||||||||||||||
0x470 | CFG [7] | ||||||||||||||||||||||||||||||||
0x474 | CTLSTAT [7] | ||||||||||||||||||||||||||||||||
0x478 | XFERCFG [7] | ||||||||||||||||||||||||||||||||
0x480 | CFG [8] | ||||||||||||||||||||||||||||||||
0x484 | CTLSTAT [8] | ||||||||||||||||||||||||||||||||
0x488 | XFERCFG [8] | ||||||||||||||||||||||||||||||||
0x490 | CFG [9] | ||||||||||||||||||||||||||||||||
0x494 | CTLSTAT [9] | ||||||||||||||||||||||||||||||||
0x498 | XFERCFG [9] | ||||||||||||||||||||||||||||||||
0x4a0 | CFG [10] | ||||||||||||||||||||||||||||||||
0x4a4 | CTLSTAT [10] | ||||||||||||||||||||||||||||||||
0x4a8 | XFERCFG [10] | ||||||||||||||||||||||||||||||||
0x4b0 | CFG [11] | ||||||||||||||||||||||||||||||||
0x4b4 | CTLSTAT [11] | ||||||||||||||||||||||||||||||||
0x4b8 | XFERCFG [11] | ||||||||||||||||||||||||||||||||
0x4c0 | CFG [12] | ||||||||||||||||||||||||||||||||
0x4c4 | CTLSTAT [12] | ||||||||||||||||||||||||||||||||
0x4c8 | XFERCFG [12] | ||||||||||||||||||||||||||||||||
0x4d0 | CFG [13] | ||||||||||||||||||||||||||||||||
0x4d4 | CTLSTAT [13] | ||||||||||||||||||||||||||||||||
0x4d8 | XFERCFG [13] | ||||||||||||||||||||||||||||||||
0x4e0 | CFG [14] | ||||||||||||||||||||||||||||||||
0x4e4 | CTLSTAT [14] | ||||||||||||||||||||||||||||||||
0x4e8 | XFERCFG [14] | ||||||||||||||||||||||||||||||||
0x4f0 | CFG [15] | ||||||||||||||||||||||||||||||||
0x4f4 | CTLSTAT [15] | ||||||||||||||||||||||||||||||||
0x4f8 | XFERCFG [15] | ||||||||||||||||||||||||||||||||
0x500 | CFG [16] | ||||||||||||||||||||||||||||||||
0x504 | CTLSTAT [16] | ||||||||||||||||||||||||||||||||
0x508 | XFERCFG [16] | ||||||||||||||||||||||||||||||||
0x510 | CFG [17] | ||||||||||||||||||||||||||||||||
0x514 | CTLSTAT [17] | ||||||||||||||||||||||||||||||||
0x518 | XFERCFG [17] | ||||||||||||||||||||||||||||||||
0x520 | CFG [18] | ||||||||||||||||||||||||||||||||
0x524 | CTLSTAT [18] | ||||||||||||||||||||||||||||||||
0x528 | XFERCFG [18] | ||||||||||||||||||||||||||||||||
0x530 | CFG [19] | ||||||||||||||||||||||||||||||||
0x534 | CTLSTAT [19] | ||||||||||||||||||||||||||||||||
0x538 | XFERCFG [19] | ||||||||||||||||||||||||||||||||
0x540 | CFG [20] | ||||||||||||||||||||||||||||||||
0x544 | CTLSTAT [20] | ||||||||||||||||||||||||||||||||
0x548 | XFERCFG [20] | ||||||||||||||||||||||||||||||||
0x550 | CFG [21] | ||||||||||||||||||||||||||||||||
0x554 | CTLSTAT [21] | ||||||||||||||||||||||||||||||||
0x558 | XFERCFG [21] | ||||||||||||||||||||||||||||||||
0x560 | CFG [22] | ||||||||||||||||||||||||||||||||
0x564 | CTLSTAT [22] | ||||||||||||||||||||||||||||||||
0x568 | XFERCFG [22] | ||||||||||||||||||||||||||||||||
0x570 | CFG [23] | ||||||||||||||||||||||||||||||||
0x574 | CTLSTAT [23] | ||||||||||||||||||||||||||||||||
0x578 | XFERCFG [23] | ||||||||||||||||||||||||||||||||
0x580 | CFG [24] | ||||||||||||||||||||||||||||||||
0x584 | CTLSTAT [24] | ||||||||||||||||||||||||||||||||
0x588 | XFERCFG [24] | ||||||||||||||||||||||||||||||||
0x590 | CFG [25] | ||||||||||||||||||||||||||||||||
0x594 | CTLSTAT [25] | ||||||||||||||||||||||||||||||||
0x598 | XFERCFG [25] | ||||||||||||||||||||||||||||||||
0x5a0 | CFG [26] | ||||||||||||||||||||||||||||||||
0x5a4 | CTLSTAT [26] | ||||||||||||||||||||||||||||||||
0x5a8 | XFERCFG [26] | ||||||||||||||||||||||||||||||||
0x5b0 | CFG [27] | ||||||||||||||||||||||||||||||||
0x5b4 | CTLSTAT [27] | ||||||||||||||||||||||||||||||||
0x5b8 | XFERCFG [27] | ||||||||||||||||||||||||||||||||
0x5c0 | CFG [28] | ||||||||||||||||||||||||||||||||
0x5c4 | CTLSTAT [28] | ||||||||||||||||||||||||||||||||
0x5c8 | XFERCFG [28] | ||||||||||||||||||||||||||||||||
0x5d0 | CFG [29] | ||||||||||||||||||||||||||||||||
0x5d4 | CTLSTAT [29] | ||||||||||||||||||||||||||||||||
0x5d8 | XFERCFG [29] |
DMA control.
Offset: 0x0, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE
rw |
Bit 0: DMA controller master enable..
Allowed values:
0: DISABLED: Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
0x1: ENABLED: Enabled. The DMA controller is enabled.
Interrupt status.
Offset: 0x4, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVEERRINT
r |
ACTIVEINT
r |
SRAM address of the channel configuration table.
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OFFSET
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET
rw |
Channel Enable read and Set for all DMA channels.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA
rw |
Channel Enable Clear for all DMA channels.
Offset: 0x28, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
w |
Channel Active status for all DMA channels.
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACT
r |
Channel Busy status for all DMA channels.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BSY
r |
Error Interrupt status for all DMA channels.
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR
rw |
Interrupt Enable read and Set for all DMA channels.
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INTEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTEN
rw |
Interrupt Enable Clear for all DMA channels.
Offset: 0x50, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
w |
Interrupt A status for all DMA channels.
Offset: 0x58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IA
rw |
Interrupt B status for all DMA channels.
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IB
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IB
rw |
Set ValidPending control bits for all DMA channels.
Offset: 0x68, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SV
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SV
w |
Set Trigger control bits for all DMA channels.
Offset: 0x70, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIG
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
w |
Channel Abort control for all DMA channels.
Offset: 0x78, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABORTCTRL
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABORTCTRL
w |
Configuration register for DMA channel .
Offset: 0x400, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x404, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x408, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x410, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x414, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x418, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x420, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x424, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x428, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x430, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x434, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x438, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x440, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x444, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x448, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x450, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x454, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x458, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x460, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x464, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x468, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x470, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x474, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x478, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x480, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x484, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x488, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x490, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x494, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x498, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4a0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4a4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4a8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4b0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4b4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4b8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4c0, reset: 0, access: read-write
7/9 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4c4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4c8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4d0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4d4, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4d8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4e0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4e4, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4e8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x4f0, reset: 0, access: read-write
7/9 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x4f4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x4f8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x500, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x504, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x508, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x510, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x514, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x518, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x520, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x524, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x528, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x530, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x534, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x538, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x540, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x544, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x548, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x550, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x554, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x558, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x560, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x564, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x568, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x570, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x574, reset: 0, access: read-only
2/2 fields covered.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x578, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x580, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x584, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x588, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x590, reset: 0, access: read-write
7/9 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x594, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x598, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x5a0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x5a4, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x5a8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x5b0, reset: 0, access: read-write
7/9 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x5b4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x5b8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x5c0, reset: 0, access: read-write
7/9 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x5c4, reset: 0, access: read-only
2/2 fields covered.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x5c8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
Configuration register for DMA channel .
Offset: 0x5d0, reset: 0, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHPRIORITY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTBURSTWRAP
rw |
SRCBURSTWRAP
rw |
BURSTPOWER
rw |
TRIGBURST
rw |
TRIGTYPE
rw |
TRIGPOL
rw |
HWTRIGEN
rw |
PERIPHREQEN
rw |
Bit 0: Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller..
Allowed values:
0: DISABLED: Disabled. Peripheral DMA requests are disabled.
0x1: ENABLED: Enabled. Peripheral DMA requests are enabled.
Bit 4: Trigger Polarity. Selects the polarity of a hardware trigger for this channel..
Allowed values:
0: ACTIVE_LOW_FALLING: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0x1: ACTIVE_HIGH_RISING: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
Bit 5: Trigger Type. Selects hardware trigger as edge triggered or level triggered..
Allowed values:
0: EDGE: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0x1: LEVEL: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
Bit 6: Trigger Burst. Selects whether hardware triggers cause a single or burst transfer..
Allowed values:
0: SINGLE: Single transfer. Hardware trigger causes a single transfer.
0x1: BURST: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
Bits 8-11: Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size..
Bit 14: Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Source burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Source burst wrapping is enabled for this DMA channel.
Bit 15: Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst..
Allowed values:
0: DISABLED: Disabled. Destination burst wrapping is not enabled for this DMA channel.
0x1: ENABLED: Enabled. Destination burst wrapping is enabled for this DMA channel.
Control and status register for DMA channel .
Offset: 0x5d4, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
r |
VALIDPENDING
r |
Bit 2: Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1..
Allowed values:
0: NOT_TRIGGERED: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0x1: TRIGGERED: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
Transfer configuration register for DMA channel .
Offset: 0x5d8, reset: 0, access: read-write
9/10 fields covered.
Bit 0: Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled..
Allowed values:
0: NOT_VALID: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0x1: VALID: Valid. The current channel descriptor is considered valid.
Bit 1: Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers..
Allowed values:
0: DISABLED: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0x1: ENABLED: Enabled. Reload the channels' control structure when the current descriptor is exhausted.
Bit 2: Software Trigger..
Allowed values:
0: NOT_SET: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0x1: SET: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
Bit 4: Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
Bit 5: Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed..
Allowed values:
0: NO_EFFECT: No effect.
0x1: SET: Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
Bits 8-9: Transfer width used for this DMA channel..
Allowed values:
0: BIT_8: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0x1: BIT_16: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x2: BIT_32: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
Bits 12-13: Determines whether the source address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2: WIDTH_X_2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
Bits 14-15: Determines whether the destination address is incremented for each DMA transfer..
Allowed values:
0: NO_INCREMENT: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1: WIDTH_X_1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2: WIDTH_X_2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3: WIDTH_X_4: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
Bits 16-25: Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed..
0x40090000: LPC5411x DMIC Subsystem (DMIC))
21/52 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | OSR [0] | ||||||||||||||||||||||||||||||||
0x4 | DIVHFCLK [0] | ||||||||||||||||||||||||||||||||
0x8 | PREAC2FSCOEF [0] | ||||||||||||||||||||||||||||||||
0xc | PREAC4FSCOEF [0] | ||||||||||||||||||||||||||||||||
0x10 | GAINSHIFT [0] | ||||||||||||||||||||||||||||||||
0x80 | FIFO_CTRL [0] | ||||||||||||||||||||||||||||||||
0x84 | FIFO_STATUS [0] | ||||||||||||||||||||||||||||||||
0x88 | FIFO_DATA [0] | ||||||||||||||||||||||||||||||||
0x8c | PHY_CTRL [0] | ||||||||||||||||||||||||||||||||
0x90 | DC_CTRL [0] | ||||||||||||||||||||||||||||||||
0x100 | OSR [1] | ||||||||||||||||||||||||||||||||
0x104 | DIVHFCLK [1] | ||||||||||||||||||||||||||||||||
0x108 | PREAC2FSCOEF [1] | ||||||||||||||||||||||||||||||||
0x10c | PREAC4FSCOEF [1] | ||||||||||||||||||||||||||||||||
0x110 | GAINSHIFT [1] | ||||||||||||||||||||||||||||||||
0x180 | FIFO_CTRL [1] | ||||||||||||||||||||||||||||||||
0x184 | FIFO_STATUS [1] | ||||||||||||||||||||||||||||||||
0x188 | FIFO_DATA [1] | ||||||||||||||||||||||||||||||||
0x18c | PHY_CTRL [1] | ||||||||||||||||||||||||||||||||
0x190 | DC_CTRL [1] | ||||||||||||||||||||||||||||||||
0xf00 | CHANEN | ||||||||||||||||||||||||||||||||
0xf0c | IOCFG | ||||||||||||||||||||||||||||||||
0xf10 | USE2FS | ||||||||||||||||||||||||||||||||
0xf80 | HWVADGAIN | ||||||||||||||||||||||||||||||||
0xf84 | HWVADHPFS | ||||||||||||||||||||||||||||||||
0xf88 | HWVADST10 | ||||||||||||||||||||||||||||||||
0xf8c | HWVADRSTT | ||||||||||||||||||||||||||||||||
0xf90 | HWVADTHGN | ||||||||||||||||||||||||||||||||
0xf94 | HWVADTHGS | ||||||||||||||||||||||||||||||||
0xf98 | HWVADLOWZ | ||||||||||||||||||||||||||||||||
0xffc | ID |
Oversample Rate register 0
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSR
rw |
DMIC Clock Register 0
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDMDIV
rw |
Pre-Emphasis Filter Coefficient for 2 FS register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP
rw |
Pre-Emphasis Filter Coefficient for 4 FS register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP
rw |
Decimator Gain Shift register
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN
rw |
FIFO Control register 0
Offset: 0x80, reset: 0, access: read-write
4/5 fields covered.
Bit 0: FIFO enable..
Allowed values:
0: DISABLED: FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1: ENABLED: FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
Bits 16-20: FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full)..
FIFO Status register 0
Offset: 0x84, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNDERRUN
rw |
OVERRUN
rw |
INT
rw |
FIFO Data Register 0
Offset: 0x88, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
PDM Source Configuration register 0
Offset: 0x8c, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_HALF
rw |
PHY_FALL
rw |
DC Control register 0
Offset: 0x90, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SATURATEAT16BIT
rw |
DCGAIN
rw |
DCPOLE
rw |
Oversample Rate register 0
Offset: 0x100, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSR
rw |
DMIC Clock Register 0
Offset: 0x104, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDMDIV
rw |
Pre-Emphasis Filter Coefficient for 2 FS register
Offset: 0x108, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP
rw |
Pre-Emphasis Filter Coefficient for 4 FS register
Offset: 0x10c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP
rw |
Decimator Gain Shift register
Offset: 0x110, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN
rw |
FIFO Control register 0
Offset: 0x180, reset: 0, access: read-write
4/5 fields covered.
Bit 0: FIFO enable..
Allowed values:
0: DISABLED: FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1: ENABLED: FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
Bits 16-20: FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full)..
FIFO Status register 0
Offset: 0x184, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNDERRUN
rw |
OVERRUN
rw |
INT
rw |
FIFO Data Register 0
Offset: 0x188, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
PDM Source Configuration register 0
Offset: 0x18c, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_HALF
rw |
PHY_FALL
rw |
DC Control register 0
Offset: 0x190, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SATURATEAT16BIT
rw |
DCGAIN
rw |
DCPOLE
rw |
Channel Enable register
Offset: 0xf00, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_CH1
rw |
EN_CH0
rw |
I/O Configuration register
Offset: 0xf0c, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STEREO_DATA0
rw |
CLK_BYPASS1
rw |
CLK_BYPASS0
rw |
Use 2FS register
Offset: 0xf10, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USE2FS
rw |
HWVAD input gain register
Offset: 0xf80, reset: 0x5, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INPUTGAIN
rw |
HWVAD filter control register
Offset: 0xf84, reset: 0x1, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HPFS
rw |
HWVAD control register
Offset: 0xf88, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ST10
rw |
HWVAD filter reset register
Offset: 0xf8c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSTT
rw |
HWVAD noise estimator gain register
Offset: 0xf90, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THGN
rw |
HWVAD signal estimator gain register
Offset: 0xf94, reset: 0x4, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THGS
rw |
HWVAD noise envelope estimator register
Offset: 0xf98, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOWZ
r |
Module Identification register
Offset: 0xffc, reset: 0x2, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
0x40014000: LPC5460x EEPROM controller
2/16 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CMD | ||||||||||||||||||||||||||||||||
0x8 | RWSTATE | ||||||||||||||||||||||||||||||||
0xc | AUTOPROG | ||||||||||||||||||||||||||||||||
0x10 | WSTATE | ||||||||||||||||||||||||||||||||
0x14 | CLKDIV | ||||||||||||||||||||||||||||||||
0x18 | PWRDWN | ||||||||||||||||||||||||||||||||
0xfd8 | INTENCLR | ||||||||||||||||||||||||||||||||
0xfdc | INTENSET | ||||||||||||||||||||||||||||||||
0xfe0 | INTSTAT | ||||||||||||||||||||||||||||||||
0xfe4 | INTEN | ||||||||||||||||||||||||||||||||
0xfe8 | INTSTATCLR | ||||||||||||||||||||||||||||||||
0xfec | INTSTATSET |
EEPROM command register
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMD
rw |
EEPROM read wait state register
Offset: 0x8, reset: 0xE07, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RPHASE1
rw |
RPHASE2
rw |
EEPROM auto programming register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOPROG
rw |
EEPROM wait state register
Offset: 0x10, reset: 0x40802, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCK_PARWEP
rw |
PHASE1
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE2
rw |
PHASE3
rw |
EEPROM clock divider register
Offset: 0x14, reset: 0x63, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKDIV
rw |
EEPROM power-down register
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWRDWN
rw |
EEPROM interrupt enable clear
Offset: 0xfd8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROG_CLR_EN
w |
EEPROM interrupt enable set
Offset: 0xfdc, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROG_SET_EN
w |
EEPROM interrupt status
Offset: 0xfe0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
END_OF_PROG
r |
EEPROM interrupt enable
Offset: 0xfe4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EE_PROG_DONE
r |
EEPROM interrupt status clear
Offset: 0xfe8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROG_CLR_ST
w |
EEPROM interrupt status set
Offset: 0xfec, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROG_SET_ST
w |
0x40081000: LPC5460x External Memory Controller (EMC)
3/107 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CONTROL | ||||||||||||||||||||||||||||||||
0x4 | STATUS | ||||||||||||||||||||||||||||||||
0x8 | CONFIG | ||||||||||||||||||||||||||||||||
0x20 | DYNAMICCONTROL | ||||||||||||||||||||||||||||||||
0x24 | DYNAMICREFRESH | ||||||||||||||||||||||||||||||||
0x28 | DYNAMICREADCONFIG | ||||||||||||||||||||||||||||||||
0x30 | DYNAMICRP | ||||||||||||||||||||||||||||||||
0x34 | DYNAMICRAS | ||||||||||||||||||||||||||||||||
0x38 | DYNAMICSREX | ||||||||||||||||||||||||||||||||
0x3c | DYNAMICAPR | ||||||||||||||||||||||||||||||||
0x40 | DYNAMICDAL | ||||||||||||||||||||||||||||||||
0x44 | DYNAMICWR | ||||||||||||||||||||||||||||||||
0x48 | DYNAMICRC | ||||||||||||||||||||||||||||||||
0x4c | DYNAMICRFC | ||||||||||||||||||||||||||||||||
0x50 | DYNAMICXSR | ||||||||||||||||||||||||||||||||
0x54 | DYNAMICRRD | ||||||||||||||||||||||||||||||||
0x58 | DYNAMICMRD | ||||||||||||||||||||||||||||||||
0x80 | STATICEXTENDEDWAIT | ||||||||||||||||||||||||||||||||
0x100 | DYNAMICCONFIG [0] | ||||||||||||||||||||||||||||||||
0x104 | DYNAMICRASCAS [0] | ||||||||||||||||||||||||||||||||
0x120 | DYNAMICCONFIG [1] | ||||||||||||||||||||||||||||||||
0x124 | DYNAMICRASCAS [1] | ||||||||||||||||||||||||||||||||
0x140 | DYNAMICCONFIG [2] | ||||||||||||||||||||||||||||||||
0x144 | DYNAMICRASCAS [2] | ||||||||||||||||||||||||||||||||
0x160 | DYNAMICCONFIG [3] | ||||||||||||||||||||||||||||||||
0x164 | DYNAMICRASCAS [3] | ||||||||||||||||||||||||||||||||
0x200 | STATICCONFIG [0] | ||||||||||||||||||||||||||||||||
0x204 | STATICWAITWEN [0] | ||||||||||||||||||||||||||||||||
0x208 | STATICWAITOEN [0] | ||||||||||||||||||||||||||||||||
0x20c | STATICWAITRD [0] | ||||||||||||||||||||||||||||||||
0x210 | STATICWAITPAGE [0] | ||||||||||||||||||||||||||||||||
0x214 | STATICWAITWR [0] | ||||||||||||||||||||||||||||||||
0x218 | STATICWAITTURN [0] | ||||||||||||||||||||||||||||||||
0x220 | STATICCONFIG [1] | ||||||||||||||||||||||||||||||||
0x224 | STATICWAITWEN [1] | ||||||||||||||||||||||||||||||||
0x228 | STATICWAITOEN [1] | ||||||||||||||||||||||||||||||||
0x22c | STATICWAITRD [1] | ||||||||||||||||||||||||||||||||
0x230 | STATICWAITPAGE [1] | ||||||||||||||||||||||||||||||||
0x234 | STATICWAITWR [1] | ||||||||||||||||||||||||||||||||
0x238 | STATICWAITTURN [1] | ||||||||||||||||||||||||||||||||
0x240 | STATICCONFIG [2] | ||||||||||||||||||||||||||||||||
0x244 | STATICWAITWEN [2] | ||||||||||||||||||||||||||||||||
0x248 | STATICWAITOEN [2] | ||||||||||||||||||||||||||||||||
0x24c | STATICWAITRD [2] | ||||||||||||||||||||||||||||||||
0x250 | STATICWAITPAGE [2] | ||||||||||||||||||||||||||||||||
0x254 | STATICWAITWR [2] | ||||||||||||||||||||||||||||||||
0x258 | STATICWAITTURN [2] | ||||||||||||||||||||||||||||||||
0x260 | STATICCONFIG [3] | ||||||||||||||||||||||||||||||||
0x264 | STATICWAITWEN [3] | ||||||||||||||||||||||||||||||||
0x268 | STATICWAITOEN [3] | ||||||||||||||||||||||||||||||||
0x26c | STATICWAITRD [3] | ||||||||||||||||||||||||||||||||
0x270 | STATICWAITPAGE [3] | ||||||||||||||||||||||||||||||||
0x274 | STATICWAITWR [3] | ||||||||||||||||||||||||||||||||
0x278 | STATICWAITTURN [3] |
Controls operation of the memory controller
Offset: 0x0, reset: 0x3, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L
rw |
M
rw |
E
rw |
Provides EMC status information
Offset: 0x4, reset: 0x5, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SA
r |
S
r |
B
r |
Configures operation of the memory controller
Offset: 0x8, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKR
rw |
EM
rw |
Configures dynamic memory refresh
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REFRESH
rw |
Configures dynamic memory read strategy
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD
rw |
Precharge command period
Offset: 0x30, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRP
rw |
Active to precharge command period
Offset: 0x34, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRAS
rw |
Self-refresh exit time
Offset: 0x38, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSREX
rw |
Last-data-out to active command time
Offset: 0x3c, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAPR
rw |
Data-in to active command time
Offset: 0x40, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDAL
rw |
Write recovery time
Offset: 0x44, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TWR
rw |
Selects the active to active command period
Offset: 0x48, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRC
rw |
Selects the auto-refresh period
Offset: 0x4c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRFC
rw |
Time for exit self-refresh to active command
Offset: 0x50, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXSR
rw |
Latency for active bank A to active bank B
Offset: 0x54, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRRD
rw |
Time for load mode register to active command
Offset: 0x58, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMRD
rw |
Time for long static memory read and write transfers
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTENDEDWAIT
rw |
RAS and CAS latencies for EMC_DYCSx
Offset: 0x104, reset: 0x303, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAS
rw |
RAS
rw |
RAS and CAS latencies for EMC_DYCSx
Offset: 0x124, reset: 0x303, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAS
rw |
RAS
rw |
RAS and CAS latencies for EMC_DYCSx
Offset: 0x144, reset: 0x303, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAS
rw |
RAS
rw |
RAS and CAS latencies for EMC_DYCSx
Offset: 0x164, reset: 0x303, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAS
rw |
RAS
rw |
Delay from EMC_CSx to write enable
Offset: 0x204, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWEN
rw |
Delay from EMC_CSx or address change, whichever is later, to output enable
Offset: 0x208, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITOEN
rw |
Delay from EMC_CSx to a read access
Offset: 0x20c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITRD
rw |
Delay for asynchronous page mode sequential accesses for EMC_CSx
Offset: 0x210, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITPAGE
rw |
Delay from EMC_CSx to a write access
Offset: 0x214, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWR
rw |
Number of bus turnaround cycles EMC_CSx
Offset: 0x218, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITTURN
rw |
Delay from EMC_CSx to write enable
Offset: 0x224, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWEN
rw |
Delay from EMC_CSx or address change, whichever is later, to output enable
Offset: 0x228, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITOEN
rw |
Delay from EMC_CSx to a read access
Offset: 0x22c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITRD
rw |
Delay for asynchronous page mode sequential accesses for EMC_CSx
Offset: 0x230, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITPAGE
rw |
Delay from EMC_CSx to a write access
Offset: 0x234, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWR
rw |
Number of bus turnaround cycles EMC_CSx
Offset: 0x238, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITTURN
rw |
Delay from EMC_CSx to write enable
Offset: 0x244, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWEN
rw |
Delay from EMC_CSx or address change, whichever is later, to output enable
Offset: 0x248, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITOEN
rw |
Delay from EMC_CSx to a read access
Offset: 0x24c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITRD
rw |
Delay for asynchronous page mode sequential accesses for EMC_CSx
Offset: 0x250, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITPAGE
rw |
Delay from EMC_CSx to a write access
Offset: 0x254, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWR
rw |
Number of bus turnaround cycles EMC_CSx
Offset: 0x258, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITTURN
rw |
Delay from EMC_CSx to write enable
Offset: 0x264, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWEN
rw |
Delay from EMC_CSx or address change, whichever is later, to output enable
Offset: 0x268, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITOEN
rw |
Delay from EMC_CSx to a read access
Offset: 0x26c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITRD
rw |
Delay for asynchronous page mode sequential accesses for EMC_CSx
Offset: 0x270, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITPAGE
rw |
Delay from EMC_CSx to a write access
Offset: 0x274, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITWR
rw |
Number of bus turnaround cycles EMC_CSx
Offset: 0x278, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITTURN
rw |
0x40092000: LPC5460x Ethernet controller
117/415 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MAC_CONFIG | ||||||||||||||||||||||||||||||||
0x4 | MAC_EXT_CONFIG | ||||||||||||||||||||||||||||||||
0x8 | MAC_FRAME_FILTER | ||||||||||||||||||||||||||||||||
0xc | MAC_WD_TIMEROUT | ||||||||||||||||||||||||||||||||
0x50 | MAC_VLAN_TAG | ||||||||||||||||||||||||||||||||
0x70 | MAC_TX_FLOW_CTRL_Q[[0]] | ||||||||||||||||||||||||||||||||
0x74 | MAC_TX_FLOW_CTRL_Q[[1]] | ||||||||||||||||||||||||||||||||
0x90 | MAC_RX_FLOW_CTRL | ||||||||||||||||||||||||||||||||
0x98 | MAC_TXQ_PRIO_MAP | ||||||||||||||||||||||||||||||||
0xa0 | MAC_RXQ_CTRL0 | ||||||||||||||||||||||||||||||||
0xa4 | MAC_RXQ_CTRL1 | ||||||||||||||||||||||||||||||||
0xa8 | MAC_RXQ_CTRL2 | ||||||||||||||||||||||||||||||||
0xb0 | MAC_INTR_STAT | ||||||||||||||||||||||||||||||||
0xb4 | MAC_INTR_EN | ||||||||||||||||||||||||||||||||
0xb8 | MAC_RXTX_STAT | ||||||||||||||||||||||||||||||||
0xc0 | MAC_PMT_CRTL_STAT | ||||||||||||||||||||||||||||||||
0xc4 | MAC_RWAKE_FRFLT | ||||||||||||||||||||||||||||||||
0xd0 | MAC_LPI_CTRL_STAT | ||||||||||||||||||||||||||||||||
0xd4 | MAC_LPI_TIMER_CTRL | ||||||||||||||||||||||||||||||||
0xd8 | MAC_LPI_ENTR_TIMR | ||||||||||||||||||||||||||||||||
0xdc | MAC_1US_TIC_COUNTR | ||||||||||||||||||||||||||||||||
0x110 | MAC_VERSION | ||||||||||||||||||||||||||||||||
0x114 | MAC_DBG | ||||||||||||||||||||||||||||||||
0x11c | MAC_HW_FEAT0 | ||||||||||||||||||||||||||||||||
0x120 | MAC_HW_FEAT1 | ||||||||||||||||||||||||||||||||
0x124 | MAC_HW_FEAT2 | ||||||||||||||||||||||||||||||||
0x200 | MAC_MDIO_ADDR | ||||||||||||||||||||||||||||||||
0x204 | MAC_MDIO_DATA | ||||||||||||||||||||||||||||||||
0x300 | MAC_ADDR_HIGH | ||||||||||||||||||||||||||||||||
0x304 | MAC_ADDR_LOW | ||||||||||||||||||||||||||||||||
0xb00 | MAC_TIMESTAMP_CTRL | ||||||||||||||||||||||||||||||||
0xb04 | MAC_SUB_SCND_INCR | ||||||||||||||||||||||||||||||||
0xb08 | MAC_SYS_TIME_SCND | ||||||||||||||||||||||||||||||||
0xb0c | MAC_SYS_TIME_NSCND | ||||||||||||||||||||||||||||||||
0xb10 | MAC_SYS_TIME_SCND_UPD | ||||||||||||||||||||||||||||||||
0xb14 | MAC_SYS_TIME_NSCND_UPD | ||||||||||||||||||||||||||||||||
0xb18 | MAC_SYS_TIMESTMP_ADDEND | ||||||||||||||||||||||||||||||||
0xb1c | MAC_SYS_TIME_HWORD_SCND | ||||||||||||||||||||||||||||||||
0xb20 | MAC_SYS_TIMESTMP_STAT | ||||||||||||||||||||||||||||||||
0xb30 | MAC_Tx_TIMESTAMP_STATUS_NANOSECONDS | ||||||||||||||||||||||||||||||||
0xb34 | MAC_Tx_TIMESTAMP_STATUS_SECONDS | ||||||||||||||||||||||||||||||||
0xb58 | MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND | ||||||||||||||||||||||||||||||||
0xb5c | MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND | ||||||||||||||||||||||||||||||||
0xc00 | MTL_OP_MODE | ||||||||||||||||||||||||||||||||
0xc20 | MTL_INTR_STAT | ||||||||||||||||||||||||||||||||
0xc30 | MTL_RXQ_DMA_MAP | ||||||||||||||||||||||||||||||||
0xd00 | MTL_TXQx_OP_MODE [0] | ||||||||||||||||||||||||||||||||
0xd04 | MTL_TXQx_UNDRFLW [0] | ||||||||||||||||||||||||||||||||
0xd08 | MTL_TXQx_DBG [0] | ||||||||||||||||||||||||||||||||
0xd10 | MTL_TXQx_ETS_CTRL [0] | ||||||||||||||||||||||||||||||||
0xd14 | MTL_TXQx_ETS_STAT [0] | ||||||||||||||||||||||||||||||||
0xd18 | MTL_TXQx_QNTM_WGHT [0] | ||||||||||||||||||||||||||||||||
0xd1c | MTL_TXQx_SNDSLP_CRDT [0] | ||||||||||||||||||||||||||||||||
0xd20 | MTL_TXQx_HI_CRDT [0] | ||||||||||||||||||||||||||||||||
0xd24 | MTL_TXQx_LO_CRDT [0] | ||||||||||||||||||||||||||||||||
0xd2c | MTL_TXQx_INTCTRL_STAT [0] | ||||||||||||||||||||||||||||||||
0xd30 | MTL_RXQx_OP_MODE [0] | ||||||||||||||||||||||||||||||||
0xd34 | MTL_RXQx_MISSPKT_OVRFLW_CNT [0] | ||||||||||||||||||||||||||||||||
0xd38 | MTL_RXQx_DBG [0] | ||||||||||||||||||||||||||||||||
0xd3c | MTL_RXQx_CTRL [0] | ||||||||||||||||||||||||||||||||
0xd40 | MTL_TXQx_OP_MODE [1] | ||||||||||||||||||||||||||||||||
0xd44 | MTL_TXQx_UNDRFLW [1] | ||||||||||||||||||||||||||||||||
0xd48 | MTL_TXQx_DBG [1] | ||||||||||||||||||||||||||||||||
0xd50 | MTL_TXQx_ETS_CTRL [1] | ||||||||||||||||||||||||||||||||
0xd54 | MTL_TXQx_ETS_STAT [1] | ||||||||||||||||||||||||||||||||
0xd58 | MTL_TXQx_QNTM_WGHT [1] | ||||||||||||||||||||||||||||||||
0xd5c | MTL_TXQx_SNDSLP_CRDT [1] | ||||||||||||||||||||||||||||||||
0xd60 | MTL_TXQx_HI_CRDT [1] | ||||||||||||||||||||||||||||||||
0xd64 | MTL_TXQx_LO_CRDT [1] | ||||||||||||||||||||||||||||||||
0xd6c | MTL_TXQx_INTCTRL_STAT [1] | ||||||||||||||||||||||||||||||||
0xd70 | MTL_RXQx_OP_MODE [1] | ||||||||||||||||||||||||||||||||
0xd74 | MTL_RXQx_MISSPKT_OVRFLW_CNT [1] | ||||||||||||||||||||||||||||||||
0xd78 | MTL_RXQx_DBG [1] | ||||||||||||||||||||||||||||||||
0xd7c | MTL_RXQx_CTRL [1] | ||||||||||||||||||||||||||||||||
0x1000 | DMA_MODE | ||||||||||||||||||||||||||||||||
0x1004 | DMA_SYSBUS_MODE | ||||||||||||||||||||||||||||||||
0x1008 | DMA_INTR_STAT | ||||||||||||||||||||||||||||||||
0x100c | DMA_DBG_STAT | ||||||||||||||||||||||||||||||||
0x1100 | DMA_CHx_CTRL [0] | ||||||||||||||||||||||||||||||||
0x1104 | DMA_CHx_TX_CTRL [0] | ||||||||||||||||||||||||||||||||
0x1108 | DMA_CHx_RX_CTRL [0] | ||||||||||||||||||||||||||||||||
0x1114 | DMA_CHx_TXDESC_LIST_ADDR [0] | ||||||||||||||||||||||||||||||||
0x111c | DMA_CHx_RXDESC_LIST_ADDR [0] | ||||||||||||||||||||||||||||||||
0x1120 | DMA_CHx_TXDESC_TAIL_PTR [0] | ||||||||||||||||||||||||||||||||
0x1128 | DMA_CHx_RXDESC_TAIL_PTR [0] | ||||||||||||||||||||||||||||||||
0x112c | DMA_CHx_TXDESC_RING_LENGTH [0] | ||||||||||||||||||||||||||||||||
0x1130 | DMA_CHx_RXDESC_RING_LENGTH [0] | ||||||||||||||||||||||||||||||||
0x1134 | DMA_CHx_INT_EN [0] | ||||||||||||||||||||||||||||||||
0x1138 | DMA_CHx_RX_INT_WDTIMER [0] | ||||||||||||||||||||||||||||||||
0x113c | DMA_CHx_SLOT_FUNC_CTRL_STAT [0] | ||||||||||||||||||||||||||||||||
0x1144 | DMA_CHx_CUR_HST_TXDESC [0] | ||||||||||||||||||||||||||||||||
0x114c | DMA_CHx_CUR_HST_RXDESC [0] | ||||||||||||||||||||||||||||||||
0x1154 | DMA_CHx_CUR_HST_TXBUF [0] | ||||||||||||||||||||||||||||||||
0x115c | DMA_CHx_CUR_HST_RXBUF [0] | ||||||||||||||||||||||||||||||||
0x1160 | DMA_CHx_STAT [0] | ||||||||||||||||||||||||||||||||
0x1180 | DMA_CHx_CTRL [1] | ||||||||||||||||||||||||||||||||
0x1184 | DMA_CHx_TX_CTRL [1] | ||||||||||||||||||||||||||||||||
0x1188 | DMA_CHx_RX_CTRL [1] | ||||||||||||||||||||||||||||||||
0x1194 | DMA_CHx_TXDESC_LIST_ADDR [1] | ||||||||||||||||||||||||||||||||
0x119c | DMA_CHx_RXDESC_LIST_ADDR [1] | ||||||||||||||||||||||||||||||||
0x11a0 | DMA_CHx_TXDESC_TAIL_PTR [1] | ||||||||||||||||||||||||||||||||
0x11a8 | DMA_CHx_RXDESC_TAIL_PTR [1] | ||||||||||||||||||||||||||||||||
0x11ac | DMA_CHx_TXDESC_RING_LENGTH [1] | ||||||||||||||||||||||||||||||||
0x11b0 | DMA_CHx_RXDESC_RING_LENGTH [1] | ||||||||||||||||||||||||||||||||
0x11b4 | DMA_CHx_INT_EN [1] | ||||||||||||||||||||||||||||||||
0x11b8 | DMA_CHx_RX_INT_WDTIMER [1] | ||||||||||||||||||||||||||||||||
0x11bc | DMA_CHx_SLOT_FUNC_CTRL_STAT [1] | ||||||||||||||||||||||||||||||||
0x11c4 | DMA_CHx_CUR_HST_TXDESC [1] | ||||||||||||||||||||||||||||||||
0x11cc | DMA_CHx_CUR_HST_RXDESC [1] | ||||||||||||||||||||||||||||||||
0x11d4 | DMA_CHx_CUR_HST_TXBUF [1] | ||||||||||||||||||||||||||||||||
0x11dc | DMA_CHx_CUR_HST_RXBUF [1] | ||||||||||||||||||||||||||||||||
0x11e0 | DMA_CHx_STAT [1] |
no description available
Offset: 0x4, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USP
rw |
SPEN
rw |
DCRCC
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPSL
rw |
MAC watchdog Timeout register
Offset: 0xc, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWE
rw |
WTO
rw |
Receive flow control register
Offset: 0x90, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UP
rw |
RFE
rw |
no description available
Offset: 0x98, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTQ1
rw |
PSTQ0
rw |
Receive Queue Control 0 register 0x0000
Offset: 0xa0, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXQ1EN
rw |
RXQ0EN
rw |
Receive Queue Control 0 register 0x0000
Offset: 0xa8, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSRQ3
rw |
PSRQ2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSRQ1
rw |
PSRQ0
rw |
Receive Transmit Status register
Offset: 0xb8, reset: 0, access: read-only
7/7 fields covered.
Bit 3: Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when Jumbo packet is enabled)..
no description available
Offset: 0xc0, reset: 0, access: read-write
5/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RWKFILTRST
rw |
RWKPTR
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RWKPFE
rw |
GLBLUCAST
rw |
RWKPRCVD
r |
MGKPRCVD
r |
RWKPKTEN
r |
MGKPKTEN
r |
PWRDWN
r |
Remote wake-up frame filter
Offset: 0xc4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR
rw |
LPI Timers Control register
Offset: 0xd4, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LST
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TWT
rw |
LPI entry Timer register
Offset: 0xd8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPIET
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPIET
rw |
no description available
Offset: 0xdc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIC_1US_CNTR
rw |
MAC version register
Offset: 0x110, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USERVER
rw |
SNPVER
rw |
MAC debug register
Offset: 0x114, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TFCSTS
r |
TPESTS
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFCFCSTS
r |
REPESTS
r |
MAC hardware feature register 0x0201
Offset: 0x120, reset: 0, access: read-only
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
L3_L4_FILTER
r |
HASHTBLSZ
r |
LPMODEEN
r |
AVSEL
r |
DBGMEMA
r |
TSOEN
r |
SPEN
r |
DCBEN
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR64
r |
ADVTHWORD
r |
PTOEN
r |
OSTEN
r |
TXFIFOSIZE
r |
RXFIFOSIZE
r |
MAC hardware feature register 0x0201
Offset: 0x124, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AUXSNAPNUM
r |
PPSOUTNUM
r |
TXCHCNT
r |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXCHCNT
r |
TXQCNT
r |
RXQCNT
r |
MDIO Data register
Offset: 0x204, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MD
rw |
MAC address0 high register
Offset: 0x300, reset: 0x8000FFFF, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AE
r |
DCS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A47_32
rw |
MAC address0 low register
Offset: 0x304, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
A31_0
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A31_0
rw |
Time stamp control register
Offset: 0xb00, reset: 0x2000, access: read-write
0/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AV8021ASMEN
rw |
TXTTSSTSM
rw |
TSENMACADDR
rw |
SNAPTYPSEL
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSMSTRENA
rw |
TSEVTENA
rw |
TSIPV4ENA
rw |
TSIPV6ENA
rw |
TSIPENA
rw |
TSVER2ENA
rw |
TSCTRLSSR
rw |
TSENALL
rw |
TADDREG
rw |
TSTRIG
rw |
TSUPDT
rw |
TSINIT
rw |
TSCFUPDT
rw |
TSENA
rw |
Sub-second increment register
Offset: 0xb04, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SSINC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System time seconds register
Offset: 0xb08, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSS
r |
System time nanoseconds register
Offset: 0xb0c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSSS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSSS
r |
no description available
Offset: 0xb10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSS
rw |
no description available
Offset: 0xb14, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDSUB
rw |
TSSS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSSS
rw |
Time stamp addend register
Offset: 0xb18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSAR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSAR
rw |
no description available
Offset: 0xb1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSHWR
rw |
Time stamp status register
Offset: 0xb20, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSSOVF
r |
Tx timestamp status nanoseconds
Offset: 0xb30, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXTSSTSMIS
r |
TXTSSTSLO
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXTSSTSLO
r |
Tx timestamp status seconds
Offset: 0xb34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXTSSTSHI
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXTSSTSHI
r |
Timestamp ingress correction
Offset: 0xb58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSIC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSIC
rw |
Timestamp egress correction
Offset: 0xb5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSEC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEC
rw |
MTL Interrupt Status register
Offset: 0xc20, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Q1IS
r |
Q0IS
r |
MTL Receive Queue and DMA Channel Mapping register
Offset: 0xc30, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Q1DDMACH
rw |
Q1MDMACH
rw |
Q0DDMACH
rw |
Q0MDMACH
rw |
Bit 4: Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address..
Bit 12: Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address..
MTL TxQx Underflow register
Offset: 0xd04, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UFCNTOVF
r |
UFFRMCNT
r |
MTL TxQx Debug register
Offset: 0xd08, reset: 0, access: read-only
7/7 fields covered.
Bit 0: Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802..
Bits 1-2: MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the Packet Abort request from the MAC..
MTL TxQx ETS control register, only TxQ1 support
Offset: 0xd10, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLC
r |
CC
rw |
AVALG
rw |
MTL TxQx ETS Status register
Offset: 0xd14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABS
rw |
no description available
Offset: 0xd18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ISCQW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISCQW
rw |
MTL TxQx SendSlopCredit register, only TxQ1 support
Offset: 0xd1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SSC
rw |
MTL TxQx hiCredit register, only TxQ1 support
Offset: 0xd20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HC
rw |
MTL TxQx loCredit register, only TxQ1 support
Offset: 0xd24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LC
rw |
MTL RxQx Operation Mode register
Offset: 0xd30, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RQS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_TCP_EF
rw |
RSF
rw |
FEP
rw |
FUP
rw |
RTC
rw |
MTL RxQx Missed Packet Overflow Counter register
Offset: 0xd34, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVFCNTOVF
r |
OVFPKTCNT
rw |
MTL RxQx Debug register
Offset: 0xd38, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRXQ
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXQSTS
r |
RRCSTS
r |
RWCSTS
rw |
MTL RxQx Control register
Offset: 0xd3c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXQ_FRM_ARBIT
rw |
RXQ_WEGT
rw |
MTL TxQx Underflow register
Offset: 0xd44, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UFCNTOVF
r |
UFFRMCNT
r |
MTL TxQx Debug register
Offset: 0xd48, reset: 0, access: read-only
7/7 fields covered.
Bit 0: Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802..
Bits 1-2: MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the Packet Abort request from the MAC..
MTL TxQx ETS control register, only TxQ1 support
Offset: 0xd50, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLC
r |
CC
rw |
AVALG
rw |
MTL TxQx ETS Status register
Offset: 0xd54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABS
rw |
no description available
Offset: 0xd58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ISCQW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISCQW
rw |
MTL TxQx SendSlopCredit register, only TxQ1 support
Offset: 0xd5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SSC
rw |
MTL TxQx hiCredit register, only TxQ1 support
Offset: 0xd60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HC
rw |
MTL TxQx loCredit register, only TxQ1 support
Offset: 0xd64, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LC
rw |
MTL RxQx Operation Mode register
Offset: 0xd70, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RQS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_TCP_EF
rw |
RSF
rw |
FEP
rw |
FUP
rw |
RTC
rw |
MTL RxQx Missed Packet Overflow Counter register
Offset: 0xd74, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVFCNTOVF
r |
OVFPKTCNT
rw |
MTL RxQx Debug register
Offset: 0xd78, reset: 0, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRXQ
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXQSTS
r |
RRCSTS
r |
RWCSTS
rw |
MTL RxQx Control register
Offset: 0xd7c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXQ_FRM_ARBIT
rw |
RXQ_WEGT
rw |
DMA System Bus mode
Offset: 0x1004, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RB
rw |
MB
rw |
AAL
rw |
FB
rw |
DMA Interrupt status
Offset: 0x1008, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MACIS
r |
MTLIS
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DC1IS
rw |
DC0IS
rw |
DMA Debug Status
Offset: 0x100c, reset: 0, access: read-write
4/5 fields covered.
Bits 8-11: DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer ) 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet data from the Rx buffer to the system memory) This field does not generate an interrupt..
Bits 12-15: DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer) 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field does not generate an interrupt..
DMA Channelx Control
Offset: 0x1100, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DSL
rw |
PBLx8
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA Channelx Transmit Control
Offset: 0x1104, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TxPBL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSF
rw |
TCW
rw |
ST
rw |
DMA Channelx Receive Control
Offset: 0x1108, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RPF
rw |
RxPBL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBSZ
rw |
SR
rw |
no description available
Offset: 0x1114, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STL
rw |
no description available
Offset: 0x111c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SRL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRL
rw |
no description available
Offset: 0x1120, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDTP
rw |
no description available
Offset: 0x1128, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDTP
rw |
no description available
Offset: 0x112c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDRL
rw |
Channelx Rx descriptor Ring Length
Offset: 0x1130, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDRL
rw |
Receive Interrupt Watchdog Timer
Offset: 0x1138, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RIWT
rw |
Slot Function Control and Status
Offset: 0x113c, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSN
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASC
rw |
ESC
rw |
Bit 1: Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or, ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set..
Channelx Current Host Transmit descriptor
Offset: 0x1144, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HTD
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HTD
r |
no description available
Offset: 0x114c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HRD
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HRD
r |
no description available
Offset: 0x1154, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HTB
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HTB
r |
Channelx Current Application Receive Buffer Address
Offset: 0x115c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HRB
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HRB
r |
Channelx DMA status register
Offset: 0x1160, reset: 0, access: read-write
0/13 fields covered.
Bit 14: Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit..
Bit 15: Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal Interrupt Summary bit..
DMA Channelx Control
Offset: 0x1180, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DSL
rw |
PBLx8
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA Channelx Transmit Control
Offset: 0x1184, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TxPBL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSF
rw |
TCW
rw |
ST
rw |
DMA Channelx Receive Control
Offset: 0x1188, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RPF
rw |
RxPBL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBSZ
rw |
SR
rw |
no description available
Offset: 0x1194, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STL
rw |
no description available
Offset: 0x119c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SRL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRL
rw |
no description available
Offset: 0x11a0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDTP
rw |
no description available
Offset: 0x11a8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDTP
rw |
no description available
Offset: 0x11ac, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDRL
rw |
Channelx Rx descriptor Ring Length
Offset: 0x11b0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDRL
rw |
Receive Interrupt Watchdog Timer
Offset: 0x11b8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RIWT
rw |
Slot Function Control and Status
Offset: 0x11bc, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSN
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASC
rw |
ESC
rw |
Bit 1: Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or, ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set..
Channelx Current Host Transmit descriptor
Offset: 0x11c4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HTD
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HTD
r |
no description available
Offset: 0x11cc, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HRD
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HRD
r |
no description available
Offset: 0x11d4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HTB
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HTB
r |
Channelx Current Application Receive Buffer Address
Offset: 0x11dc, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HRB
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HRB
r |
Channelx DMA status register
Offset: 0x11e0, reset: 0, access: read-write
0/13 fields covered.
Bit 14: Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit..
Bit 15: Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal Interrupt Summary bit..
0xe0041000: Embedded Trace Macrocell Registers
72/102 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | CCR | ||||||||||||||||||||||||||||||||
0x8 | TRIGGER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | SCR | ||||||||||||||||||||||||||||||||
0x20 | EEVR | ||||||||||||||||||||||||||||||||
0x24 | TECR1 | ||||||||||||||||||||||||||||||||
0x28 | FFLR | ||||||||||||||||||||||||||||||||
0x140 | CNTRLDVR1 | ||||||||||||||||||||||||||||||||
0x1e0 | SYNCFR | ||||||||||||||||||||||||||||||||
0x1e4 | IDR | ||||||||||||||||||||||||||||||||
0x1e8 | CCER | ||||||||||||||||||||||||||||||||
0x1f0 | TESSEICR | ||||||||||||||||||||||||||||||||
0x1f8 | TSEVR | ||||||||||||||||||||||||||||||||
0x200 | TRACEIDR | ||||||||||||||||||||||||||||||||
0x208 | IDR2 | ||||||||||||||||||||||||||||||||
0x314 | PDSR | ||||||||||||||||||||||||||||||||
0xee0 | _ITMISCIN | ||||||||||||||||||||||||||||||||
0xee8 | _ITTRIGOUT | ||||||||||||||||||||||||||||||||
0xef0 | _ITATBCTR2 | ||||||||||||||||||||||||||||||||
0xef8 | _ITATBCTR0 | ||||||||||||||||||||||||||||||||
0xf00 | ITCTRL | ||||||||||||||||||||||||||||||||
0xfa0 | CLAIMSET | ||||||||||||||||||||||||||||||||
0xfa4 | CLAIMCLR | ||||||||||||||||||||||||||||||||
0xfb0 | LAR | ||||||||||||||||||||||||||||||||
0xfb4 | LSR | ||||||||||||||||||||||||||||||||
0xfb8 | AUTHSTATUS | ||||||||||||||||||||||||||||||||
0xfcc | DEVTYPE | ||||||||||||||||||||||||||||||||
0xfd0 | PIDR4 | ||||||||||||||||||||||||||||||||
0xfd4 | PIDR5 | ||||||||||||||||||||||||||||||||
0xfd8 | PIDR6 | ||||||||||||||||||||||||||||||||
0xfdc | PIDR7 | ||||||||||||||||||||||||||||||||
0xfe0 | PIDR0 | ||||||||||||||||||||||||||||||||
0xfe4 | PIDR1 | ||||||||||||||||||||||||||||||||
0xfe8 | PIDR2 | ||||||||||||||||||||||||||||||||
0xfec | PIDR3 | ||||||||||||||||||||||||||||||||
0xff0 | CIDR0 | ||||||||||||||||||||||||||||||||
0xff4 | CIDR1 | ||||||||||||||||||||||||||||||||
0xff8 | CIDR2 | ||||||||||||||||||||||||||||||||
0xffc | CIDR3 |
Main Control Register
Offset: 0x0, reset: 0x411, access: read-write
1/11 fields covered.
Bit 7: Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace resumes without corruption once the FIFO has drained, if overflow does occur. An ETM reset sets this bit to 0..
Bit 8: Branch output. When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed. When this bit is set to 1, more trace data is generated, and this may affect the performance of the trace system. Information about the execution of a branch is traced regardless of the state of this bit. An ETM reset sets this bit to 0..
Bit 11: ETM port selection. This bit can be used to control other trace components in an implementation. This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM. An ETM reset sets this bit to 0..
Allowed values:
0: ETMPS_0: ETMEN is LOW.
0x1: ETMPS_1: ETMEN is HIGH.
Trigger Event Register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TriggerEvent
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TriggerEvent
rw |
ETM Status Register
Offset: 0x10, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Trigger
rw |
Status
rw |
Progbit
r |
UOF
r |
Bit 0: Untraced overflow flag. If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either: - trace is restarted - the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1. Note: Setting or clearing the ETM programming bit does not cause this bit to be cleared to 0..
System Configuration Register
Offset: 0x14, reset: 0x20D09, access: read-only
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NoFetchComparisons
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N
r |
PortModeSupported
r |
PortSizeSupported
r |
MaximumPortSize3
r |
FIFOFULLsupported
r |
MaximumPortSize
r |
Trace Enable Event Register
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TraceEnableEvent
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TraceEnableEvent
rw |
Trace Enable Control 1 Register
Offset: 0x24, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TraceControlEnable
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit 25: Trace start/stop enable. The trace start/stop resource, resource 0x5F, is unaffected by the value of this bit..
Allowed values:
0: TraceControlEnable_0: Tracing is unaffected by the trace start/stop logic.
0x1: TraceControlEnable_1: Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic.
FIFOFULL Level Register
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOFullLevel
rw |
Free-running counter reload value
Offset: 0x140, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IntitialCount
rw |
Synchronization Frequency Register
Offset: 0x1e0, reset: 0x400, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SyncFrequency
r |
ID Register
Offset: 0x1e4, reset: 0x4114F250, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ImplementorCode
r |
BranchPacketEncoding
r |
SecurityExtensionSupport
r |
ThumbInstructionTracing
r |
LoadPCfirst
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProcessorFamily
r |
MajorETMarchitectureVersion
r |
MinorETMarchitectureVersion
r |
ImplementationRevision
r |
Bit 18: 32-bit Thumb instruction tracing. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction..
Allowed values:
0: ThumbInstructionTracing_0: A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions.
0x1: ThumbInstructionTracing_1: A 32-bit Thimb instruction is traced as a single instruction.
Bit 19: Security Extensions support. The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times..
Allowed values:
0: SecurityExtensionSupport_0: The ETM behaves as if the processor is in Secure state at all times.
0x1: SecurityExtensionSupport_1: The ARM architecture Security Extensions are implemented by the processor.
Bit 20: Branch packet encoding. The value of this bit is 1, indicating that alternative branch packet encoding is implemented..
Allowed values:
0: BranchPacketEncoding_0: The ETM implements the original branch packet encoding.
0x1: BranchPacketEncoding_1: The ETM implements the alternative branch packet encoding.
Configuration Code Extension Register
Offset: 0x1e8, reset: 0x18541800, access: read-only
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TimestampSize
r |
TimestampEncoding
r |
ReducedFunctionCounter
r |
TimestampingImplemented
r |
EmbeddedICEbehaviorControlImplemented
r |
TraceStartStopBlockUsesEmbeddedICEwatchpointInputs
r |
EmbeddedICEwatchpointInputs
r |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
InstrumentationResources
r |
DataAddressComparisons
r |
ReadableRegisters
r |
ExtendedExternalInputBus
r |
ExtendedExternalInputSelectors
r |
TraceEnable Start/Stop EmbeddedICE Control Register
Offset: 0x1f0, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
StopResourceSelection
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
StartResourceSelection
rw |
Bits 0-3: Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4..
Bits 16-19: Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4..
Timestamp Event Register
Offset: 0x1f8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TimestampEvent
rw |
CoreSight Trace ID Register
Offset: 0x200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TraceID
rw |
ETM ID Register 2
Offset: 0x208, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Device Power-Down Status Register
Offset: 0x314, reset: 0x1, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETMpoweredup
r |
Integration Test Miscelaneous Inputs Register
Offset: 0xee0, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COREHALT
r |
EXTIN
r |
Integration Test Trigger Out Register
Offset: 0xee8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGGER
w |
ETM Integration Test ATB Control 2 Register
Offset: 0xef0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATREADY
r |
ETM Integration Test ATB Control 0 Register
Offset: 0xef8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATVALID
w |
Integration Mode Control Register
Offset: 0xf00, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Mode
rw |
Claim Tag Set Register
Offset: 0xfa0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAIMSET
rw |
Claim Tag Clear Register
Offset: 0xfa4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAIMCLR
rw |
Lock Access Register
Offset: 0xfb0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WriteAccessCode
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WriteAccessCode
rw |
Lock Status Register
Offset: 0xfb4, reset: 0x1, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
s8BIT
r |
STATUS
r |
IMP
r |
Authentication Status Register
Offset: 0xfb8, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SNID
r |
SID
r |
NSNID
r |
NSID
r |
CoreSight Device Type Register
Offset: 0xfcc, reset: 0x13, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SubType
r |
MajorType
r |
Peripheral Identification Register 4
Offset: 0xfd0, reset: 0x4, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
c4KB
r |
JEP106
r |
Peripheral Identification Register 5
Offset: 0xfd4, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 6
Offset: 0xfd8, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 7
Offset: 0xfdc, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 0
Offset: 0xfe0, reset: 0x25, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PartNumber
r |
Peripheral Identification Register 1
Offset: 0xfe4, reset: 0xB9, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEP106_identity_code
r |
PartNumber
r |
Peripheral Identification Register 2
Offset: 0xfe8, reset: 0xB, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Revision
r |
JEP106_identity_code
r |
Peripheral Identification Register 3
Offset: 0xfec, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RevAnd
r |
CustomerModified
r |
Component Identification Register 0
Offset: 0xff0, reset: 0xD, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
Component Identification Register 1
Offset: 0xff4, reset: 0x90, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ComponentClass
r |
Preamble
r |
Component Identification Register 2
Offset: 0xff8, reset: 0x5, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
Component Identification Register 3
Offset: 0xffc, reset: 0xB1, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
0x40086000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40087000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40088000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40089000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x4008a000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40096000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40097000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40098000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40099000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x4009a000: LPC5411x Flexcomm serial communication
9/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xff8 | PSELID | ||||||||||||||||||||||||||||||||
0xffc | PID |
Peripheral Select and Flexcomm ID register.
Offset: 0xff8, reset: 0x101000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID
r |
I2SPRESENT
r |
I2CPRESENT
r |
SPIPRESENT
r |
USARTPRESENT
r |
LOCK
rw |
PERSEL
rw |
Bits 0-2: Peripheral Select. This field is writable by software..
Allowed values:
0: NO_PERIPH_SELECTED: No peripheral selected.
0x1: USART: USART function selected.
0x2: SPI: SPI function selected.
0x3: I2C: I2C function selected.
0x4: I2S_TRANSMIT: I2S transmit function selected.
0x5: I2S_RECEIVE: I2S receive function selected.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
0x40034000: LPC5460x Flash signature generator
5/12 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | FCTR | ||||||||||||||||||||||||||||||||
0x10 | FBWST | ||||||||||||||||||||||||||||||||
0x20 | FMSSTART | ||||||||||||||||||||||||||||||||
0x24 | FMSSTOP | ||||||||||||||||||||||||||||||||
0x2c | FMSW[[0]] | ||||||||||||||||||||||||||||||||
0x30 | FMSW[[1]] | ||||||||||||||||||||||||||||||||
0x34 | FMSW[[2]] | ||||||||||||||||||||||||||||||||
0x38 | FMSW[[3]] | ||||||||||||||||||||||||||||||||
0xfe0 | FMSTAT | ||||||||||||||||||||||||||||||||
0xfe8 | FMSTATCLR |
Control register
Offset: 0x0, reset: 0x200005, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS_RD1
rw |
FS_RD0
rw |
Wait state register
Offset: 0x10, reset: 0xC005, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITSTATES
rw |
Signature start address register
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START
rw |
Signature stop-address register
Offset: 0x24, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIG_START
rw |
STOP
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STOP
rw |
Words of 128-bit signature word
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SW
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SW
r |
Words of 128-bit signature word
Offset: 0x30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SW
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SW
r |
Words of 128-bit signature word
Offset: 0x34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SW
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SW
r |
Words of 128-bit signature word
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SW
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SW
r |
Signature generation status register
Offset: 0xfe0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIG_DONE
r |
Signature generation status clear register
Offset: 0xfe8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIG_DONE_CLR
w |
0x40002000: LPC5411x Group GPIO input interrupt (GINT0/1)
3/7 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x20 | PORT_POL[[0]] | ||||||||||||||||||||||||||||||||
0x24 | PORT_POL[[1]] | ||||||||||||||||||||||||||||||||
0x40 | PORT_ENA[[0]] | ||||||||||||||||||||||||||||||||
0x44 | PORT_ENA[[1]] |
GPIO grouped interrupt control register
Offset: 0x0, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
rw |
COMB
rw |
INT
rw |
Bit 1: Combine enabled inputs for group interrupt.
Allowed values:
0: OR: Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
0x1: AND: And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
GPIO grouped interrupt port 0 polarity register
Offset: 0x20, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL
rw |
Bits 0-31: Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt..
GPIO grouped interrupt port 0 polarity register
Offset: 0x24, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL
rw |
Bits 0-31: Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt..
GPIO grouped interrupt port 0 enable register
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA
rw |
GPIO grouped interrupt port 0 enable register
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA
rw |
0x40003000: LPC5411x Group GPIO input interrupt (GINT0/1)
3/7 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x20 | PORT_POL[[0]] | ||||||||||||||||||||||||||||||||
0x24 | PORT_POL[[1]] | ||||||||||||||||||||||||||||||||
0x40 | PORT_ENA[[0]] | ||||||||||||||||||||||||||||||||
0x44 | PORT_ENA[[1]] |
GPIO grouped interrupt control register
Offset: 0x0, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIG
rw |
COMB
rw |
INT
rw |
Bit 1: Combine enabled inputs for group interrupt.
Allowed values:
0: OR: Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
0x1: AND: And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
GPIO grouped interrupt port 0 polarity register
Offset: 0x20, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL
rw |
Bits 0-31: Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt..
GPIO grouped interrupt port 0 polarity register
Offset: 0x24, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL
rw |
Bits 0-31: Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt..
GPIO grouped interrupt port 0 enable register
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA
rw |
GPIO grouped interrupt port 0 enable register
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA
rw |
0x4008c000: LPC5411x General Purpose I/O (GPIO)
0/72 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | B_[%s] [0] | ||||||||||||||||||||||||||||||||
0x20 | B_[%s] [1] | ||||||||||||||||||||||||||||||||
0x40 | B_[%s] [2] | ||||||||||||||||||||||||||||||||
0x60 | B_[%s] [3] | ||||||||||||||||||||||||||||||||
0x80 | B_[%s] [4] | ||||||||||||||||||||||||||||||||
0xa0 | B_[%s] [5] | ||||||||||||||||||||||||||||||||
0x1000 | W_[%s] [0] | ||||||||||||||||||||||||||||||||
0x1080 | W_[%s] [1] | ||||||||||||||||||||||||||||||||
0x1100 | W_[%s] [2] | ||||||||||||||||||||||||||||||||
0x1180 | W_[%s] [3] | ||||||||||||||||||||||||||||||||
0x1200 | W_[%s] [4] | ||||||||||||||||||||||||||||||||
0x1280 | W_[%s] [5] | ||||||||||||||||||||||||||||||||
0x2000 | DIR[[0]] | ||||||||||||||||||||||||||||||||
0x2004 | DIR[[1]] | ||||||||||||||||||||||||||||||||
0x2008 | DIR[[2]] | ||||||||||||||||||||||||||||||||
0x200c | DIR[[3]] | ||||||||||||||||||||||||||||||||
0x2010 | DIR[[4]] | ||||||||||||||||||||||||||||||||
0x2014 | DIR[[5]] | ||||||||||||||||||||||||||||||||
0x2080 | MASK[[0]] | ||||||||||||||||||||||||||||||||
0x2084 | MASK[[1]] | ||||||||||||||||||||||||||||||||
0x2088 | MASK[[2]] | ||||||||||||||||||||||||||||||||
0x208c | MASK[[3]] | ||||||||||||||||||||||||||||||||
0x2090 | MASK[[4]] | ||||||||||||||||||||||||||||||||
0x2094 | MASK[[5]] | ||||||||||||||||||||||||||||||||
0x2100 | PIN[[0]] | ||||||||||||||||||||||||||||||||
0x2104 | PIN[[1]] | ||||||||||||||||||||||||||||||||
0x2108 | PIN[[2]] | ||||||||||||||||||||||||||||||||
0x210c | PIN[[3]] | ||||||||||||||||||||||||||||||||
0x2110 | PIN[[4]] | ||||||||||||||||||||||||||||||||
0x2114 | PIN[[5]] | ||||||||||||||||||||||||||||||||
0x2180 | MPIN[[0]] | ||||||||||||||||||||||||||||||||
0x2184 | MPIN[[1]] | ||||||||||||||||||||||||||||||||
0x2188 | MPIN[[2]] | ||||||||||||||||||||||||||||||||
0x218c | MPIN[[3]] | ||||||||||||||||||||||||||||||||
0x2190 | MPIN[[4]] | ||||||||||||||||||||||||||||||||
0x2194 | MPIN[[5]] | ||||||||||||||||||||||||||||||||
0x2200 | SET[[0]] | ||||||||||||||||||||||||||||||||
0x2204 | SET[[1]] | ||||||||||||||||||||||||||||||||
0x2208 | SET[[2]] | ||||||||||||||||||||||||||||||||
0x220c | SET[[3]] | ||||||||||||||||||||||||||||||||
0x2210 | SET[[4]] | ||||||||||||||||||||||||||||||||
0x2214 | SET[[5]] | ||||||||||||||||||||||||||||||||
0x2280 | CLR[[0]] | ||||||||||||||||||||||||||||||||
0x2284 | CLR[[1]] | ||||||||||||||||||||||||||||||||
0x2288 | CLR[[2]] | ||||||||||||||||||||||||||||||||
0x228c | CLR[[3]] | ||||||||||||||||||||||||||||||||
0x2290 | CLR[[4]] | ||||||||||||||||||||||||||||||||
0x2294 | CLR[[5]] | ||||||||||||||||||||||||||||||||
0x2300 | NOT[[0]] | ||||||||||||||||||||||||||||||||
0x2304 | NOT[[1]] | ||||||||||||||||||||||||||||||||
0x2308 | NOT[[2]] | ||||||||||||||||||||||||||||||||
0x230c | NOT[[3]] | ||||||||||||||||||||||||||||||||
0x2310 | NOT[[4]] | ||||||||||||||||||||||||||||||||
0x2314 | NOT[[5]] | ||||||||||||||||||||||||||||||||
0x2380 | DIRSET[[0]] | ||||||||||||||||||||||||||||||||
0x2384 | DIRSET[[1]] | ||||||||||||||||||||||||||||||||
0x2388 | DIRSET[[2]] | ||||||||||||||||||||||||||||||||
0x238c | DIRSET[[3]] | ||||||||||||||||||||||||||||||||
0x2390 | DIRSET[[4]] | ||||||||||||||||||||||||||||||||
0x2394 | DIRSET[[5]] | ||||||||||||||||||||||||||||||||
0x2400 | DIRCLR[[0]] | ||||||||||||||||||||||||||||||||
0x2404 | DIRCLR[[1]] | ||||||||||||||||||||||||||||||||
0x2408 | DIRCLR[[2]] | ||||||||||||||||||||||||||||||||
0x240c | DIRCLR[[3]] | ||||||||||||||||||||||||||||||||
0x2410 | DIRCLR[[4]] | ||||||||||||||||||||||||||||||||
0x2414 | DIRCLR[[5]] | ||||||||||||||||||||||||||||||||
0x2480 | DIRNOT[[0]] | ||||||||||||||||||||||||||||||||
0x2484 | DIRNOT[[1]] | ||||||||||||||||||||||||||||||||
0x2488 | DIRNOT[[2]] | ||||||||||||||||||||||||||||||||
0x248c | DIRNOT[[3]] | ||||||||||||||||||||||||||||||||
0x2490 | DIRNOT[[4]] | ||||||||||||||||||||||||||||||||
0x2494 | DIRNOT[[5]] |
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Byte pin registers for all port 0 and 1 GPIO pins
Offset: 0xa0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBYTE
rw |
Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1000, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1080, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1100, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1180, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Word pin registers for all port 0 and 1 GPIO pins
Offset: 0x1280, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWORD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWORD
rw |
Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..
Direction registers
Offset: 0x2000, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Direction registers
Offset: 0x2004, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Direction registers
Offset: 0x2008, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Direction registers
Offset: 0x200c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Direction registers
Offset: 0x2010, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Direction registers
Offset: 0x2014, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRP
rw |
Mask register
Offset: 0x2080, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Mask register
Offset: 0x2084, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Mask register
Offset: 0x2088, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Mask register
Offset: 0x208c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Mask register
Offset: 0x2090, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Mask register
Offset: 0x2094, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MASKP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKP
rw |
Bits 0-31: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..
Port pin register
Offset: 0x2100, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Port pin register
Offset: 0x2104, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Port pin register
Offset: 0x2108, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Port pin register
Offset: 0x210c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Port pin register
Offset: 0x2110, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Port pin register
Offset: 0x2114, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PORT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT
rw |
Masked port register
Offset: 0x2180, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Masked port register
Offset: 0x2184, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Masked port register
Offset: 0x2188, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Masked port register
Offset: 0x218c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Masked port register
Offset: 0x2190, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Masked port register
Offset: 0x2194, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MPORTP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPORTP
rw |
Bits 0-31: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..
Write: Set register for port Read: output bits for port
Offset: 0x2200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Write: Set register for port Read: output bits for port
Offset: 0x2204, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Write: Set register for port Read: output bits for port
Offset: 0x2208, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Write: Set register for port Read: output bits for port
Offset: 0x220c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Write: Set register for port Read: output bits for port
Offset: 0x2210, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Write: Set register for port Read: output bits for port
Offset: 0x2214, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETP
rw |
Clear port
Offset: 0x2280, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Clear port
Offset: 0x2284, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Clear port
Offset: 0x2288, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Clear port
Offset: 0x228c, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Clear port
Offset: 0x2290, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Clear port
Offset: 0x2294, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRP
w |
Toggle port
Offset: 0x2300, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Toggle port
Offset: 0x2304, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Toggle port
Offset: 0x2308, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Toggle port
Offset: 0x230c, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Toggle port
Offset: 0x2310, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Toggle port
Offset: 0x2314, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTP
w |
Set pin direction bits for port
Offset: 0x2380, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Set pin direction bits for port
Offset: 0x2384, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Set pin direction bits for port
Offset: 0x2388, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Set pin direction bits for port
Offset: 0x238c, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Set pin direction bits for port
Offset: 0x2390, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Set pin direction bits for port
Offset: 0x2394, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRSETP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRSETP
w |
Clear pin direction bits for port
Offset: 0x2400, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Clear pin direction bits for port
Offset: 0x2404, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Clear pin direction bits for port
Offset: 0x2408, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Clear pin direction bits for port
Offset: 0x240c, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Clear pin direction bits for port
Offset: 0x2410, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Clear pin direction bits for port
Offset: 0x2414, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRCLRP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRCLRP
w |
Toggle pin direction bits for port
Offset: 0x2480, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
Toggle pin direction bits for port
Offset: 0x2484, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
Toggle pin direction bits for port
Offset: 0x2488, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
Toggle pin direction bits for port
Offset: 0x248c, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
Toggle pin direction bits for port
Offset: 0x2490, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
Toggle pin direction bits for port
Offset: 0x2494, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIRNOTP
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIRNOTP
w |
0x40086000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40087000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40088000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40089000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4008a000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40096000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40097000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40098000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40099000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4009a000: LPC5411x I2C-bus interfaces
72/93 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x800 | CFG | ||||||||||||||||||||||||||||||||
0x804 | STAT | ||||||||||||||||||||||||||||||||
0x808 | INTENSET | ||||||||||||||||||||||||||||||||
0x80c | INTENCLR | ||||||||||||||||||||||||||||||||
0x810 | TIMEOUT | ||||||||||||||||||||||||||||||||
0x814 | CLKDIV | ||||||||||||||||||||||||||||||||
0x818 | INTSTAT | ||||||||||||||||||||||||||||||||
0x820 | MSTCTL | ||||||||||||||||||||||||||||||||
0x824 | MSTTIME | ||||||||||||||||||||||||||||||||
0x828 | MSTDAT | ||||||||||||||||||||||||||||||||
0x840 | SLVCTL | ||||||||||||||||||||||||||||||||
0x844 | SLVDAT | ||||||||||||||||||||||||||||||||
0x848 | SLVADR[[0]] | ||||||||||||||||||||||||||||||||
0x84c | SLVADR[[1]] | ||||||||||||||||||||||||||||||||
0x850 | SLVADR[[2]] | ||||||||||||||||||||||||||||||||
0x854 | SLVADR[[3]] | ||||||||||||||||||||||||||||||||
0x858 | SLVQUAL0 | ||||||||||||||||||||||||||||||||
0x880 | MONRXDAT | ||||||||||||||||||||||||||||||||
0xffc | ID |
Configuration for shared functions.
Offset: 0x800, reset: 0, access: read-write
6/6 fields covered.
Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..
Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
Bit 4: Monitor function Clock Stretching..
Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
Bit 5: High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor..
Allowed values:
0: FAST_MODE_PLUS: Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0x1: HIGH_SPEED: High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.
Status register for Master, Slave, and Monitor functions.
Offset: 0x804, reset: 0x801, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
rw |
EVENTTIMEOUT
rw |
MONIDLE
rw |
MONACTIVE
r |
MONOV
rw |
MONRDY
r |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
rw |
SLVSEL
r |
SLVIDX
r |
SLVNOTSTR
r |
SLVSTATE
r |
SLVPENDING
r |
MSTSTSTPERR
rw |
MSTARBLOSS
rw |
MSTSTATE
r |
MSTPENDING
r |
Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..
Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..
Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.
Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..
Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..
Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..
Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).
Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..
Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..
Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.
Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..
Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.
Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
Bit 17: Monitor Overflow flag..
Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..
Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.
Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..
Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..
Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..
Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.
Interrupt Enable Set and read register.
Offset: 0x808, reset: 0, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTEN
rw |
EVENTTIMEOUTEN
rw |
MONIDLEEN
rw |
MONOVEN
rw |
MONRDYEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELEN
rw |
SLVNOTSTREN
rw |
SLVPENDINGEN
rw |
MSTSTSTPERREN
rw |
MSTARBLOSSEN
rw |
MSTPENDINGEN
rw |
Interrupt Enable Clear register.
Offset: 0x80c, reset: 0, access: write-only
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUTCLR
w |
EVENTTIMEOUTCLR
w |
MONIDLECLR
w |
MONOVCLR
w |
MONRDYCLR
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESELCLR
w |
SLVNOTSTRCLR
w |
SLVPENDINGCLR
w |
MSTSTSTPERRCLR
w |
MSTARBLOSSCLR
w |
MSTPENDINGCLR
w |
Time-out value register.
Offset: 0x810, reset: 0xFFFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO
rw |
TOMIN
rw |
Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
Offset: 0x814, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..
Interrupt Status register for Master, Slave, and Monitor functions.
Offset: 0x818, reset: 0x801, access: read-only
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCLTIMEOUT
r |
EVENTTIMEOUT
r |
MONIDLE
r |
MONOV
r |
MONRDY
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVDESEL
r |
SLVNOTSTR
r |
SLVPENDING
r |
MSTSTSTPERR
r |
MSTARBLOSS
r |
MSTPENDING
r |
Master control register.
Offset: 0x820, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTDMA
rw |
MSTSTOP
rw |
MSTSTART
rw |
MSTCONTINUE
w |
Bit 0: Master Continue. This bit is write-only..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
Bit 3: Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write..
Allowed values:
0: DISABLED: Disable. No DMA requests are generated for master operation.
0x1: ENABLED: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
Master timing configuration.
Offset: 0x824, reset: 0x77, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTSCLHIGH
rw |
MSTSCLLOW
rw |
Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..
Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Combined Master receiver and transmitter data register.
Offset: 0x828, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave control register.
Offset: 0x840, reset: 0, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOMATCHREAD
rw |
AUTOACK
rw |
SLVDMA
rw |
SLVNACK
rw |
SLVCONTINUE
rw |
Bit 0: Slave Continue..
Allowed values:
0: NO_EFFECT: No effect.
0x1: CONTINUE: Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.
Bit 8: Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt..
Allowed values:
0: NORMAL: Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
0x1: AUTOMATIC_ACK: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
Bit 9: When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation..
Allowed values:
0: I2C_WRITE: The expected next operation in Automatic Mode is an I2C write.
0x1: I2C_READ: The expected next operation in Automatic Mode is an I2C read.
Combined Slave receiver and transmitter data register.
Offset: 0x844, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Slave address register.
Offset: 0x848, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x84c, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x850, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave address register.
Offset: 0x854, reset: 0x1, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTONACK
rw |
SLVADR
rw |
SADISABLE
rw |
Bit 15: Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations..
Allowed values:
0: NORMAL: Normal operation, matching I2C addresses are not ignored.
0x1: AUTOMATIC: Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.
Slave Qualification for address 0.
Offset: 0x858, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLVQUAL0
rw |
QUALMODE0
rw |
Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..
Monitor receiver data register.
Offset: 0x880, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MONNACK
r |
MONRESTART
r |
MONSTART
r |
MONRXDAT
r |
Bit 9: Monitor Received Repeated Start..
Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
Bit 10: Monitor Received NACK..
Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40097000: LPC5411x I2S interface
54/88 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xc00 | CFG1 | ||||||||||||||||||||||||||||||||
0xc04 | CFG2 | ||||||||||||||||||||||||||||||||
0xc08 | STAT | ||||||||||||||||||||||||||||||||
0xc1c | DIV | ||||||||||||||||||||||||||||||||
0xc20 | PCFG1 [0] | ||||||||||||||||||||||||||||||||
0xc24 | PCFG2 [0] | ||||||||||||||||||||||||||||||||
0xc28 | PSTAT [0] | ||||||||||||||||||||||||||||||||
0xc40 | PCFG1 [1] | ||||||||||||||||||||||||||||||||
0xc44 | PCFG2 [1] | ||||||||||||||||||||||||||||||||
0xc48 | PSTAT [1] | ||||||||||||||||||||||||||||||||
0xc60 | PCFG1 [2] | ||||||||||||||||||||||||||||||||
0xc64 | PCFG2 [2] | ||||||||||||||||||||||||||||||||
0xc68 | PSTAT [2] | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe24 | FIFOWR48H | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe34 | FIFORD48H | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xe44 | FIFORD48HNOPOP | ||||||||||||||||||||||||||||||||
0x1dfc | ID |
Configuration register 1 for the primary channel pair.
Offset: 0xc00, reset: 0, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATALEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WS_POL
rw |
SCK_POL
rw |
PDMDATA
rw |
ONECHANNEL
rw |
LEFTJUST
rw |
RIGHTLOW
rw |
MODE
rw |
MSTSLVCFG
rw |
PAIRCOUNT
rw |
DATAPAUSE
rw |
MAINENABLE
rw |
Bit 0: Main enable for I 2S function in this Flexcomm.
Allowed values:
0: DISABLED: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled.
0x1: ENABLED: This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
Bit 1: Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame..
Allowed values:
0: NORMAL: Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
0x1: PAUSE: A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
Bits 2-3: Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm..
Allowed values:
0: PAIRS_1: 1 I2S channel pairs in this flexcomm
0x1: PAIRS_2: 2 I2S channel pairs in this flexcomm
0x2: PAIRS_3: 3 I2S channel pairs in this flexcomm
0x3: PAIRS_4: 4 I2S channel pairs in this flexcomm
Bits 4-5: Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm..
Allowed values:
0: NORMAL_SLAVE_MODE: Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
0x1: WS_SYNC_MASTER: WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock.
0x2: MASTER_USING_SCK: Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
0x3: NORMAL_MASTER: Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
Bits 6-7: Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples..
Allowed values:
0: CLASSIC_MODE: I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
0x1: DSP_MODE_WS_50_DUTYCYCLE: DSP mode where WS has a 50% duty cycle. See remark for mode 0.
0x2: DSP_MODE_WS_1_CLOCK: DSP mode where WS has a one clock long pulse at the beginning of each data frame.
0x3: DSP_MODE_WS_1_DATA: DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
Bit 8: Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed..
Allowed values:
0: RIGHT_HIGH: The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel.
0x1: RIGHT_LOW: The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel.
Bit 9: Left Justify data..
Allowed values:
0: RIGHT_JUSTIFIED: Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus.
0x1: LEFT_JUSTIFIED: Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus.
Bit 10: Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers..
Allowed values:
0: DUAL_CHANNEL: I2S data for this channel pair is treated as left and right channels.
0x1: SINGLE_CHANNEL: I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION.
Bit 11: PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7..
Allowed values:
0: NORMAL: Normal operation, data is transferred to or from the Flexcomm FIFO.
0x1: DMIC_SUBSYSTEM: The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.
Bits 16-20: Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length.
Configuration register 2 for the primary channel pair.
Offset: 0xc04, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAMELEN
rw |
Bits 0-8: Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly..
Bits 16-24: Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase..
Status register for the primary channel pair.
Offset: 0xc08, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
r |
SLVFRMERR
w |
BUSY
r |
Bit 1: Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream..
Allowed values:
0: NO_ERROR: No error has been recorded.
0x1: ERROR: An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
Bit 2: Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair..
Allowed values:
0: LEFT_CHANNEL: Left channel.
0x1: RIGHT_CHANNEL: Right channel.
Bit 3: Data Paused status flag. Applies to all I2S channels.
Allowed values:
0: NOT_PAUSED: Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
0x1: PAUSED: A data pause has been requested and is now in force.
Clock divider, used by all channel pairs.
Offset: 0xc1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Bits 0-11: This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096..
Configuration register 1 for channel pair
Offset: 0xc20, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc28, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
Configuration register 1 for channel pair
Offset: 0xc40, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc48, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
Configuration register 1 for channel pair
Offset: 0xc60, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc64, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc68, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
10/12 fields covered.
Bit 2: Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused..
Allowed values:
0: LAST_VALUE: If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair.
0x1: ZERO: If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
Bit 3: Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA..
Allowed values:
0: BIT_24: 48-bit I2S FIFO entries are handled as all 24-bit values.
0x1: BIT_32_16: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
w |
FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe24, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
w |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe44, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
I2S Module identification
Offset: 0x1dfc, reset: 0xE0900000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
Aperture
r |
0x40098000: LPC5411x I2S interface
54/88 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0xc00 | CFG1 | ||||||||||||||||||||||||||||||||
0xc04 | CFG2 | ||||||||||||||||||||||||||||||||
0xc08 | STAT | ||||||||||||||||||||||||||||||||
0xc1c | DIV | ||||||||||||||||||||||||||||||||
0xc20 | PCFG1 [0] | ||||||||||||||||||||||||||||||||
0xc24 | PCFG2 [0] | ||||||||||||||||||||||||||||||||
0xc28 | PSTAT [0] | ||||||||||||||||||||||||||||||||
0xc40 | PCFG1 [1] | ||||||||||||||||||||||||||||||||
0xc44 | PCFG2 [1] | ||||||||||||||||||||||||||||||||
0xc48 | PSTAT [1] | ||||||||||||||||||||||||||||||||
0xc60 | PCFG1 [2] | ||||||||||||||||||||||||||||||||
0xc64 | PCFG2 [2] | ||||||||||||||||||||||||||||||||
0xc68 | PSTAT [2] | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe24 | FIFOWR48H | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe34 | FIFORD48H | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xe44 | FIFORD48HNOPOP | ||||||||||||||||||||||||||||||||
0x1dfc | ID |
Configuration register 1 for the primary channel pair.
Offset: 0xc00, reset: 0, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATALEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WS_POL
rw |
SCK_POL
rw |
PDMDATA
rw |
ONECHANNEL
rw |
LEFTJUST
rw |
RIGHTLOW
rw |
MODE
rw |
MSTSLVCFG
rw |
PAIRCOUNT
rw |
DATAPAUSE
rw |
MAINENABLE
rw |
Bit 0: Main enable for I 2S function in this Flexcomm.
Allowed values:
0: DISABLED: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled.
0x1: ENABLED: This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
Bit 1: Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame..
Allowed values:
0: NORMAL: Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
0x1: PAUSE: A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
Bits 2-3: Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm..
Allowed values:
0: PAIRS_1: 1 I2S channel pairs in this flexcomm
0x1: PAIRS_2: 2 I2S channel pairs in this flexcomm
0x2: PAIRS_3: 3 I2S channel pairs in this flexcomm
0x3: PAIRS_4: 4 I2S channel pairs in this flexcomm
Bits 4-5: Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm..
Allowed values:
0: NORMAL_SLAVE_MODE: Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
0x1: WS_SYNC_MASTER: WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock.
0x2: MASTER_USING_SCK: Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
0x3: NORMAL_MASTER: Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
Bits 6-7: Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples..
Allowed values:
0: CLASSIC_MODE: I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
0x1: DSP_MODE_WS_50_DUTYCYCLE: DSP mode where WS has a 50% duty cycle. See remark for mode 0.
0x2: DSP_MODE_WS_1_CLOCK: DSP mode where WS has a one clock long pulse at the beginning of each data frame.
0x3: DSP_MODE_WS_1_DATA: DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
Bit 8: Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed..
Allowed values:
0: RIGHT_HIGH: The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel.
0x1: RIGHT_LOW: The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel.
Bit 9: Left Justify data..
Allowed values:
0: RIGHT_JUSTIFIED: Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus.
0x1: LEFT_JUSTIFIED: Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus.
Bit 10: Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers..
Allowed values:
0: DUAL_CHANNEL: I2S data for this channel pair is treated as left and right channels.
0x1: SINGLE_CHANNEL: I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION.
Bit 11: PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7..
Allowed values:
0: NORMAL: Normal operation, data is transferred to or from the Flexcomm FIFO.
0x1: DMIC_SUBSYSTEM: The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.
Bits 16-20: Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length.
Configuration register 2 for the primary channel pair.
Offset: 0xc04, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAMELEN
rw |
Bits 0-8: Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly..
Bits 16-24: Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase..
Status register for the primary channel pair.
Offset: 0xc08, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
r |
SLVFRMERR
w |
BUSY
r |
Bit 1: Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream..
Allowed values:
0: NO_ERROR: No error has been recorded.
0x1: ERROR: An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
Bit 2: Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair..
Allowed values:
0: LEFT_CHANNEL: Left channel.
0x1: RIGHT_CHANNEL: Right channel.
Bit 3: Data Paused status flag. Applies to all I2S channels.
Allowed values:
0: NOT_PAUSED: Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
0x1: PAUSED: A data pause has been requested and is now in force.
Clock divider, used by all channel pairs.
Offset: 0xc1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Bits 0-11: This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096..
Configuration register 1 for channel pair
Offset: 0xc20, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc28, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
Configuration register 1 for channel pair
Offset: 0xc40, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc48, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
Configuration register 1 for channel pair
Offset: 0xc60, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ONECHANNEL
rw |
PAIRENABLE
rw |
Configuration register 2 for channel pair
Offset: 0xc64, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POSITION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Status register for channel pair
Offset: 0xc68, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAPAUSED
r |
LR
rw |
SLVFRMERR
rw |
BUSY
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
10/12 fields covered.
Bit 2: Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused..
Allowed values:
0: LAST_VALUE: If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair.
0x1: ZERO: If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
Bit 3: Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA..
Allowed values:
0: BIT_24: 48-bit I2S FIFO entries are handled as all 24-bit values.
0x1: BIT_32_16: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
w |
FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe24, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
w |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe34, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
Offset: 0xe44, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA
r |
I2S Module identification
Offset: 0x1dfc, reset: 0xE0900000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Major_Rev
r |
Minor_Rev
r |
Aperture
r |
0x40005000: LPC5411x Input multiplexing (INPUT MUX)
0/51 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | SCT0_INMUX[[0]] | ||||||||||||||||||||||||||||||||
0x4 | SCT0_INMUX[[1]] | ||||||||||||||||||||||||||||||||
0x8 | SCT0_INMUX[[2]] | ||||||||||||||||||||||||||||||||
0xc | SCT0_INMUX[[3]] | ||||||||||||||||||||||||||||||||
0x10 | SCT0_INMUX[[4]] | ||||||||||||||||||||||||||||||||
0x14 | SCT0_INMUX[[5]] | ||||||||||||||||||||||||||||||||
0x18 | SCT0_INMUX[[6]] | ||||||||||||||||||||||||||||||||
0xc0 | PINTSEL[[0]] | ||||||||||||||||||||||||||||||||
0xc4 | PINTSEL[[1]] | ||||||||||||||||||||||||||||||||
0xc8 | PINTSEL[[2]] | ||||||||||||||||||||||||||||||||
0xcc | PINTSEL[[3]] | ||||||||||||||||||||||||||||||||
0xd0 | PINTSEL[[4]] | ||||||||||||||||||||||||||||||||
0xd4 | PINTSEL[[5]] | ||||||||||||||||||||||||||||||||
0xd8 | PINTSEL[[6]] | ||||||||||||||||||||||||||||||||
0xdc | PINTSEL[[7]] | ||||||||||||||||||||||||||||||||
0xe0 | DMA_ITRIG_INMUX[[0]] | ||||||||||||||||||||||||||||||||
0xe4 | DMA_ITRIG_INMUX[[1]] | ||||||||||||||||||||||||||||||||
0xe8 | DMA_ITRIG_INMUX[[2]] | ||||||||||||||||||||||||||||||||
0xec | DMA_ITRIG_INMUX[[3]] | ||||||||||||||||||||||||||||||||
0xf0 | DMA_ITRIG_INMUX[[4]] | ||||||||||||||||||||||||||||||||
0xf4 | DMA_ITRIG_INMUX[[5]] | ||||||||||||||||||||||||||||||||
0xf8 | DMA_ITRIG_INMUX[[6]] | ||||||||||||||||||||||||||||||||
0xfc | DMA_ITRIG_INMUX[[7]] | ||||||||||||||||||||||||||||||||
0x100 | DMA_ITRIG_INMUX[[8]] | ||||||||||||||||||||||||||||||||
0x104 | DMA_ITRIG_INMUX[[9]] | ||||||||||||||||||||||||||||||||
0x108 | DMA_ITRIG_INMUX[[10]] | ||||||||||||||||||||||||||||||||
0x10c | DMA_ITRIG_INMUX[[11]] | ||||||||||||||||||||||||||||||||
0x110 | DMA_ITRIG_INMUX[[12]] | ||||||||||||||||||||||||||||||||
0x114 | DMA_ITRIG_INMUX[[13]] | ||||||||||||||||||||||||||||||||
0x118 | DMA_ITRIG_INMUX[[14]] | ||||||||||||||||||||||||||||||||
0x11c | DMA_ITRIG_INMUX[[15]] | ||||||||||||||||||||||||||||||||
0x120 | DMA_ITRIG_INMUX[[16]] | ||||||||||||||||||||||||||||||||
0x124 | DMA_ITRIG_INMUX[[17]] | ||||||||||||||||||||||||||||||||
0x128 | DMA_ITRIG_INMUX[[18]] | ||||||||||||||||||||||||||||||||
0x12c | DMA_ITRIG_INMUX[[19]] | ||||||||||||||||||||||||||||||||
0x130 | DMA_ITRIG_INMUX[[20]] | ||||||||||||||||||||||||||||||||
0x134 | DMA_ITRIG_INMUX[[21]] | ||||||||||||||||||||||||||||||||
0x138 | DMA_ITRIG_INMUX[[22]] | ||||||||||||||||||||||||||||||||
0x13c | DMA_ITRIG_INMUX[[23]] | ||||||||||||||||||||||||||||||||
0x140 | DMA_ITRIG_INMUX[[24]] | ||||||||||||||||||||||||||||||||
0x144 | DMA_ITRIG_INMUX[[25]] | ||||||||||||||||||||||||||||||||
0x148 | DMA_ITRIG_INMUX[[26]] | ||||||||||||||||||||||||||||||||
0x14c | DMA_ITRIG_INMUX[[27]] | ||||||||||||||||||||||||||||||||
0x150 | DMA_ITRIG_INMUX[[28]] | ||||||||||||||||||||||||||||||||
0x154 | DMA_ITRIG_INMUX[[29]] | ||||||||||||||||||||||||||||||||
0x160 | DMA_OTRIG_INMUX[[0]] | ||||||||||||||||||||||||||||||||
0x164 | DMA_OTRIG_INMUX[[1]] | ||||||||||||||||||||||||||||||||
0x168 | DMA_OTRIG_INMUX[[2]] | ||||||||||||||||||||||||||||||||
0x16c | DMA_OTRIG_INMUX[[3]] | ||||||||||||||||||||||||||||||||
0x180 | FREQMEAS_REF | ||||||||||||||||||||||||||||||||
0x184 | FREQMEAS_TARGET |
Trigger select register for DMA channel
Offset: 0x0, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0x4, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0x8, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0xc, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0x10, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0x14, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Trigger select register for DMA channel
Offset: 0x18, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP_N
rw |
Pin interrupt select register
Offset: 0xc0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xc4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xc8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xcc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xd0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xd4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xd8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Pin interrupt select register
Offset: 0xdc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPIN
rw |
Trigger select register for DMA channel
Offset: 0xe0, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xe4, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xe8, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xec, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xf0, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xf4, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xf8, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0xfc, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x100, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x104, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x108, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x10c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x110, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x114, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x118, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x11c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x120, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x124, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x128, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x12c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x130, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x134, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x138, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x13c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x140, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x144, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x148, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x14c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x150, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
Trigger select register for DMA channel
Offset: 0x154, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Bits 0-4: Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3.
DMA output trigger selection to become DMA trigger
Offset: 0x160, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
DMA output trigger selection to become DMA trigger
Offset: 0x164, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
DMA output trigger selection to become DMA trigger
Offset: 0x168, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
DMA output trigger selection to become DMA trigger
Offset: 0x16c, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INP
rw |
Selection for frequency measurement reference clock
Offset: 0x180, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKIN
rw |
Selection for frequency measurement target clock
Offset: 0x184, reset: 0x1F, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKIN
rw |
0x40001000: LPC5411x I/O pin configuration (IOCON)
1334/1334 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | PIO00 | ||||||||||||||||||||||||||||||||
0x4 | PIO01 | ||||||||||||||||||||||||||||||||
0x8 | PIO02 | ||||||||||||||||||||||||||||||||
0xc | PIO03 | ||||||||||||||||||||||||||||||||
0x10 | PIO04 | ||||||||||||||||||||||||||||||||
0x14 | PIO05 | ||||||||||||||||||||||||||||||||
0x18 | PIO06 | ||||||||||||||||||||||||||||||||
0x1c | PIO07 | ||||||||||||||||||||||||||||||||
0x20 | PIO08 | ||||||||||||||||||||||||||||||||
0x24 | PIO09 | ||||||||||||||||||||||||||||||||
0x28 | PIO010 | ||||||||||||||||||||||||||||||||
0x2c | PIO011 | ||||||||||||||||||||||||||||||||
0x30 | PIO012 | ||||||||||||||||||||||||||||||||
0x34 | PIO013 | ||||||||||||||||||||||||||||||||
0x38 | PIO014 | ||||||||||||||||||||||||||||||||
0x3c | PIO015 | ||||||||||||||||||||||||||||||||
0x40 | PIO016 | ||||||||||||||||||||||||||||||||
0x44 | PIO017 | ||||||||||||||||||||||||||||||||
0x48 | PIO018 | ||||||||||||||||||||||||||||||||
0x4c | PIO019 | ||||||||||||||||||||||||||||||||
0x50 | PIO020 | ||||||||||||||||||||||||||||||||
0x54 | PIO021 | ||||||||||||||||||||||||||||||||
0x58 | PIO022 | ||||||||||||||||||||||||||||||||
0x5c | PIO023 | ||||||||||||||||||||||||||||||||
0x60 | PIO024 | ||||||||||||||||||||||||||||||||
0x64 | PIO025 | ||||||||||||||||||||||||||||||||
0x68 | PIO026 | ||||||||||||||||||||||||||||||||
0x6c | PIO027 | ||||||||||||||||||||||||||||||||
0x70 | PIO028 | ||||||||||||||||||||||||||||||||
0x74 | PIO029 | ||||||||||||||||||||||||||||||||
0x78 | PIO030 | ||||||||||||||||||||||||||||||||
0x7c | PIO031 | ||||||||||||||||||||||||||||||||
0x80 | PIO10 | ||||||||||||||||||||||||||||||||
0x84 | PIO11 | ||||||||||||||||||||||||||||||||
0x88 | PIO12 | ||||||||||||||||||||||||||||||||
0x8c | PIO13 | ||||||||||||||||||||||||||||||||
0x90 | PIO14 | ||||||||||||||||||||||||||||||||
0x94 | PIO15 | ||||||||||||||||||||||||||||||||
0x98 | PIO16 | ||||||||||||||||||||||||||||||||
0x9c | PIO17 | ||||||||||||||||||||||||||||||||
0xa0 | PIO18 | ||||||||||||||||||||||||||||||||
0xa4 | PIO19 | ||||||||||||||||||||||||||||||||
0xa8 | PIO110 | ||||||||||||||||||||||||||||||||
0xac | PIO111 | ||||||||||||||||||||||||||||||||
0xb0 | PIO112 | ||||||||||||||||||||||||||||||||
0xb4 | PIO113 | ||||||||||||||||||||||||||||||||
0xb8 | PIO114 | ||||||||||||||||||||||||||||||||
0xbc | PIO115 | ||||||||||||||||||||||||||||||||
0xc0 | PIO116 | ||||||||||||||||||||||||||||||||
0xc4 | PIO117 | ||||||||||||||||||||||||||||||||
0xc8 | PIO118 | ||||||||||||||||||||||||||||||||
0xcc | PIO119 | ||||||||||||||||||||||||||||||||
0xd0 | PIO120 | ||||||||||||||||||||||||||||||||
0xd4 | PIO121 | ||||||||||||||||||||||||||||||||
0xd8 | PIO122 | ||||||||||||||||||||||||||||||||
0xdc | PIO123 | ||||||||||||||||||||||||||||||||
0xe0 | PIO124 | ||||||||||||||||||||||||||||||||
0xe4 | PIO125 | ||||||||||||||||||||||||||||||||
0xe8 | PIO126 | ||||||||||||||||||||||||||||||||
0xec | PIO127 | ||||||||||||||||||||||||||||||||
0xf0 | PIO128 | ||||||||||||||||||||||||||||||||
0xf4 | PIO129 | ||||||||||||||||||||||||||||||||
0xf8 | PIO130 | ||||||||||||||||||||||||||||||||
0xfc | PIO131 | ||||||||||||||||||||||||||||||||
0x100 | PIO20 | ||||||||||||||||||||||||||||||||
0x104 | PIO21 | ||||||||||||||||||||||||||||||||
0x108 | PIO22 | ||||||||||||||||||||||||||||||||
0x10c | PIO23 | ||||||||||||||||||||||||||||||||
0x110 | PIO24 | ||||||||||||||||||||||||||||||||
0x114 | PIO25 | ||||||||||||||||||||||||||||||||
0x118 | PIO26 | ||||||||||||||||||||||||||||||||
0x11c | PIO27 | ||||||||||||||||||||||||||||||||
0x120 | PIO28 | ||||||||||||||||||||||||||||||||
0x124 | PIO29 | ||||||||||||||||||||||||||||||||
0x128 | PIO210 | ||||||||||||||||||||||||||||||||
0x12c | PIO211 | ||||||||||||||||||||||||||||||||
0x130 | PIO212 | ||||||||||||||||||||||||||||||||
0x134 | PIO213 | ||||||||||||||||||||||||||||||||
0x138 | PIO214 | ||||||||||||||||||||||||||||||||
0x13c | PIO215 | ||||||||||||||||||||||||||||||||
0x140 | PIO216 | ||||||||||||||||||||||||||||||||
0x144 | PIO217 | ||||||||||||||||||||||||||||||||
0x148 | PIO218 | ||||||||||||||||||||||||||||||||
0x14c | PIO219 | ||||||||||||||||||||||||||||||||
0x150 | PIO220 | ||||||||||||||||||||||||||||||||
0x154 | PIO221 | ||||||||||||||||||||||||||||||||
0x158 | PIO222 | ||||||||||||||||||||||||||||||||
0x15c | PIO223 | ||||||||||||||||||||||||||||||||
0x160 | PIO224 | ||||||||||||||||||||||||||||||||
0x164 | PIO225 | ||||||||||||||||||||||||||||||||
0x168 | PIO226 | ||||||||||||||||||||||||||||||||
0x16c | PIO227 | ||||||||||||||||||||||||||||||||
0x170 | PIO228 | ||||||||||||||||||||||||||||||||
0x174 | PIO229 | ||||||||||||||||||||||||||||||||
0x178 | PIO230 | ||||||||||||||||||||||||||||||||
0x17c | PIO231 | ||||||||||||||||||||||||||||||||
0x180 | PIO30 | ||||||||||||||||||||||||||||||||
0x184 | PIO31 | ||||||||||||||||||||||||||||||||
0x188 | PIO32 | ||||||||||||||||||||||||||||||||
0x18c | PIO33 | ||||||||||||||||||||||||||||||||
0x190 | PIO34 | ||||||||||||||||||||||||||||||||
0x194 | PIO35 | ||||||||||||||||||||||||||||||||
0x198 | PIO36 | ||||||||||||||||||||||||||||||||
0x19c | PIO37 | ||||||||||||||||||||||||||||||||
0x1a0 | PIO38 | ||||||||||||||||||||||||||||||||
0x1a4 | PIO39 | ||||||||||||||||||||||||||||||||
0x1a8 | PIO310 | ||||||||||||||||||||||||||||||||
0x1ac | PIO311 | ||||||||||||||||||||||||||||||||
0x1b0 | PIO312 | ||||||||||||||||||||||||||||||||
0x1b4 | PIO313 | ||||||||||||||||||||||||||||||||
0x1b8 | PIO314 | ||||||||||||||||||||||||||||||||
0x1bc | PIO315 | ||||||||||||||||||||||||||||||||
0x1c0 | PIO316 | ||||||||||||||||||||||||||||||||
0x1c4 | PIO317 | ||||||||||||||||||||||||||||||||
0x1c8 | PIO318 | ||||||||||||||||||||||||||||||||
0x1cc | PIO319 | ||||||||||||||||||||||||||||||||
0x1d0 | PIO320 | ||||||||||||||||||||||||||||||||
0x1d4 | PIO321 | ||||||||||||||||||||||||||||||||
0x1d8 | PIO322 | ||||||||||||||||||||||||||||||||
0x1dc | PIO323 | ||||||||||||||||||||||||||||||||
0x1e0 | PIO324 | ||||||||||||||||||||||||||||||||
0x1e4 | PIO325 | ||||||||||||||||||||||||||||||||
0x1e8 | PIO326 | ||||||||||||||||||||||||||||||||
0x1ec | PIO327 | ||||||||||||||||||||||||||||||||
0x1f0 | PIO328 | ||||||||||||||||||||||||||||||||
0x1f4 | PIO329 | ||||||||||||||||||||||||||||||||
0x1f8 | PIO330 | ||||||||||||||||||||||||||||||||
0x1fc | PIO331 | ||||||||||||||||||||||||||||||||
0x200 | PIO40 | ||||||||||||||||||||||||||||||||
0x204 | PIO41 | ||||||||||||||||||||||||||||||||
0x208 | PIO42 | ||||||||||||||||||||||||||||||||
0x20c | PIO43 | ||||||||||||||||||||||||||||||||
0x210 | PIO44 | ||||||||||||||||||||||||||||||||
0x214 | PIO45 | ||||||||||||||||||||||||||||||||
0x218 | PIO46 | ||||||||||||||||||||||||||||||||
0x21c | PIO47 | ||||||||||||||||||||||||||||||||
0x220 | PIO48 | ||||||||||||||||||||||||||||||||
0x224 | PIO49 | ||||||||||||||||||||||||||||||||
0x228 | PIO410 | ||||||||||||||||||||||||||||||||
0x22c | PIO411 | ||||||||||||||||||||||||||||||||
0x230 | PIO412 | ||||||||||||||||||||||||||||||||
0x234 | PIO413 | ||||||||||||||||||||||||||||||||
0x238 | PIO414 | ||||||||||||||||||||||||||||||||
0x23c | PIO415 | ||||||||||||||||||||||||||||||||
0x240 | PIO416 | ||||||||||||||||||||||||||||||||
0x244 | PIO417 | ||||||||||||||||||||||||||||||||
0x248 | PIO418 | ||||||||||||||||||||||||||||||||
0x24c | PIO419 | ||||||||||||||||||||||||||||||||
0x250 | PIO420 | ||||||||||||||||||||||||||||||||
0x254 | PIO421 | ||||||||||||||||||||||||||||||||
0x258 | PIO422 | ||||||||||||||||||||||||||||||||
0x25c | PIO423 | ||||||||||||||||||||||||||||||||
0x260 | PIO424 | ||||||||||||||||||||||||||||||||
0x264 | PIO425 | ||||||||||||||||||||||||||||||||
0x268 | PIO426 | ||||||||||||||||||||||||||||||||
0x26c | PIO427 | ||||||||||||||||||||||||||||||||
0x270 | PIO428 | ||||||||||||||||||||||||||||||||
0x274 | PIO429 | ||||||||||||||||||||||||||||||||
0x278 | PIO430 | ||||||||||||||||||||||||||||||||
0x27c | PIO431 | ||||||||||||||||||||||||||||||||
0x280 | PIO50 | ||||||||||||||||||||||||||||||||
0x284 | PIO51 | ||||||||||||||||||||||||||||||||
0x288 | PIO52 | ||||||||||||||||||||||||||||||||
0x28c | PIO53 | ||||||||||||||||||||||||||||||||
0x290 | PIO54 | ||||||||||||||||||||||||||||||||
0x294 | PIO55 | ||||||||||||||||||||||||||||||||
0x298 | PIO56 | ||||||||||||||||||||||||||||||||
0x29c | PIO57 | ||||||||||||||||||||||||||||||||
0x2a0 | PIO58 | ||||||||||||||||||||||||||||||||
0x2a4 | PIO59 | ||||||||||||||||||||||||||||||||
0x2a8 | PIO510 | ||||||||||||||||||||||||||||||||
0x2ac | PIO511 | ||||||||||||||||||||||||||||||||
0x2b0 | PIO512 | ||||||||||||||||||||||||||||||||
0x2b4 | PIO513 | ||||||||||||||||||||||||||||||||
0x2b8 | PIO514 | ||||||||||||||||||||||||||||||||
0x2bc | PIO515 | ||||||||||||||||||||||||||||||||
0x2c0 | PIO516 | ||||||||||||||||||||||||||||||||
0x2c4 | PIO517 | ||||||||||||||||||||||||||||||||
0x2c8 | PIO518 | ||||||||||||||||||||||||||||||||
0x2cc | PIO519 | ||||||||||||||||||||||||||||||||
0x2d0 | PIO520 | ||||||||||||||||||||||||||||||||
0x2d4 | PIO521 | ||||||||||||||||||||||||||||||||
0x2d8 | PIO522 | ||||||||||||||||||||||||||||||||
0x2dc | PIO523 | ||||||||||||||||||||||||||||||||
0x2e0 | PIO524 | ||||||||||||||||||||||||||||||||
0x2e4 | PIO525 | ||||||||||||||||||||||||||||||||
0x2e8 | PIO526 | ||||||||||||||||||||||||||||||||
0x2ec | PIO527 | ||||||||||||||||||||||||||||||||
0x2f0 | PIO528 | ||||||||||||||||||||||||||||||||
0x2f4 | PIO529 | ||||||||||||||||||||||||||||||||
0x2f8 | PIO530 | ||||||||||||||||||||||||||||||||
0x2fc | PIO531 |
Digital I/O control for port 0 pins PIO0_0
Offset: 0x0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_1
Offset: 0x4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_2
Offset: 0x8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_3
Offset: 0xc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_4
Offset: 0x10, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_5
Offset: 0x14, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_6
Offset: 0x18, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_7
Offset: 0x1c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_8
Offset: 0x20, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_9
Offset: 0x24, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_10
Offset: 0x28, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_11
Offset: 0x2c, reset: 0x326, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_12
Offset: 0x30, reset: 0x326, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_13
Offset: 0x34, reset: 0x340, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bit 10: Controls the current sink capability of the pin..
Allowed values:
0: LOW: Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0x1: HIGH: High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
Digital I/O control for port 0 pins PIO0_14
Offset: 0x38, reset: 0x340, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bit 10: Controls the current sink capability of the pin..
Allowed values:
0: LOW: Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0x1: HIGH: High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
Digital I/O control for port 0 pins PIO0_15
Offset: 0x3c, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_16
Offset: 0x40, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_17
Offset: 0x44, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_18
Offset: 0x48, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_19
Offset: 0x4c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_20
Offset: 0x50, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_21
Offset: 0x54, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_22
Offset: 0x58, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_23
Offset: 0x5c, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_24
Offset: 0x60, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_25
Offset: 0x64, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_26
Offset: 0x68, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_27
Offset: 0x6c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_28
Offset: 0x70, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_29
Offset: 0x74, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_30
Offset: 0x78, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 0 pins PIO0_31
Offset: 0x7c, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_0
Offset: 0x80, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_1
Offset: 0x84, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_2
Offset: 0x88, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_3
Offset: 0x8c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_4
Offset: 0x90, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_5
Offset: 0x94, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_6
Offset: 0x98, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_7
Offset: 0x9c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_8
Offset: 0xa0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_9
Offset: 0xa4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_10
Offset: 0xa8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_11
Offset: 0xac, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_12
Offset: 0xb0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_13
Offset: 0xb4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_14
Offset: 0xb8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_15
Offset: 0xbc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_16
Offset: 0xc0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_17
Offset: 0xc4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_18
Offset: 0xc8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_19
Offset: 0xcc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_20
Offset: 0xd0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_21
Offset: 0xd4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_22
Offset: 0xd8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_23
Offset: 0xdc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_24
Offset: 0xe0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_25
Offset: 0xe4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_26
Offset: 0xe8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_27
Offset: 0xec, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_28
Offset: 0xf0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_29
Offset: 0xf4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_30
Offset: 0xf8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 1 pins PIO1_31
Offset: 0xfc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_0
Offset: 0x100, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_1
Offset: 0x104, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_2
Offset: 0x108, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_3
Offset: 0x10c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_4
Offset: 0x110, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_5
Offset: 0x114, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_6
Offset: 0x118, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_7
Offset: 0x11c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_8
Offset: 0x120, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_9
Offset: 0x124, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_10
Offset: 0x128, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_11
Offset: 0x12c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_12
Offset: 0x130, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_13
Offset: 0x134, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_14
Offset: 0x138, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_15
Offset: 0x13c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_16
Offset: 0x140, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_17
Offset: 0x144, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_18
Offset: 0x148, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_19
Offset: 0x14c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_20
Offset: 0x150, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_21
Offset: 0x154, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_22
Offset: 0x158, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_23
Offset: 0x15c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_24
Offset: 0x160, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_25
Offset: 0x164, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_26
Offset: 0x168, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_27
Offset: 0x16c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_28
Offset: 0x170, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_29
Offset: 0x174, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_30
Offset: 0x178, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 2 pins PIO2_31
Offset: 0x17c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_0
Offset: 0x180, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_1
Offset: 0x184, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_2
Offset: 0x188, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_3
Offset: 0x18c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_4
Offset: 0x190, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_5
Offset: 0x194, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_6
Offset: 0x198, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_7
Offset: 0x19c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_8
Offset: 0x1a0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_9
Offset: 0x1a4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_10
Offset: 0x1a8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_11
Offset: 0x1ac, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_12
Offset: 0x1b0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_13
Offset: 0x1b4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_14
Offset: 0x1b8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_15
Offset: 0x1bc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_16
Offset: 0x1c0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_17
Offset: 0x1c4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_18
Offset: 0x1c8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_19
Offset: 0x1cc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_20
Offset: 0x1d0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_21
Offset: 0x1d4, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_22
Offset: 0x1d8, reset: 0x320, access: read-write
6/6 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_23
Offset: 0x1dc, reset: 0x340, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bit 10: Controls the current sink capability of the pin..
Allowed values:
0: LOW: Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0x1: HIGH: High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
Digital I/O control for port 3 pins PIO3_24
Offset: 0x1e0, reset: 0x340, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bit 10: Controls the current sink capability of the pin..
Allowed values:
0: LOW: Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0x1: HIGH: High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
Digital I/O control for port 3 pins PIO3_25
Offset: 0x1e4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_26
Offset: 0x1e8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_27
Offset: 0x1ec, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_28
Offset: 0x1f0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_29
Offset: 0x1f4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_30
Offset: 0x1f8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 3 pins PIO3_31
Offset: 0x1fc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_0
Offset: 0x200, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_1
Offset: 0x204, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_2
Offset: 0x208, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_3
Offset: 0x20c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_4
Offset: 0x210, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_5
Offset: 0x214, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_6
Offset: 0x218, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_7
Offset: 0x21c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_8
Offset: 0x220, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_9
Offset: 0x224, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_10
Offset: 0x228, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_11
Offset: 0x22c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_12
Offset: 0x230, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_13
Offset: 0x234, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_14
Offset: 0x238, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_15
Offset: 0x23c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_16
Offset: 0x240, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_17
Offset: 0x244, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_18
Offset: 0x248, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_19
Offset: 0x24c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_20
Offset: 0x250, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_21
Offset: 0x254, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_22
Offset: 0x258, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_23
Offset: 0x25c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_24
Offset: 0x260, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_25
Offset: 0x264, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_26
Offset: 0x268, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_27
Offset: 0x26c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_28
Offset: 0x270, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_29
Offset: 0x274, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_30
Offset: 0x278, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 4 pins PIO4_31
Offset: 0x27c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_0
Offset: 0x280, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_1
Offset: 0x284, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_2
Offset: 0x288, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_3
Offset: 0x28c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_4
Offset: 0x290, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_5
Offset: 0x294, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_6
Offset: 0x298, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_7
Offset: 0x29c, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_8
Offset: 0x2a0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_9
Offset: 0x2a4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_10
Offset: 0x2a8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_11
Offset: 0x2ac, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_12
Offset: 0x2b0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_13
Offset: 0x2b4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_14
Offset: 0x2b8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_15
Offset: 0x2bc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_16
Offset: 0x2c0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_17
Offset: 0x2c4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_18
Offset: 0x2c8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_19
Offset: 0x2cc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_20
Offset: 0x2d0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_21
Offset: 0x2d4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_22
Offset: 0x2d8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_23
Offset: 0x2dc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_24
Offset: 0x2e0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_25
Offset: 0x2e4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_26
Offset: 0x2e8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_27
Offset: 0x2ec, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_28
Offset: 0x2f0, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_29
Offset: 0x2f4, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_30
Offset: 0x2f8, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
Digital I/O control for port 5 pins PIO5_31
Offset: 0x2fc, reset: 0x320, access: read-write
7/7 fields covered.
Bits 0-3: Selects pin function..
Allowed values:
0: ALT0: Alternative connection 0.
0x1: ALT1: Alternative connection 1.
0x2: ALT2: Alternative connection 2.
0x3: ALT3: Alternative connection 3.
0x4: ALT4: Alternative connection 4.
0x5: ALT5: Alternative connection 5.
0x6: ALT6: Alternative connection 6.
0x7: ALT7: Alternative connection 7.
Bits 4-5: Selects function mode (on-chip pull-up/pull-down resistor control)..
Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.
0xe0000000: Instrumentation Trace Macrocell Registers
25/96 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | STIM0_READ | ||||||||||||||||||||||||||||||||
0x0 | STIM0_WRITE | ||||||||||||||||||||||||||||||||
0x4 | STIM1_READ | ||||||||||||||||||||||||||||||||
0x4 | STIM1_WRITE | ||||||||||||||||||||||||||||||||
0x8 | STIM2_READ | ||||||||||||||||||||||||||||||||
0x8 | STIM2_WRITE | ||||||||||||||||||||||||||||||||
0xc | STIM3_READ | ||||||||||||||||||||||||||||||||
0xc | STIM3_WRITE | ||||||||||||||||||||||||||||||||
0x10 | STIM4_READ | ||||||||||||||||||||||||||||||||
0x10 | STIM4_WRITE | ||||||||||||||||||||||||||||||||
0x14 | STIM5_READ | ||||||||||||||||||||||||||||||||
0x14 | STIM5_WRITE | ||||||||||||||||||||||||||||||||
0x18 | STIM6_READ | ||||||||||||||||||||||||||||||||
0x18 | STIM6_WRITE | ||||||||||||||||||||||||||||||||
0x1c | STIM7_READ | ||||||||||||||||||||||||||||||||
0x1c | STIM7_WRITE | ||||||||||||||||||||||||||||||||
0x20 | STIM8_READ | ||||||||||||||||||||||||||||||||
0x20 | STIM8_WRITE | ||||||||||||||||||||||||||||||||
0x24 | STIM9_READ | ||||||||||||||||||||||||||||||||
0x24 | STIM9_WRITE | ||||||||||||||||||||||||||||||||
0x28 | STIM10_READ | ||||||||||||||||||||||||||||||||
0x28 | STIM10_WRITE | ||||||||||||||||||||||||||||||||
0x2c | STIM11_READ | ||||||||||||||||||||||||||||||||
0x2c | STIM11_WRITE | ||||||||||||||||||||||||||||||||
0x30 | STIM12_READ | ||||||||||||||||||||||||||||||||
0x30 | STIM12_WRITE | ||||||||||||||||||||||||||||||||
0x34 | STIM13_READ | ||||||||||||||||||||||||||||||||
0x34 | STIM13_WRITE | ||||||||||||||||||||||||||||||||
0x38 | STIM14_READ | ||||||||||||||||||||||||||||||||
0x38 | STIM14_WRITE | ||||||||||||||||||||||||||||||||
0x3c | STIM15_READ | ||||||||||||||||||||||||||||||||
0x3c | STIM15_WRITE | ||||||||||||||||||||||||||||||||
0x40 | STIM16_READ | ||||||||||||||||||||||||||||||||
0x40 | STIM16_WRITE | ||||||||||||||||||||||||||||||||
0x44 | STIM17_READ | ||||||||||||||||||||||||||||||||
0x44 | STIM17_WRITE | ||||||||||||||||||||||||||||||||
0x48 | STIM18_READ | ||||||||||||||||||||||||||||||||
0x48 | STIM18_WRITE | ||||||||||||||||||||||||||||||||
0x4c | STIM19_READ | ||||||||||||||||||||||||||||||||
0x4c | STIM19_WRITE | ||||||||||||||||||||||||||||||||
0x50 | STIM20_READ | ||||||||||||||||||||||||||||||||
0x50 | STIM20_WRITE | ||||||||||||||||||||||||||||||||
0x54 | STIM21_READ | ||||||||||||||||||||||||||||||||
0x54 | STIM21_WRITE | ||||||||||||||||||||||||||||||||
0x58 | STIM22_READ | ||||||||||||||||||||||||||||||||
0x58 | STIM22_WRITE | ||||||||||||||||||||||||||||||||
0x5c | STIM23_READ | ||||||||||||||||||||||||||||||||
0x5c | STIM23_WRITE | ||||||||||||||||||||||||||||||||
0x60 | STIM24_READ | ||||||||||||||||||||||||||||||||
0x60 | STIM24_WRITE | ||||||||||||||||||||||||||||||||
0x64 | STIM25_READ | ||||||||||||||||||||||||||||||||
0x64 | STIM25_WRITE | ||||||||||||||||||||||||||||||||
0x68 | STIM26_READ | ||||||||||||||||||||||||||||||||
0x68 | STIM26_WRITE | ||||||||||||||||||||||||||||||||
0x6c | STIM27_READ | ||||||||||||||||||||||||||||||||
0x6c | STIM27_WRITE | ||||||||||||||||||||||||||||||||
0x70 | STIM28_READ | ||||||||||||||||||||||||||||||||
0x70 | STIM28_WRITE | ||||||||||||||||||||||||||||||||
0x74 | STIM29_READ | ||||||||||||||||||||||||||||||||
0x74 | STIM29_WRITE | ||||||||||||||||||||||||||||||||
0x78 | STIM30_READ | ||||||||||||||||||||||||||||||||
0x78 | STIM30_WRITE | ||||||||||||||||||||||||||||||||
0x7c | STIM31_READ | ||||||||||||||||||||||||||||||||
0x7c | STIM31_WRITE | ||||||||||||||||||||||||||||||||
0xe00 | TER | ||||||||||||||||||||||||||||||||
0xe40 | TPR | ||||||||||||||||||||||||||||||||
0xe80 | TCR | ||||||||||||||||||||||||||||||||
0xfb0 | LAR | ||||||||||||||||||||||||||||||||
0xfb4 | LSR | ||||||||||||||||||||||||||||||||
0xfd0 | PID4 | ||||||||||||||||||||||||||||||||
0xfd4 | PID5 | ||||||||||||||||||||||||||||||||
0xfd8 | PID6 | ||||||||||||||||||||||||||||||||
0xfdc | PID7 | ||||||||||||||||||||||||||||||||
0xfe0 | PID0 | ||||||||||||||||||||||||||||||||
0xfe4 | PID1 | ||||||||||||||||||||||||||||||||
0xfe8 | PID2 | ||||||||||||||||||||||||||||||||
0xfec | PID3 | ||||||||||||||||||||||||||||||||
0xff0 | CID0 | ||||||||||||||||||||||||||||||||
0xff4 | CID1 | ||||||||||||||||||||||||||||||||
0xff8 | CID2 | ||||||||||||||||||||||||||||||||
0xffc | CID3 |
Stimulus Port Register 0 (for reading)
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 0 (for writing)
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 1 (for reading)
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 1 (for writing)
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 2 (for reading)
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 2 (for writing)
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 3 (for reading)
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 3 (for writing)
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 4 (for reading)
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 4 (for writing)
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 5 (for reading)
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 5 (for writing)
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 6 (for reading)
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 6 (for writing)
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 7 (for reading)
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 7 (for writing)
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 8 (for reading)
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 8 (for writing)
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 9 (for reading)
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 9 (for writing)
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 10 (for reading)
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 10 (for writing)
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 11 (for reading)
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 11 (for writing)
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 12 (for reading)
Offset: 0x30, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 12 (for writing)
Offset: 0x30, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 13 (for reading)
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 13 (for writing)
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 14 (for reading)
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 14 (for writing)
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 15 (for reading)
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 15 (for writing)
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 16 (for reading)
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 16 (for writing)
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 17 (for reading)
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 17 (for writing)
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 18 (for reading)
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 18 (for writing)
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 19 (for reading)
Offset: 0x4c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 19 (for writing)
Offset: 0x4c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 20 (for reading)
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 20 (for writing)
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 21 (for reading)
Offset: 0x54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 21 (for writing)
Offset: 0x54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 22 (for reading)
Offset: 0x58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 22 (for writing)
Offset: 0x58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 23 (for reading)
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 23 (for writing)
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 24 (for reading)
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 24 (for writing)
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 25 (for reading)
Offset: 0x64, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 25 (for writing)
Offset: 0x64, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 26 (for reading)
Offset: 0x68, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 26 (for writing)
Offset: 0x68, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 27 (for reading)
Offset: 0x6c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 27 (for writing)
Offset: 0x6c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 28 (for reading)
Offset: 0x70, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 28 (for writing)
Offset: 0x70, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 29 (for reading)
Offset: 0x74, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 29 (for writing)
Offset: 0x74, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 30 (for reading)
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 30 (for writing)
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Stimulus Port Register 31 (for reading)
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOREADY
rw |
Stimulus Port Register 31 (for writing)
Offset: 0x7c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMULUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMULUS
rw |
Trace Enable Register
Offset: 0xe00, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STIMENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIMENA
rw |
Trace Privilege Register
Offset: 0xe40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRIVMASK
rw |
Trace Control Register
Offset: 0xe80, reset: 0, access: read-write
8/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BUSY
r |
TraceBusID
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GTSFREQ
rw |
TSPrescale
rw |
SWOENA
rw |
TXENA
rw |
SYNCENA
rw |
TSENA
rw |
ITMENA
rw |
Bits 10-11: Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps..
Allowed values:
0: GTSFREQ_0: Disable generation of global timestamps.
0x1: GTSFREQ_1: Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles.
0x2: GTSFREQ_2: Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles.
0x3: GTSFREQ_3: Generate a timestamp after every packet, if the output FIFO is empty.
Lock Access Register
Offset: 0xfb0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WriteAccessCode
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WriteAccessCode
rw |
Lock Status Register
Offset: 0xfb4, reset: 0x1, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
s8BIT
r |
STATUS
r |
IMP
r |
Peripheral Identification Register 4.
Offset: 0xfd0, reset: 0x4, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
c4KB
r |
JEP106
r |
Peripheral Identification Register 5.
Offset: 0xfd4, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 6.
Offset: 0xfd8, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 7.
Offset: 0xfdc, reset: 0, access: read-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Peripheral Identification Register 0.
Offset: 0xfe0, reset: 0x2, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PartNumber
r |
Peripheral Identification Register 1.
Offset: 0xfe4, reset: 0xB0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEP106_identity_code
r |
PartNumber
r |
Peripheral Identification Register 2.
Offset: 0xfe8, reset: 0x3B, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Revision
r |
JEP106_identity_code
r |
Peripheral Identification Register 3.
Offset: 0xfec, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RevAnd
r |
CustomerModified
r |
Component Identification Register 0.
Offset: 0xff0, reset: 0xD, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
Component Identification Register 1.
Offset: 0xff4, reset: 0xE0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ComponentClass
r |
Preamble
r |
Component Identification Register 2.
Offset: 0xff8, reset: 0x5, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
Component Identification Register 3.
Offset: 0xffc, reset: 0xB1, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Preamble
r |
0x4000d000: LPC5411x Multi-Rate Timer (MRT)
31/40 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | INTVAL [0] | ||||||||||||||||||||||||||||||||
0x4 | TIMER [0] | ||||||||||||||||||||||||||||||||
0x8 | CTRL [0] | ||||||||||||||||||||||||||||||||
0xc | STAT [0] | ||||||||||||||||||||||||||||||||
0x10 | INTVAL [1] | ||||||||||||||||||||||||||||||||
0x14 | TIMER [1] | ||||||||||||||||||||||||||||||||
0x18 | CTRL [1] | ||||||||||||||||||||||||||||||||
0x1c | STAT [1] | ||||||||||||||||||||||||||||||||
0x20 | INTVAL [2] | ||||||||||||||||||||||||||||||||
0x24 | TIMER [2] | ||||||||||||||||||||||||||||||||
0x28 | CTRL [2] | ||||||||||||||||||||||||||||||||
0x2c | STAT [2] | ||||||||||||||||||||||||||||||||
0x30 | INTVAL [3] | ||||||||||||||||||||||||||||||||
0x34 | TIMER [3] | ||||||||||||||||||||||||||||||||
0x38 | CTRL [3] | ||||||||||||||||||||||||||||||||
0x3c | STAT [3] | ||||||||||||||||||||||||||||||||
0xf0 | MODCFG | ||||||||||||||||||||||||||||||||
0xf4 | IDLE_CH | ||||||||||||||||||||||||||||||||
0xf8 | IRQ_FLAG |
MRT Time interval value register. This value is loaded into the TIMER register.
Offset: 0x0, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOAD
rw |
IVALUE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IVALUE
rw |
Bits 0-23: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..
Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..
Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
MRT Timer register. This register reads the value of the down-counter.
Offset: 0x4, reset: 0xFFFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALUE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE
r |
Bits 0-23: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..
MRT Control register. This register controls the MRT modes.
Offset: 0x8, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE
rw |
INTEN
rw |
MRT Status register.
Offset: 0xc, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INUSE
rw |
RUN
rw |
INTFLAG
rw |
Bit 0: Monitors the interrupt flag..
Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
MRT Time interval value register. This value is loaded into the TIMER register.
Offset: 0x10, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOAD
rw |
IVALUE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IVALUE
rw |
Bits 0-23: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..
Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..
Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
MRT Timer register. This register reads the value of the down-counter.
Offset: 0x14, reset: 0xFFFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALUE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE
r |
Bits 0-23: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..
MRT Control register. This register controls the MRT modes.
Offset: 0x18, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE
rw |
INTEN
rw |
MRT Status register.
Offset: 0x1c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INUSE
rw |
RUN
rw |
INTFLAG
rw |
Bit 0: Monitors the interrupt flag..
Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
MRT Time interval value register. This value is loaded into the TIMER register.
Offset: 0x20, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOAD
rw |
IVALUE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IVALUE
rw |
Bits 0-23: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..
Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..
Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
MRT Timer register. This register reads the value of the down-counter.
Offset: 0x24, reset: 0xFFFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALUE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE
r |
Bits 0-23: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..
MRT Control register. This register controls the MRT modes.
Offset: 0x28, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE
rw |
INTEN
rw |
MRT Status register.
Offset: 0x2c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INUSE
rw |
RUN
rw |
INTFLAG
rw |
Bit 0: Monitors the interrupt flag..
Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
MRT Time interval value register. This value is loaded into the TIMER register.
Offset: 0x30, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOAD
rw |
IVALUE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IVALUE
rw |
Bits 0-23: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..
Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..
Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
MRT Timer register. This register reads the value of the down-counter.
Offset: 0x34, reset: 0xFFFFFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALUE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE
r |
Bits 0-23: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..
MRT Control register. This register controls the MRT modes.
Offset: 0x38, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE
rw |
INTEN
rw |
MRT Status register.
Offset: 0x3c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INUSE
rw |
RUN
rw |
INTFLAG
rw |
Bit 0: Monitors the interrupt flag..
Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature.
Offset: 0xf0, reset: 0x173, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MULTITASK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOB
rw |
NOC
rw |
Idle channel register. This register returns the number of the first idle channel.
Offset: 0xf4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHAN
r |
Bits 4-7: Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details..
Global interrupt flag register
Offset: 0xf8, reset: 0, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GFLAG3
rw |
GFLAG2
rw |
GFLAG1
rw |
GFLAG0
rw |
Bit 0: Monitors the interrupt flag of TIMER0..
Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0xe000e100: Nested Vectored Interrupt Controller
0/127 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | NVICISER0 | ||||||||||||||||||||||||||||||||
0x4 | NVICISER1 | ||||||||||||||||||||||||||||||||
0x8 | NVICISER2 | ||||||||||||||||||||||||||||||||
0xc | NVICISER3 | ||||||||||||||||||||||||||||||||
0x80 | NVICICER0 | ||||||||||||||||||||||||||||||||
0x84 | NVICICER1 | ||||||||||||||||||||||||||||||||
0x88 | NVICICER2 | ||||||||||||||||||||||||||||||||
0x8c | NVICICER3 | ||||||||||||||||||||||||||||||||
0x100 | NVICISPR0 | ||||||||||||||||||||||||||||||||
0x104 | NVICISPR1 | ||||||||||||||||||||||||||||||||
0x108 | NVICISPR2 | ||||||||||||||||||||||||||||||||
0x10c | NVICISPR3 | ||||||||||||||||||||||||||||||||
0x180 | NVICICPR0 | ||||||||||||||||||||||||||||||||
0x184 | NVICICPR1 | ||||||||||||||||||||||||||||||||
0x188 | NVICICPR2 | ||||||||||||||||||||||||||||||||
0x18c | NVICICPR3 | ||||||||||||||||||||||||||||||||
0x200 | NVICIABR0 | ||||||||||||||||||||||||||||||||
0x204 | NVICIABR1 | ||||||||||||||||||||||||||||||||
0x208 | NVICIABR2 | ||||||||||||||||||||||||||||||||
0x20c | NVICIABR3 | ||||||||||||||||||||||||||||||||
0x300 | NVICIP0 | ||||||||||||||||||||||||||||||||
0x301 | NVICIP1 | ||||||||||||||||||||||||||||||||
0x302 | NVICIP2 | ||||||||||||||||||||||||||||||||
0x303 | NVICIP3 | ||||||||||||||||||||||||||||||||
0x304 | NVICIP4 | ||||||||||||||||||||||||||||||||
0x305 | NVICIP5 | ||||||||||||||||||||||||||||||||
0x306 | NVICIP6 | ||||||||||||||||||||||||||||||||
0x307 | NVICIP7 | ||||||||||||||||||||||||||||||||
0x308 | NVICIP8 | ||||||||||||||||||||||||||||||||
0x309 | NVICIP9 | ||||||||||||||||||||||||||||||||
0x30a | NVICIP10 | ||||||||||||||||||||||||||||||||
0x30b | NVICIP11 | ||||||||||||||||||||||||||||||||
0x30c | NVICIP12 | ||||||||||||||||||||||||||||||||
0x30d | NVICIP13 | ||||||||||||||||||||||||||||||||
0x30e | NVICIP14 | ||||||||||||||||||||||||||||||||
0x30f | NVICIP15 | ||||||||||||||||||||||||||||||||
0x310 | NVICIP16 | ||||||||||||||||||||||||||||||||
0x311 | NVICIP17 | ||||||||||||||||||||||||||||||||
0x312 | NVICIP18 | ||||||||||||||||||||||||||||||||
0x313 | NVICIP19 | ||||||||||||||||||||||||||||||||
0x314 | NVICIP20 | ||||||||||||||||||||||||||||||||
0x315 | NVICIP21 | ||||||||||||||||||||||||||||||||
0x316 | NVICIP22 | ||||||||||||||||||||||||||||||||
0x317 | NVICIP23 | ||||||||||||||||||||||||||||||||
0x318 | NVICIP24 | ||||||||||||||||||||||||||||||||
0x319 | NVICIP25 | ||||||||||||||||||||||||||||||||
0x31a | NVICIP26 | ||||||||||||||||||||||||||||||||
0x31b | NVICIP27 | ||||||||||||||||||||||||||||||||
0x31c | NVICIP28 | ||||||||||||||||||||||||||||||||
0x31d | NVICIP29 | ||||||||||||||||||||||||||||||||
0x31e | NVICIP30 | ||||||||||||||||||||||||||||||||
0x31f | NVICIP31 | ||||||||||||||||||||||||||||||||
0x320 | NVICIP32 | ||||||||||||||||||||||||||||||||
0x321 | NVICIP33 | ||||||||||||||||||||||||||||||||
0x322 | NVICIP34 | ||||||||||||||||||||||||||||||||
0x323 | NVICIP35 | ||||||||||||||||||||||||||||||||
0x324 | NVICIP36 | ||||||||||||||||||||||||||||||||
0x325 | NVICIP37 | ||||||||||||||||||||||||||||||||
0x326 | NVICIP38 | ||||||||||||||||||||||||||||||||
0x327 | NVICIP39 | ||||||||||||||||||||||||||||||||
0x328 | NVICIP40 | ||||||||||||||||||||||||||||||||
0x329 | NVICIP41 | ||||||||||||||||||||||||||||||||
0x32a | NVICIP42 | ||||||||||||||||||||||||||||||||
0x32b | NVICIP43 | ||||||||||||||||||||||||||||||||
0x32c | NVICIP44 | ||||||||||||||||||||||||||||||||
0x32d | NVICIP45 | ||||||||||||||||||||||||||||||||
0x32e | NVICIP46 | ||||||||||||||||||||||||||||||||
0x32f | NVICIP47 | ||||||||||||||||||||||||||||||||
0x330 | NVICIP48 | ||||||||||||||||||||||||||||||||
0x331 | NVICIP49 | ||||||||||||||||||||||||||||||||
0x332 | NVICIP50 | ||||||||||||||||||||||||||||||||
0x333 | NVICIP51 | ||||||||||||||||||||||||||||||||
0x334 | NVICIP52 | ||||||||||||||||||||||||||||||||
0x335 | NVICIP53 | ||||||||||||||||||||||||||||||||
0x336 | NVICIP54 | ||||||||||||||||||||||||||||||||
0x337 | NVICIP55 | ||||||||||||||||||||||||||||||||
0x338 | NVICIP56 | ||||||||||||||||||||||||||||||||
0x339 | NVICIP57 | ||||||||||||||||||||||||||||||||
0x33a | NVICIP58 | ||||||||||||||||||||||||||||||||
0x33b | NVICIP59 | ||||||||||||||||||||||||||||||||
0x33c | NVICIP60 | ||||||||||||||||||||||||||||||||
0x33d | NVICIP61 | ||||||||||||||||||||||||||||||||
0x33e | NVICIP62 | ||||||||||||||||||||||||||||||||
0x33f | NVICIP63 | ||||||||||||||||||||||||||||||||
0x340 | NVICIP64 | ||||||||||||||||||||||||||||||||
0x341 | NVICIP65 | ||||||||||||||||||||||||||||||||
0x342 | NVICIP66 | ||||||||||||||||||||||||||||||||
0x343 | NVICIP67 | ||||||||||||||||||||||||||||||||
0x344 | NVICIP68 | ||||||||||||||||||||||||||||||||
0x345 | NVICIP69 | ||||||||||||||||||||||||||||||||
0x346 | NVICIP70 | ||||||||||||||||||||||||||||||||
0x347 | NVICIP71 | ||||||||||||||||||||||||||||||||
0x348 | NVICIP72 | ||||||||||||||||||||||||||||||||
0x349 | NVICIP73 | ||||||||||||||||||||||||||||||||
0x34a | NVICIP74 | ||||||||||||||||||||||||||||||||
0x34b | NVICIP75 | ||||||||||||||||||||||||||||||||
0x34c | NVICIP76 | ||||||||||||||||||||||||||||||||
0x34d | NVICIP77 | ||||||||||||||||||||||||||||||||
0x34e | NVICIP78 | ||||||||||||||||||||||||||||||||
0x34f | NVICIP79 | ||||||||||||||||||||||||||||||||
0x350 | NVICIP80 | ||||||||||||||||||||||||||||||||
0x351 | NVICIP81 | ||||||||||||||||||||||||||||||||
0x352 | NVICIP82 | ||||||||||||||||||||||||||||||||
0x353 | NVICIP83 | ||||||||||||||||||||||||||||||||
0x354 | NVICIP84 | ||||||||||||||||||||||||||||||||
0x355 | NVICIP85 | ||||||||||||||||||||||||||||||||
0x356 | NVICIP86 | ||||||||||||||||||||||||||||||||
0x357 | NVICIP87 | ||||||||||||||||||||||||||||||||
0x358 | NVICIP88 | ||||||||||||||||||||||||||||||||
0x359 | NVICIP89 | ||||||||||||||||||||||||||||||||
0x35a | NVICIP90 | ||||||||||||||||||||||||||||||||
0x35b | NVICIP91 | ||||||||||||||||||||||||||||||||
0x35c | NVICIP92 | ||||||||||||||||||||||||||||||||
0x35d | NVICIP93 | ||||||||||||||||||||||||||||||||
0x35e | NVICIP94 | ||||||||||||||||||||||||||||||||
0x35f | NVICIP95 | ||||||||||||||||||||||||||||||||
0x360 | NVICIP96 | ||||||||||||||||||||||||||||||||
0x361 | NVICIP97 | ||||||||||||||||||||||||||||||||
0x362 | NVICIP98 | ||||||||||||||||||||||||||||||||
0x363 | NVICIP99 | ||||||||||||||||||||||||||||||||
0x364 | NVICIP100 | ||||||||||||||||||||||||||||||||
0x365 | NVICIP101 | ||||||||||||||||||||||||||||||||
0x366 | NVICIP102 | ||||||||||||||||||||||||||||||||
0x367 | NVICIP103 | ||||||||||||||||||||||||||||||||
0x368 | NVICIP104 | ||||||||||||||||||||||||||||||||
0x369 | NVICIP105 | ||||||||||||||||||||||||||||||||
0xe00 | NVICSTIR |
Interrupt Set Enable Register n
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Set Enable Register n
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Set Enable Register n
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Set Enable Register n
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Clear Enable Register n
Offset: 0x80, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Clear Enable Register n
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Clear Enable Register n
Offset: 0x88, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Clear Enable Register n
Offset: 0x8c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Set Pending Register n
Offset: 0x100, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Set Pending Register n
Offset: 0x104, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Set Pending Register n
Offset: 0x108, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Set Pending Register n
Offset: 0x10c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Clear Pending Register n
Offset: 0x180, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Clear Pending Register n
Offset: 0x184, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Clear Pending Register n
Offset: 0x188, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Clear Pending Register n
Offset: 0x18c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Active bit Register n
Offset: 0x200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
rw |
Interrupt Active bit Register n
Offset: 0x204, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
rw |
Interrupt Active bit Register n
Offset: 0x208, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
rw |
Interrupt Active bit Register n
Offset: 0x20c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
rw |
Interrupt Priority Register n
Offset: 0x300, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI0
rw |
Interrupt Priority Register n
Offset: 0x301, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI1
rw |
Interrupt Priority Register n
Offset: 0x302, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI2
rw |
Interrupt Priority Register n
Offset: 0x303, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI3
rw |
Interrupt Priority Register n
Offset: 0x304, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI4
rw |
Interrupt Priority Register n
Offset: 0x305, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI5
rw |
Interrupt Priority Register n
Offset: 0x306, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI6
rw |
Interrupt Priority Register n
Offset: 0x307, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7
rw |
Interrupt Priority Register n
Offset: 0x308, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI8
rw |
Interrupt Priority Register n
Offset: 0x309, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI9
rw |
Interrupt Priority Register n
Offset: 0x30a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI10
rw |
Interrupt Priority Register n
Offset: 0x30b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI11
rw |
Interrupt Priority Register n
Offset: 0x30c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI12
rw |
Interrupt Priority Register n
Offset: 0x30d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI13
rw |
Interrupt Priority Register n
Offset: 0x30e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI14
rw |
Interrupt Priority Register n
Offset: 0x30f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI15
rw |
Interrupt Priority Register n
Offset: 0x310, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI16
rw |
Interrupt Priority Register n
Offset: 0x311, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI17
rw |
Interrupt Priority Register n
Offset: 0x312, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI18
rw |
Interrupt Priority Register n
Offset: 0x313, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI19
rw |
Interrupt Priority Register n
Offset: 0x314, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI20
rw |
Interrupt Priority Register n
Offset: 0x315, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI21
rw |
Interrupt Priority Register n
Offset: 0x316, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI22
rw |
Interrupt Priority Register n
Offset: 0x317, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI23
rw |
Interrupt Priority Register n
Offset: 0x318, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI24
rw |
Interrupt Priority Register n
Offset: 0x319, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI25
rw |
Interrupt Priority Register n
Offset: 0x31a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI26
rw |
Interrupt Priority Register n
Offset: 0x31b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI27
rw |
Interrupt Priority Register n
Offset: 0x31c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI28
rw |
Interrupt Priority Register n
Offset: 0x31d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI29
rw |
Interrupt Priority Register n
Offset: 0x31e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI30
rw |
Interrupt Priority Register n
Offset: 0x31f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI31
rw |
Interrupt Priority Register n
Offset: 0x320, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI32
rw |
Interrupt Priority Register n
Offset: 0x321, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI33
rw |
Interrupt Priority Register n
Offset: 0x322, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI34
rw |
Interrupt Priority Register n
Offset: 0x323, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI35
rw |
Interrupt Priority Register n
Offset: 0x324, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI36
rw |
Interrupt Priority Register n
Offset: 0x325, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI37
rw |
Interrupt Priority Register n
Offset: 0x326, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI38
rw |
Interrupt Priority Register n
Offset: 0x327, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI39
rw |
Interrupt Priority Register n
Offset: 0x328, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI40
rw |
Interrupt Priority Register n
Offset: 0x329, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI41
rw |
Interrupt Priority Register n
Offset: 0x32a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI42
rw |
Interrupt Priority Register n
Offset: 0x32b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI43
rw |
Interrupt Priority Register n
Offset: 0x32c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI44
rw |
Interrupt Priority Register n
Offset: 0x32d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI45
rw |
Interrupt Priority Register n
Offset: 0x32e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI46
rw |
Interrupt Priority Register n
Offset: 0x32f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI47
rw |
Interrupt Priority Register n
Offset: 0x330, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI48
rw |
Interrupt Priority Register n
Offset: 0x331, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI49
rw |
Interrupt Priority Register n
Offset: 0x332, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI50
rw |
Interrupt Priority Register n
Offset: 0x333, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI51
rw |
Interrupt Priority Register n
Offset: 0x334, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI52
rw |
Interrupt Priority Register n
Offset: 0x335, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI53
rw |
Interrupt Priority Register n
Offset: 0x336, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI54
rw |
Interrupt Priority Register n
Offset: 0x337, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI55
rw |
Interrupt Priority Register n
Offset: 0x338, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI56
rw |
Interrupt Priority Register n
Offset: 0x339, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI57
rw |
Interrupt Priority Register n
Offset: 0x33a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI58
rw |
Interrupt Priority Register n
Offset: 0x33b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI59
rw |
Interrupt Priority Register n
Offset: 0x33c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI60
rw |
Interrupt Priority Register n
Offset: 0x33d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI61
rw |
Interrupt Priority Register n
Offset: 0x33e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI62
rw |
Interrupt Priority Register n
Offset: 0x33f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI63
rw |
Interrupt Priority Register n
Offset: 0x340, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI64
rw |
Interrupt Priority Register n
Offset: 0x341, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI65
rw |
Interrupt Priority Register n
Offset: 0x342, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI66
rw |
Interrupt Priority Register n
Offset: 0x343, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI67
rw |
Interrupt Priority Register n
Offset: 0x344, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI68
rw |
Interrupt Priority Register n
Offset: 0x345, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI69
rw |
Interrupt Priority Register n
Offset: 0x346, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI70
rw |
Interrupt Priority Register n
Offset: 0x347, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI71
rw |
Interrupt Priority Register n
Offset: 0x348, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI72
rw |
Interrupt Priority Register n
Offset: 0x349, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI73
rw |
Interrupt Priority Register n
Offset: 0x34a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI74
rw |
Interrupt Priority Register n
Offset: 0x34b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI75
rw |
Interrupt Priority Register n
Offset: 0x34c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI76
rw |
Interrupt Priority Register n
Offset: 0x34d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI77
rw |
Interrupt Priority Register n
Offset: 0x34e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI78
rw |
Interrupt Priority Register n
Offset: 0x34f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI79
rw |
Interrupt Priority Register n
Offset: 0x350, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI80
rw |
Interrupt Priority Register n
Offset: 0x351, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI81
rw |
Interrupt Priority Register n
Offset: 0x352, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI82
rw |
Interrupt Priority Register n
Offset: 0x353, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI83
rw |
Interrupt Priority Register n
Offset: 0x354, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI84
rw |
Interrupt Priority Register n
Offset: 0x355, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI85
rw |
Interrupt Priority Register n
Offset: 0x356, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI86
rw |
Interrupt Priority Register n
Offset: 0x357, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI87
rw |
Interrupt Priority Register n
Offset: 0x358, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI88
rw |
Interrupt Priority Register n
Offset: 0x359, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI89
rw |
Interrupt Priority Register n
Offset: 0x35a, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI90
rw |
Interrupt Priority Register n
Offset: 0x35b, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI91
rw |
Interrupt Priority Register n
Offset: 0x35c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI92
rw |
Interrupt Priority Register n
Offset: 0x35d, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI93
rw |
Interrupt Priority Register n
Offset: 0x35e, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI94
rw |
Interrupt Priority Register n
Offset: 0x35f, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI95
rw |
Interrupt Priority Register n
Offset: 0x360, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI96
rw |
Interrupt Priority Register n
Offset: 0x361, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI97
rw |
Interrupt Priority Register n
Offset: 0x362, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI98
rw |
Interrupt Priority Register n
Offset: 0x363, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI99
rw |
Interrupt Priority Register n
Offset: 0x364, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI100
rw |
Interrupt Priority Register n
Offset: 0x365, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI101
rw |
Interrupt Priority Register n
Offset: 0x366, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI102
rw |
Interrupt Priority Register n
Offset: 0x367, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI103
rw |
Interrupt Priority Register n
Offset: 0x368, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI104
rw |
Interrupt Priority Register n
Offset: 0x369, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI105
rw |
Software Trigger Interrupt Register
Offset: 0xe00, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTID
rw |
0x40015000: This is the description of component otpc It is an eFUSE OTP (One Time Programmable memory) controller with APB bus interface. More details will follow.
16/16 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x10 | AESKEY[[0]] | ||||||||||||||||||||||||||||||||
0x14 | AESKEY[[1]] | ||||||||||||||||||||||||||||||||
0x18 | AESKEY[[2]] | ||||||||||||||||||||||||||||||||
0x1c | AESKEY[[3]] | ||||||||||||||||||||||||||||||||
0x20 | AESKEY[[4]] | ||||||||||||||||||||||||||||||||
0x24 | AESKEY[[5]] | ||||||||||||||||||||||||||||||||
0x28 | AESKEY[[6]] | ||||||||||||||||||||||||||||||||
0x2c | AESKEY[[7]] | ||||||||||||||||||||||||||||||||
0x30 | ECRP | ||||||||||||||||||||||||||||||||
0x38 | USER0 | ||||||||||||||||||||||||||||||||
0x3c | USER1 |
Register for reading the AES key.
Offset: 0x10, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x14, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x18, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x1c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x20, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x24, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x28, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
Register for reading the AES key.
Offset: 0x2c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
r |
ECRP options.
Offset: 0x30, reset: 0, access: read-only
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JTAG_DISABLE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRP_ALLOW_ZERO
r |
CRP_ISP_DISABLE_IAP
r |
CRP_ISP_DISABLE_PIN
r |
IAP_PROTECTION_ENABLE
r |
CRP_MASS_ERASE_DISABLE
r |
User application specific options.
Offset: 0x38, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USER0
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER0
r |
User application specific options.
Offset: 0x3c, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USER1
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER1
r |
0x40004000: LPC5411x Pin interrupt and pattern match (PINT)
25/36 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISEL | ||||||||||||||||||||||||||||||||
0x4 | IENR | ||||||||||||||||||||||||||||||||
0x8 | SIENR | ||||||||||||||||||||||||||||||||
0xc | CIENR | ||||||||||||||||||||||||||||||||
0x10 | IENF | ||||||||||||||||||||||||||||||||
0x14 | SIENF | ||||||||||||||||||||||||||||||||
0x18 | CIENF | ||||||||||||||||||||||||||||||||
0x1c | RISE | ||||||||||||||||||||||||||||||||
0x20 | FALL | ||||||||||||||||||||||||||||||||
0x24 | IST | ||||||||||||||||||||||||||||||||
0x28 | PMCTRL | ||||||||||||||||||||||||||||||||
0x2c | PMSRC | ||||||||||||||||||||||||||||||||
0x30 | PMCFG |
Pin Interrupt Mode register
Offset: 0x0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PMODE
rw |
Pin interrupt level or rising edge interrupt enable register
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENRL
rw |
Pin interrupt level or rising edge interrupt set register
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENRL
w |
Pin interrupt level (rising edge interrupt) clear register
Offset: 0xc, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CENRL
w |
Pin interrupt active level or falling edge interrupt enable register
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENAF
rw |
Bits 0-7: Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH..
Pin interrupt active level or falling edge interrupt set register
Offset: 0x14, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENAF
w |
Pin interrupt active level or falling edge interrupt clear register
Offset: 0x18, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CENAF
w |
Pin interrupt rising edge register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDET
rw |
Bits 0-7: Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin..
Pin interrupt falling edge register
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDET
rw |
Bits 0-7: Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin..
Pin interrupt status register
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTAT
rw |
Bits 0-7: Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)..
Pattern match interrupt control register
Offset: 0x28, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PMAT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA_RXEV
rw |
SEL_PMATCH
rw |
Bit 0: Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function..
Allowed values:
0: PIN_INTERRUPT: Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
0x1: PATTERN_MATCH: Pattern match. Interrupts are driven in response to pattern matches.
Pattern match interrupt bit-slice source register
Offset: 0x2c, reset: 0, access: read-write
8/8 fields covered.
Bits 8-10: Selects the input source for bit slice 0.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
Bits 11-13: Selects the input source for bit slice 1.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
Bits 14-16: Selects the input source for bit slice 2.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
Bits 17-19: Selects the input source for bit slice 3.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
Bits 20-22: Selects the input source for bit slice 4.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
Bits 23-25: Selects the input source for bit slice 5.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
Bits 26-28: Selects the input source for bit slice 6.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
Bits 29-31: Selects the input source for bit slice 7.
Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
Pattern match interrupt bit slice configuration register
Offset: 0x30, reset: 0, access: read-write
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CFG7
rw |
CFG6
rw |
CFG5
rw |
CFG4
rw |
CFG3
rw |
CFG2
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CFG2
rw |
CFG1
rw |
CFG0
rw |
PROD_ENDPTS6
rw |
PROD_ENDPTS5
rw |
PROD_ENDPTS4
rw |
PROD_ENDPTS3
rw |
PROD_ENDPTS2
rw |
PROD_ENDPTS1
rw |
PROD_ENDPTS0
rw |
Bits 8-10: Specifies the match contribution condition for bit slice 0..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 11-13: Specifies the match contribution condition for bit slice 1..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 14-16: Specifies the match contribution condition for bit slice 2..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 17-19: Specifies the match contribution condition for bit slice 3..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 20-22: Specifies the match contribution condition for bit slice 4..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 23-25: Specifies the match contribution condition for bit slice 5..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 26-28: Specifies the match contribution condition for bit slice 6..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
Bits 29-31: Specifies the match contribution condition for bit slice 7..
Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x4002d000: LPC5460x Repetitive Interrupt Timer(RIT)
0/10 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | COMPVAL | ||||||||||||||||||||||||||||||||
0x4 | MASK | ||||||||||||||||||||||||||||||||
0x8 | CTRL | ||||||||||||||||||||||||||||||||
0xc | COUNTER | ||||||||||||||||||||||||||||||||
0x10 | COMPVAL_H | ||||||||||||||||||||||||||||||||
0x14 | MASK_H | ||||||||||||||||||||||||||||||||
0x1c | COUNTER_H |
Compare value LSB register
Offset: 0x0, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RICOMP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RICOMP
rw |
Mask LSB register
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RIMASK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RIMASK
rw |
Control register
Offset: 0x8, reset: 0xC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RITEN
rw |
RITENBR
rw |
RITENCLR
rw |
RITINT
rw |
Counter LSB register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RICOUNTER
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RICOUNTER
rw |
Compare value MSB register
Offset: 0x10, reset: 0xFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RICOMP
rw |
Mask MSB register
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RIMASK
rw |
Counter MSB register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RICOUNTER
rw |
0x4002c000: LPC5411x Real-Time Clock (RTC)
8/19 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | MATCH | ||||||||||||||||||||||||||||||||
0x8 | COUNT | ||||||||||||||||||||||||||||||||
0xc | WAKE | ||||||||||||||||||||||||||||||||
0x40 | GPREG[[0]] | ||||||||||||||||||||||||||||||||
0x44 | GPREG[[1]] | ||||||||||||||||||||||||||||||||
0x48 | GPREG[[2]] | ||||||||||||||||||||||||||||||||
0x4c | GPREG[[3]] | ||||||||||||||||||||||||||||||||
0x50 | GPREG[[4]] | ||||||||||||||||||||||||||||||||
0x54 | GPREG[[5]] | ||||||||||||||||||||||||||||||||
0x58 | GPREG[[6]] | ||||||||||||||||||||||||||||||||
0x5c | GPREG[[7]] |
RTC control register
Offset: 0x0, reset: 0x1, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTC_OSC_PD
rw |
RTC_EN
rw |
RTC1KHZ_EN
rw |
WAKEDPD_EN
rw |
ALARMDPD_EN
rw |
WAKE1KHZ
rw |
ALARM1HZ
rw |
SWRESET
rw |
Bit 0: Software reset control.
Allowed values:
0: NOT_IN_RESET: Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
0x1: IN_RESET: In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared.
Bit 2: RTC 1 Hz timer alarm flag status..
Allowed values:
0: NO_MATCH: No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
0x1: MATCH: Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
Bit 3: RTC 1 kHz timer wake-up flag status..
Allowed values:
0: RUN: Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
0x1: TIMEOUT: Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
Bit 6: RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)..
Allowed values:
0: DISABLE: Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
0x1: ENABLE: Enable. The 1 kHz RTC timer is enabled.
Bit 7: RTC enable..
Allowed values:
0: DISABLE: Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.
0x1: ENABLE: Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.
RTC match register
Offset: 0x4, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATVAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATVAL
rw |
RTC counter register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VAL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL
rw |
Bits 0-31: A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set..
High-resolution/wake-up timer control register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL
rw |
General Purpose register
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x4c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x58, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
General Purpose register
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPDATA
rw |
0x40085000: SCTimer/PWM (SCT)
129/321 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CONFIG | ||||||||||||||||||||||||||||||||
0x4 | CTRL | ||||||||||||||||||||||||||||||||
0x8 | LIMIT | ||||||||||||||||||||||||||||||||
0xc | HALT | ||||||||||||||||||||||||||||||||
0x10 | STOP | ||||||||||||||||||||||||||||||||
0x14 | START | ||||||||||||||||||||||||||||||||
0x40 | COUNT | ||||||||||||||||||||||||||||||||
0x44 | STATE | ||||||||||||||||||||||||||||||||
0x48 | INPUT | ||||||||||||||||||||||||||||||||
0x4c | REGMODE | ||||||||||||||||||||||||||||||||
0x50 | OUTPUT | ||||||||||||||||||||||||||||||||
0x54 | OUTPUTDIRCTRL | ||||||||||||||||||||||||||||||||
0x58 | RES | ||||||||||||||||||||||||||||||||
0x5c | DMAREQ0 | ||||||||||||||||||||||||||||||||
0x60 | DMAREQ1 | ||||||||||||||||||||||||||||||||
0xf0 | EVEN | ||||||||||||||||||||||||||||||||
0xf4 | EVFLAG | ||||||||||||||||||||||||||||||||
0xf8 | CONEN | ||||||||||||||||||||||||||||||||
0xfc | CONFLAG | ||||||||||||||||||||||||||||||||
0x100 | CAP0 | ||||||||||||||||||||||||||||||||
0x100 | MATCH0 | ||||||||||||||||||||||||||||||||
0x104 | CAP1 | ||||||||||||||||||||||||||||||||
0x104 | MATCH1 | ||||||||||||||||||||||||||||||||
0x108 | CAP2 | ||||||||||||||||||||||||||||||||
0x108 | MATCH2 | ||||||||||||||||||||||||||||||||
0x10c | CAP3 | ||||||||||||||||||||||||||||||||
0x10c | MATCH3 | ||||||||||||||||||||||||||||||||
0x110 | CAP4 | ||||||||||||||||||||||||||||||||
0x110 | MATCH4 | ||||||||||||||||||||||||||||||||
0x114 | CAP5 | ||||||||||||||||||||||||||||||||
0x114 | MATCH5 | ||||||||||||||||||||||||||||||||
0x118 | CAP6 | ||||||||||||||||||||||||||||||||
0x118 | MATCH6 | ||||||||||||||||||||||||||||||||
0x11c | CAP7 | ||||||||||||||||||||||||||||||||
0x11c | MATCH7 | ||||||||||||||||||||||||||||||||
0x120 | CAP8 | ||||||||||||||||||||||||||||||||
0x120 | MATCH8 | ||||||||||||||||||||||||||||||||
0x124 | CAP9 | ||||||||||||||||||||||||||||||||
0x124 | MATCH9 | ||||||||||||||||||||||||||||||||
0x200 | CAPCTRL0 | ||||||||||||||||||||||||||||||||
0x200 | MATCHREL0 | ||||||||||||||||||||||||||||||||
0x204 | CAPCTRL1 | ||||||||||||||||||||||||||||||||
0x204 | MATCHREL1 | ||||||||||||||||||||||||||||||||
0x208 | CAPCTRL2 | ||||||||||||||||||||||||||||||||
0x208 | MATCHREL2 | ||||||||||||||||||||||||||||||||
0x20c | CAPCTRL3 | ||||||||||||||||||||||||||||||||
0x20c | MATCHREL3 | ||||||||||||||||||||||||||||||||
0x210 | CAPCTRL4 | ||||||||||||||||||||||||||||||||
0x210 | MATCHREL4 | ||||||||||||||||||||||||||||||||
0x214 | CAPCTRL5 | ||||||||||||||||||||||||||||||||
0x214 | MATCHREL5 | ||||||||||||||||||||||||||||||||
0x218 | CAPCTRL6 | ||||||||||||||||||||||||||||||||
0x218 | MATCHREL6 | ||||||||||||||||||||||||||||||||
0x21c | CAPCTRL7 | ||||||||||||||||||||||||||||||||
0x21c | MATCHREL7 | ||||||||||||||||||||||||||||||||
0x220 | CAPCTRL8 | ||||||||||||||||||||||||||||||||
0x220 | MATCHREL8 | ||||||||||||||||||||||||||||||||
0x224 | CAPCTRL9 | ||||||||||||||||||||||||||||||||
0x224 | MATCHREL9 | ||||||||||||||||||||||||||||||||
0x300 | EV_STATE [0] | ||||||||||||||||||||||||||||||||
0x304 | EV_CTRL [0] | ||||||||||||||||||||||||||||||||
0x308 | EV_STATE [1] | ||||||||||||||||||||||||||||||||
0x30c | EV_CTRL [1] | ||||||||||||||||||||||||||||||||
0x310 | EV_STATE [2] | ||||||||||||||||||||||||||||||||
0x314 | EV_CTRL [2] | ||||||||||||||||||||||||||||||||
0x318 | EV_STATE [3] | ||||||||||||||||||||||||||||||||
0x31c | EV_CTRL [3] | ||||||||||||||||||||||||||||||||
0x320 | EV_STATE [4] | ||||||||||||||||||||||||||||||||
0x324 | EV_CTRL [4] | ||||||||||||||||||||||||||||||||
0x328 | EV_STATE [5] | ||||||||||||||||||||||||||||||||
0x32c | EV_CTRL [5] | ||||||||||||||||||||||||||||||||
0x330 | EV_STATE [6] | ||||||||||||||||||||||||||||||||
0x334 | EV_CTRL [6] | ||||||||||||||||||||||||||||||||
0x338 | EV_STATE [7] | ||||||||||||||||||||||||||||||||
0x33c | EV_CTRL [7] | ||||||||||||||||||||||||||||||||
0x340 | EV_STATE [8] | ||||||||||||||||||||||||||||||||
0x344 | EV_CTRL [8] | ||||||||||||||||||||||||||||||||
0x348 | EV_STATE [9] | ||||||||||||||||||||||||||||||||
0x34c | EV_CTRL [9] | ||||||||||||||||||||||||||||||||
0x500 | OUT_SET [0] | ||||||||||||||||||||||||||||||||
0x504 | OUT_CLR [0] | ||||||||||||||||||||||||||||||||
0x508 | OUT_SET [1] | ||||||||||||||||||||||||||||||||
0x50c | OUT_CLR [1] | ||||||||||||||||||||||||||||||||
0x510 | OUT_SET [2] | ||||||||||||||||||||||||||||||||
0x514 | OUT_CLR [2] | ||||||||||||||||||||||||||||||||
0x518 | OUT_SET [3] | ||||||||||||||||||||||||||||||||
0x51c | OUT_CLR [3] | ||||||||||||||||||||||||||||||||
0x520 | OUT_SET [4] | ||||||||||||||||||||||||||||||||
0x524 | OUT_CLR [4] | ||||||||||||||||||||||||||||||||
0x528 | OUT_SET [5] | ||||||||||||||||||||||||||||||||
0x52c | OUT_CLR [5] | ||||||||||||||||||||||||||||||||
0x530 | OUT_SET [6] | ||||||||||||||||||||||||||||||||
0x534 | OUT_CLR [6] | ||||||||||||||||||||||||||||||||
0x538 | OUT_SET [7] | ||||||||||||||||||||||||||||||||
0x53c | OUT_CLR [7] | ||||||||||||||||||||||||||||||||
0x540 | OUT_SET [8] | ||||||||||||||||||||||||||||||||
0x544 | OUT_CLR [8] | ||||||||||||||||||||||||||||||||
0x548 | OUT_SET [9] | ||||||||||||||||||||||||||||||||
0x54c | OUT_CLR [9] |
SCT configuration register
Offset: 0x0, reset: 0x1E00, access: read-write
3/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AUTOLIMIT_H
rw |
AUTOLIMIT_L
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INSYNC
rw |
NORELOAD_H
rw |
NORELOAD_L
rw |
CKSEL
rw |
CLKMODE
rw |
UNIFY
rw |
Bits 1-2: SCT clock mode.
Allowed values:
0: SYSTEM_CLOCK_MODE: System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
0x1: SAMPLED_SYSTEM_CLOCK_MODE: Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
0x2: SCT_INPUT_CLOCK_MODE: SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
0x3: ASYNCHRONOUS_MODE: Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.
Bits 3-6: SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register..
Allowed values:
0: INPUT_0_RISING_EDGES: Rising edges on input 0.
0x1: INPUT_0_FALLING_EDGE: Falling edges on input 0.
0x2: INPUT_1_RISING_EDGES: Rising edges on input 1.
0x3: INPUT_1_FALLING_EDGE: Falling edges on input 1.
0x4: INPUT_2_RISING_EDGES: Rising edges on input 2.
0x5: INPUT_2_FALLING_EDGE: Falling edges on input 2.
0x6: INPUT_3_RISING_EDGES: Rising edges on input 3.
0x7: INPUT_3_FALLING_EDGE: Falling edges on input 3.
0x8: INPUT_4_RISING_EDGES: Rising edges on input 4.
0x9: INPUT_4_FALLING_EDGE: Falling edges on input 4.
0xA: INPUT_5_RISING_EDGES: Rising edges on input 5.
0xB: INPUT_5_FALLING_EDGE: Falling edges on input 5.
0xC: INPUT_6_RISING_EDGES: Rising edges on input 6.
0xD: INPUT_6_FALLING_EDGE: Falling edges on input 6.
0xE: INPUT_7_RISING_EDGES: Rising edges on input 7.
0xF: INPUT_7_FALLING_EDGE: Falling edges on input 7.
Bit 7: A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set..
Bit 8: A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set..
Bits 9-12: Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field..
Bit 17: A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set..
Bit 18: A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set..
SCT control register
Offset: 0x4, reset: 0x40004, access: read-write
2/12 fields covered.
Bit 2: When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset..
Bit 18: When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset..
SCT limit event select register
Offset: 0x8, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LIMMSK_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LIMMSK_L
rw |
SCT halt event select register
Offset: 0xc, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HALTMSK_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HALTMSK_L
rw |
SCT stop event select register
Offset: 0x10, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STOPMSK_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STOPMSK_L
rw |
SCT start event select register
Offset: 0x14, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STARTMSK_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTMSK_L
rw |
SCT counter register
Offset: 0x40, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTR_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTR_L
rw |
SCT state register
Offset: 0x44, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STATE_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATE_L
rw |
SCT input register
Offset: 0x48, reset: 0, access: read-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIN15
r |
SIN14
r |
SIN13
r |
SIN12
r |
SIN11
r |
SIN10
r |
SIN9
r |
SIN8
r |
SIN7
r |
SIN6
r |
SIN5
r |
SIN4
r |
SIN3
r |
SIN2
r |
SIN1
r |
SIN0
r |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AIN15
r |
AIN14
r |
AIN13
r |
AIN12
r |
AIN11
r |
AIN10
r |
AIN9
r |
AIN8
r |
AIN7
r |
AIN6
r |
AIN5
r |
AIN4
r |
AIN3
r |
AIN2
r |
AIN1
r |
AIN0
r |
SCT match/capture mode register
Offset: 0x4c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REGMOD_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REGMOD_L
rw |
SCT output register
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT
rw |
SCT output counter direction control register
Offset: 0x54, reset: 0, access: read-write
16/16 fields covered.
Bits 0-1: Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 2-3: Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 4-5: Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 6-7: Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 8-9: Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 10-11: Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 12-13: Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 14-15: Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 16-17: Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 18-19: Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 20-21: Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 22-23: Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 24-25: Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 26-27: Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 28-29: Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Bits 30-31: Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value..
Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SCT DMA request 0 register
Offset: 0x5c, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DRQ0
rw |
DRL0
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEV_0
rw |
SCT DMA request 1 register
Offset: 0x60, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DRQ1
rw |
DRL1
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEV_1
rw |
SCT event interrupt enable register
Offset: 0xf0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEN
rw |
SCT event flag register
Offset: 0xf4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLAG
rw |
SCT conflict interrupt enable register
Offset: 0xf8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCEN
rw |
SCT conflict flag register
Offset: 0xfc, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BUSERRH
rw |
BUSERRL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCFLAG
rw |
SCT capture register of capture channel
Offset: 0x100, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x100, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x104, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x104, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x108, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x108, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x10c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x10c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x110, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x110, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x114, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x114, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x118, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x118, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x11c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x11c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x120, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x120, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture register of capture channel
Offset: 0x124, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPn_L
rw |
SCT match value register of match channels
Offset: 0x124, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MATCHn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MATCHn_L
rw |
SCT capture control register
Offset: 0x200, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x200, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x204, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x204, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x208, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x208, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x20c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x20c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x210, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x210, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x214, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x214, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x218, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x218, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x21c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x21c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x220, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x220, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT capture control register
Offset: 0x224, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CAPCONn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCONn_L
rw |
SCT match reload value register
Offset: 0x224, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOADn_H
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOADn_L
rw |
SCT event state register 0
Offset: 0x300, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x304, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x308, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x30c, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x310, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x314, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x318, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x31c, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x320, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x324, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x328, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x32c, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x330, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x334, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x338, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x33c, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x340, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x344, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT event state register 0
Offset: 0x348, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATEMSKn
rw |
SCT event control register 0
Offset: 0x34c, reset: 0, access: read-write
6/10 fields covered.
Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..
Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH
Bits 12-13: Selects how the specified match and I/O condition are used and combined..
Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.
Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..
Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..
Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.
SCT output 0 set register
Offset: 0x500, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x504, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x508, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x50c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x510, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x514, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x518, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x51c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x520, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x524, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x528, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x52c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x530, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x534, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x538, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x53c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x540, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x544, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 set register
Offset: 0x548, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET
rw |
Bits 0-15: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
SCT output 0 clear register
Offset: 0x54c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR
rw |
Bits 0-15: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..
0x4009b000: SDMMC
0/215 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | PWREN | ||||||||||||||||||||||||||||||||
0x8 | CLKDIV | ||||||||||||||||||||||||||||||||
0x10 | CLKENA | ||||||||||||||||||||||||||||||||
0x14 | TMOUT | ||||||||||||||||||||||||||||||||
0x18 | CTYPE | ||||||||||||||||||||||||||||||||
0x1c | BLKSIZ | ||||||||||||||||||||||||||||||||
0x20 | BYTCNT | ||||||||||||||||||||||||||||||||
0x24 | INTMASK | ||||||||||||||||||||||||||||||||
0x28 | CMDARG | ||||||||||||||||||||||||||||||||
0x2c | CMD | ||||||||||||||||||||||||||||||||
0x30 | RESP[[0]] | ||||||||||||||||||||||||||||||||
0x34 | RESP[[1]] | ||||||||||||||||||||||||||||||||
0x38 | RESP[[2]] | ||||||||||||||||||||||||||||||||
0x3c | RESP[[3]] | ||||||||||||||||||||||||||||||||
0x40 | MINTSTS | ||||||||||||||||||||||||||||||||
0x44 | RINTSTS | ||||||||||||||||||||||||||||||||
0x48 | STATUS | ||||||||||||||||||||||||||||||||
0x4c | FIFOTH | ||||||||||||||||||||||||||||||||
0x50 | CDETECT | ||||||||||||||||||||||||||||||||
0x54 | WRTPRT | ||||||||||||||||||||||||||||||||
0x5c | TCBCNT | ||||||||||||||||||||||||||||||||
0x60 | TBBCNT | ||||||||||||||||||||||||||||||||
0x64 | DEBNCE | ||||||||||||||||||||||||||||||||
0x78 | RST_N | ||||||||||||||||||||||||||||||||
0x80 | BMOD | ||||||||||||||||||||||||||||||||
0x84 | PLDMND | ||||||||||||||||||||||||||||||||
0x88 | DBADDR | ||||||||||||||||||||||||||||||||
0x8c | IDSTS | ||||||||||||||||||||||||||||||||
0x90 | IDINTEN | ||||||||||||||||||||||||||||||||
0x94 | DSCADDR | ||||||||||||||||||||||||||||||||
0x98 | BUFADDR | ||||||||||||||||||||||||||||||||
0x100 | CARDTHRCTL | ||||||||||||||||||||||||||||||||
0x104 | BACKENDPWR | ||||||||||||||||||||||||||||||||
0x200 | FIFO[[0]] | ||||||||||||||||||||||||||||||||
0x204 | FIFO[[1]] | ||||||||||||||||||||||||||||||||
0x208 | FIFO[[2]] | ||||||||||||||||||||||||||||||||
0x20c | FIFO[[3]] | ||||||||||||||||||||||||||||||||
0x210 | FIFO[[4]] | ||||||||||||||||||||||||||||||||
0x214 | FIFO[[5]] | ||||||||||||||||||||||||||||||||
0x218 | FIFO[[6]] | ||||||||||||||||||||||||||||||||
0x21c | FIFO[[7]] | ||||||||||||||||||||||||||||||||
0x220 | FIFO[[8]] | ||||||||||||||||||||||||||||||||
0x224 | FIFO[[9]] | ||||||||||||||||||||||||||||||||
0x228 | FIFO[[10]] | ||||||||||||||||||||||||||||||||
0x22c | FIFO[[11]] | ||||||||||||||||||||||||||||||||
0x230 | FIFO[[12]] | ||||||||||||||||||||||||||||||||
0x234 | FIFO[[13]] | ||||||||||||||||||||||||||||||||
0x238 | FIFO[[14]] | ||||||||||||||||||||||||||||||||
0x23c | FIFO[[15]] | ||||||||||||||||||||||||||||||||
0x240 | FIFO[[16]] | ||||||||||||||||||||||||||||||||
0x244 | FIFO[[17]] | ||||||||||||||||||||||||||||||||
0x248 | FIFO[[18]] | ||||||||||||||||||||||||||||||||
0x24c | FIFO[[19]] | ||||||||||||||||||||||||||||||||
0x250 | FIFO[[20]] | ||||||||||||||||||||||||||||||||
0x254 | FIFO[[21]] | ||||||||||||||||||||||||||||||||
0x258 | FIFO[[22]] | ||||||||||||||||||||||||||||||||
0x25c | FIFO[[23]] | ||||||||||||||||||||||||||||||||
0x260 | FIFO[[24]] | ||||||||||||||||||||||||||||||||
0x264 | FIFO[[25]] | ||||||||||||||||||||||||||||||||
0x268 | FIFO[[26]] | ||||||||||||||||||||||||||||||||
0x26c | FIFO[[27]] | ||||||||||||||||||||||||||||||||
0x270 | FIFO[[28]] | ||||||||||||||||||||||||||||||||
0x274 | FIFO[[29]] | ||||||||||||||||||||||||||||||||
0x278 | FIFO[[30]] | ||||||||||||||||||||||||||||||||
0x27c | FIFO[[31]] | ||||||||||||||||||||||||||||||||
0x280 | FIFO[[32]] | ||||||||||||||||||||||||||||||||
0x284 | FIFO[[33]] | ||||||||||||||||||||||||||||||||
0x288 | FIFO[[34]] | ||||||||||||||||||||||||||||||||
0x28c | FIFO[[35]] | ||||||||||||||||||||||||||||||||
0x290 | FIFO[[36]] | ||||||||||||||||||||||||||||||||
0x294 | FIFO[[37]] | ||||||||||||||||||||||||||||||||
0x298 | FIFO[[38]] | ||||||||||||||||||||||||||||||||
0x29c | FIFO[[39]] | ||||||||||||||||||||||||||||||||
0x2a0 | FIFO[[40]] | ||||||||||||||||||||||||||||||||
0x2a4 | FIFO[[41]] | ||||||||||||||||||||||||||||||||
0x2a8 | FIFO[[42]] | ||||||||||||||||||||||||||||||||
0x2ac | FIFO[[43]] | ||||||||||||||||||||||||||||||||
0x2b0 | FIFO[[44]] | ||||||||||||||||||||||||||||||||
0x2b4 | FIFO[[45]] | ||||||||||||||||||||||||||||||||
0x2b8 | FIFO[[46]] | ||||||||||||||||||||||||||||||||
0x2bc | FIFO[[47]] | ||||||||||||||||||||||||||||||||
0x2c0 | FIFO[[48]] | ||||||||||||||||||||||||||||||||
0x2c4 | FIFO[[49]] | ||||||||||||||||||||||||||||||||
0x2c8 | FIFO[[50]] | ||||||||||||||||||||||||||||||||
0x2cc | FIFO[[51]] | ||||||||||||||||||||||||||||||||
0x2d0 | FIFO[[52]] | ||||||||||||||||||||||||||||||||
0x2d4 | FIFO[[53]] | ||||||||||||||||||||||||||||||||
0x2d8 | FIFO[[54]] | ||||||||||||||||||||||||||||||||
0x2dc | FIFO[[55]] | ||||||||||||||||||||||||||||||||
0x2e0 | FIFO[[56]] | ||||||||||||||||||||||||||||||||
0x2e4 | FIFO[[57]] | ||||||||||||||||||||||||||||||||
0x2e8 | FIFO[[58]] | ||||||||||||||||||||||||||||||||
0x2ec | FIFO[[59]] | ||||||||||||||||||||||||||||||||
0x2f0 | FIFO[[60]] | ||||||||||||||||||||||||||||||||
0x2f4 | FIFO[[61]] | ||||||||||||||||||||||||||||||||
0x2f8 | FIFO[[62]] | ||||||||||||||||||||||||||||||||
0x2fc | FIFO[[63]] |
Control register
Offset: 0x0, reset: 0, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USE_INTERNAL_DMAC
rw |
CARD_VOLTAGE_A2
rw |
CARD_VOLTAGE_A1
rw |
CARD_VOLTAGE_A0
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CEATA_DEVICE_INTERRUPT_STATUS
rw |
SEND_AUTO_STOP_CCSD
rw |
SEND_CCSD
rw |
ABORT_READ_DATA
rw |
SEND_IRQ_RESPONSE
rw |
READ_WAIT
rw |
INT_ENABLE
rw |
DMA_RESET
rw |
FIFO_RESET
rw |
CONTROLLER_RESET
rw |
Power Enable register
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_ENABLE
rw |
Clock Divider register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_DIVIDER0
rw |
Clock Enable register
Offset: 0x10, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCLK_LOW_POWER
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCLK_ENABLE
rw |
Time-out register
Offset: 0x14, reset: 0xFFFFFF40, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA_TIMEOUT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_TIMEOUT
rw |
RESPONSE_TIMEOUT
rw |
Card Type register
Offset: 0x18, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARD_WIDTH1
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARD_WIDTH0
rw |
Block Size register
Offset: 0x1c, reset: 0x200, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BLOCK_SIZE
rw |
Byte Count register
Offset: 0x20, reset: 0x200, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BYTE_COUNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTE_COUNT
rw |
Command Argument register
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMD_ARG
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMD_ARG
rw |
Command register
Offset: 0x2c, reset: 0, access: read-write
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START_CMD
rw |
USE_HOLD_REG
rw |
VOLT_SWITCH
rw |
BOOT_MODE
rw |
DISABLE_BOOT
rw |
EXPECT_BOOT_ACK
rw |
ENABLE_BOOT
rw |
CCS_EXPECTED
rw |
READ_CEATA_DEVICE
rw |
UPDATE_CLOCK_REGISTERS_ONLY
rw |
||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEND_INITIALIZATION
rw |
STOP_ABORT_CMD
rw |
WAIT_PRVDATA_COMPLETE
rw |
SEND_AUTO_STOP
rw |
TRANSFER_MODE
rw |
READ_WRITE
rw |
DATA_EXPECTED
rw |
CHECK_RESPONSE_CRC
rw |
RESPONSE_LENGTH
rw |
RESPONSE_EXPECT
rw |
CMD_INDEX
rw |
Response register
Offset: 0x30, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESPONSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESPONSE
rw |
Response register
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESPONSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESPONSE
rw |
Response register
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESPONSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESPONSE
rw |
Response register
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESPONSE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESPONSE
rw |
Status register
Offset: 0x48, reset: 0x406, access: read-write
0/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMA_REQ
rw |
DMA_ACK
rw |
FIFO_COUNT
rw |
RESPONSE_INDEX
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESPONSE_INDEX
rw |
DATA_STATE_MC_BUSY
rw |
DATA_BUSY
rw |
DATA_3_STATUS
rw |
CMDFSMSTATES
rw |
FIFO_FULL
rw |
FIFO_EMPTY
rw |
FIFO_TX_WATERMARK
rw |
FIFO_RX_WATERMARK
rw |
Bits 4-7: Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits..
FIFO Threshold Watermark register
Offset: 0x4c, reset: 0x1F0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMA_MTS
rw |
RX_WMARK
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_WMARK
rw |
Card Detect register
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARD_DETECT
rw |
Write Protect register
Offset: 0x54, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRITE_PROTECT
rw |
Transferred CIU Card Byte Count register
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRANS_CARD_BYTE_COUNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANS_CARD_BYTE_COUNT
rw |
Transferred Host to BIU-FIFO Byte Count register
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRANS_FIFO_BYTE_COUNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANS_FIFO_BYTE_COUNT
rw |
Debounce Count register
Offset: 0x64, reset: 0xFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEBOUNCE_COUNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEBOUNCE_COUNT
rw |
Hardware Reset
Offset: 0x78, reset: 0x1, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARD_RESET
rw |
Poll Demand register
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PD
rw |
Descriptor List Base Address register
Offset: 0x88, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SDL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDL
rw |
Current Host Descriptor Address register
Offset: 0x94, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HDA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HDA
rw |
Current Buffer Descriptor Address register
Offset: 0x98, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HBA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HBA
rw |
Card Threshold Control
Offset: 0x100, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARDTHRESHOLD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BSYCLRINTEN
rw |
CARDRDTHREN
rw |
Power control
Offset: 0x104, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BACKENDPWR
rw |
SDIF FIFO
Offset: 0x200, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x204, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x208, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x20c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x210, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x214, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x218, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x21c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x220, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x224, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x228, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x22c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x230, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x234, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x238, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x23c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x240, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x244, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x248, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x24c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x250, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x254, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x258, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x25c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x260, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x264, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x268, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x26c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x270, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x274, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x278, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x27c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x280, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x284, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x288, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x28c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x290, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x294, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x298, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x29c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2a0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2a4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2a8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2ac, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2b0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2b4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2b8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2bc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2c0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2c4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2c8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2cc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2d0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2d4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2d8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2dc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2e0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2e4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2e8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2ec, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2f0, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2f4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2f8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SDIF FIFO
Offset: 0x2fc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
0x40036000: LPC5460x Smart Card Interface
11/36 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DLL | ||||||||||||||||||||||||||||||||
0x0 | RBR | ||||||||||||||||||||||||||||||||
0x0 | THR | ||||||||||||||||||||||||||||||||
0x4 | DLM | ||||||||||||||||||||||||||||||||
0x4 | IER | ||||||||||||||||||||||||||||||||
0x8 | FCR | ||||||||||||||||||||||||||||||||
0x8 | IIR | ||||||||||||||||||||||||||||||||
0xc | LCR | ||||||||||||||||||||||||||||||||
0x14 | LSR | ||||||||||||||||||||||||||||||||
0x1c | SCR | ||||||||||||||||||||||||||||||||
0x2c | OSR | ||||||||||||||||||||||||||||||||
0x48 | SCICTRL |
Divisor Latch LSB
Offset: 0x0, reset: 0x1, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLLSB
rw |
Receiver Buffer Register
Offset: 0x0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBR
r |
Transmit Holding Register
Offset: 0x0, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR
w |
Divisor Latch MSB
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLMSB
rw |
Interrupt Enable Register
Offset: 0x4, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXIE
rw |
THREIE
rw |
RBRIE
rw |
Interrupt ID Register
Offset: 0x8, reset: 0x1, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOENABLE
r |
INTID
r |
INTSTATUS
r |
Scratch Pad Register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAD
rw |
Oversampling register
Offset: 0x2c, reset: 0xF0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDINT
rw |
OSINT
rw |
OSFRAC
rw |
0x40037000: LPC5460x Smart Card Interface
11/36 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DLL | ||||||||||||||||||||||||||||||||
0x0 | RBR | ||||||||||||||||||||||||||||||||
0x0 | THR | ||||||||||||||||||||||||||||||||
0x4 | DLM | ||||||||||||||||||||||||||||||||
0x4 | IER | ||||||||||||||||||||||||||||||||
0x8 | FCR | ||||||||||||||||||||||||||||||||
0x8 | IIR | ||||||||||||||||||||||||||||||||
0xc | LCR | ||||||||||||||||||||||||||||||||
0x14 | LSR | ||||||||||||||||||||||||||||||||
0x1c | SCR | ||||||||||||||||||||||||||||||||
0x2c | OSR | ||||||||||||||||||||||||||||||||
0x48 | SCICTRL |
Divisor Latch LSB
Offset: 0x0, reset: 0x1, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLLSB
rw |
Receiver Buffer Register
Offset: 0x0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBR
r |
Transmit Holding Register
Offset: 0x0, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR
w |
Divisor Latch MSB
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLMSB
rw |
Interrupt Enable Register
Offset: 0x4, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXIE
rw |
THREIE
rw |
RBRIE
rw |
Interrupt ID Register
Offset: 0x8, reset: 0x1, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOENABLE
r |
INTID
r |
INTSTATUS
r |
Scratch Pad Register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAD
rw |
Oversampling register
Offset: 0x2c, reset: 0xF0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDINT
rw |
OSINT
rw |
OSFRAC
rw |
0x40086000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40087000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40088000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40089000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4008a000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40096000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40097000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40098000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40099000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4009a000: LPC5411x Serial Peripheral Interfaces (SPI)
67/90 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x400 | CFG | ||||||||||||||||||||||||||||||||
0x404 | DLY | ||||||||||||||||||||||||||||||||
0x408 | STAT | ||||||||||||||||||||||||||||||||
0x40c | INTENSET | ||||||||||||||||||||||||||||||||
0x410 | INTENCLR | ||||||||||||||||||||||||||||||||
0x424 | DIV | ||||||||||||||||||||||||||||||||
0x428 | INTSTAT | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
SPI Configuration register
Offset: 0x400, reset: 0, access: read-write
10/10 fields covered.
Bit 2: Master mode select..
Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
Bit 4: Clock Phase select..
Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
SPI Delay register
Offset: 0x404, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSFER_DELAY
rw |
FRAME_DELAY
rw |
POST_DELAY
rw |
PRE_DELAY
rw |
Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..
Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
Offset: 0x408, reset: 0x100, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
ENDTRANSFER
rw |
STALLED
r |
SSD
w |
SSA
w |
Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..
Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0x40c, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLEEN
rw |
SSDEN
rw |
SSAEN
rw |
Bit 4: Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: ENABLED: Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
Bit 5: Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted..
Allowed values:
0: DISABLED: Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: ENABLED: Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
Offset: 0x410, reset: 0, access: write-only
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
w |
SSDEN
w |
SSAEN
w |
SPI clock Divider
Offset: 0x424, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIVVAL
rw |
Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..
SPI Interrupt Status
Offset: 0x428, reset: 0, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSTIDLE
r |
SSD
r |
SSA
r |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
7/9 fields covered.
Bit 20: End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register..
Allowed values:
0: NOT_DEASSERTED: SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: DEASSERTED: SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
Bit 21: End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..
Allowed values:
0: NOT_EOF: Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1: EOF: Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.
Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA..
Allowed values:
0: READ: Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: IGNORE: Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
Bits 24-27: Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length..
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
6/6 fields covered.
Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 17: Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 18: Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Bit 19: Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40080000: LPC5411x SPI Flash Interface (SPIFI)
10/31 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | CMD | ||||||||||||||||||||||||||||||||
0x8 | ADDR | ||||||||||||||||||||||||||||||||
0xc | IDATA | ||||||||||||||||||||||||||||||||
0x10 | CLIMIT | ||||||||||||||||||||||||||||||||
0x14 | DATA | ||||||||||||||||||||||||||||||||
0x18 | MCMD | ||||||||||||||||||||||||||||||||
0x1c | STAT |
SPIFI control register
Offset: 0x0, reset: 0x400FFFFF, access: read-write
5/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAEN
rw |
FBCLK
rw |
RFCLK
rw |
DUAL
rw |
PRFTCH_DIS
rw |
MODE3
rw |
INTEN
rw |
D_PRFTCH_DIS
rw |
CSHIGH
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMEOUT
rw |
Bits 0-15: This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again..
Bit 23: SPI Mode 3 select..
Allowed values:
0: SCK_LOW: SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH.
0x1: SCK_HIGH: SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
Bit 29: Select active clock edge for input data..
Allowed values:
0: RISING_EDGE: Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.
0x1: FALLING_EDGE: Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
Bit 30: Feedback clock select..
Allowed values:
0: INTERNAL_CLOCK: Internal clock. The SPIFI samples read data using an internal clock.
0x1: FEEDBACK_CLOCK: Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
Bit 31: A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode..
SPIFI command register
Offset: 0x4, reset: 0, access: read-write
3/7 fields covered.
Bit 14: This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs.
Bits 16-18: This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes..
Bits 19-20: This field controls how the fields of the command are sent..
Allowed values:
0: ALL_SERIAL: All serial. All fields of the command are serial.
0x1: QUAD_DUAL_DATA: Quad/dual data. Data field is quad/dual, other fields are serial.
0x2: SERIAL_OPCODE: Serial opcode. Opcode field is serial. Other fields are quad/dual.
0x3: ALL_QUAD_DUAL: All quad/dual. All fields of the command are in quad/dual format.
Bits 21-23: This field controls the opcode and address fields..
Allowed values:
0x1: OPCODE: Opcode. Opcode only, no address.
0x2: OPCODE_1_BYTE: Opcode one byte. Opcode, least significant byte of address.
0x3: OPCODE_2_BYTES: Opcode two bytes. Opcode, two least significant bytes of address.
0x4: OPCODE_3_BYTES: Opcode three bytes. Opcode, three least significant bytes of address.
0x5: OPCODE_4_BYTES: Opcode four bytes. Opcode, 4 bytes of address.
0x6: NO_OPCODE_3_BYTES: No opcode three bytes. No opcode, 3 least significant bytes of address.
0x7: NO_OPCODE_4_BYTES: No opcode four bytes. No opcode, 4 bytes of address.
SPIFI address register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDRESS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
SPIFI intermediate data register
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATA
rw |
SPIFI limit register
Offset: 0x10, reset: 0x8000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLIMIT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLIMIT
rw |
SPIFI data register
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
SPIFI memory command register
Offset: 0x18, reset: 0, access: read-write
2/6 fields covered.
Bits 16-18: This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes..
Bits 19-20: This field controls how the fields of the command are sent..
Allowed values:
0: ALL_SERIAL: All serial. All fields of the command are serial.
0x1: QUAD_DUAL_DATA: Quad/dual data. Data field is quad/dual, other fields are serial.
0x2: SERIAL_OPCODE: Serial opcode. Opcode field is serial. Other fields are quad/dual.
0x3: ALL_QUAD_DUAL: All quad/dual. All fields of the command are in quad/dual format.
Bits 21-23: This field controls the opcode and address fields..
Allowed values:
0x1: OPCODE: Opcode. Opcode only, no address.
0x2: OPCODE_1_BYTE: Opcode one byte. Opcode, least-significant byte of address.
0x3: OPCODE_2_BYTES: Opcode two bytes. Opcode, 2 least-significant bytes of address.
0x4: OPCODE_3_BYTES: Opcode three bytes. Opcode, 3 least-significant bytes of address.
0x5: OPCODE_4_BYTES: Opcode four bytes. Opcode, 4 bytes of address.
0x6: NO_OPCODE_3_BYTES: No opcode three bytes. No opcode, 3 least-significant bytes of address.
0x7: NO_OPCODE_4_BYTES: No opcode, 4 bytes of address.
SPIFI status register
Offset: 0x1c, reset: 0x2000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTRQ
rw |
RESET
rw |
CMD
rw |
MCINIT
rw |
0x40000000: LPC5460x System configuration (SYSCON)
54/514 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x10 | AHBMATPRIO | ||||||||||||||||||||||||||||||||
0x40 | SYSTCKCAL | ||||||||||||||||||||||||||||||||
0x48 | NMISRC | ||||||||||||||||||||||||||||||||
0x4c | ASYNCAPBCTRL | ||||||||||||||||||||||||||||||||
0xc0 | PIOPORCAP[[0]] | ||||||||||||||||||||||||||||||||
0xc4 | PIOPORCAP[[1]] | ||||||||||||||||||||||||||||||||
0xd0 | PIORESCAP[[0]] | ||||||||||||||||||||||||||||||||
0xd4 | PIORESCAP[[1]] | ||||||||||||||||||||||||||||||||
0x100 | PRESETCTRL0 | ||||||||||||||||||||||||||||||||
0x104 | PRESETCTRL1 | ||||||||||||||||||||||||||||||||
0x108 | PRESETCTRL2 | ||||||||||||||||||||||||||||||||
0x120 | PRESETCTRLSET[[0]] | ||||||||||||||||||||||||||||||||
0x124 | PRESETCTRLSET[[1]] | ||||||||||||||||||||||||||||||||
0x128 | PRESETCTRLSET[[2]] | ||||||||||||||||||||||||||||||||
0x140 | PRESETCTRLCLR[[0]] | ||||||||||||||||||||||||||||||||
0x144 | PRESETCTRLCLR[[1]] | ||||||||||||||||||||||||||||||||
0x148 | PRESETCTRLCLR[[2]] | ||||||||||||||||||||||||||||||||
0x1f0 | SYSRSTSTAT | ||||||||||||||||||||||||||||||||
0x200 | AHBCLKCTRL0 | ||||||||||||||||||||||||||||||||
0x204 | AHBCLKCTRL1 | ||||||||||||||||||||||||||||||||
0x208 | AHBCLKCTRL2 | ||||||||||||||||||||||||||||||||
0x220 | AHBCLKCTRLSET[[0]] | ||||||||||||||||||||||||||||||||
0x224 | AHBCLKCTRLSET[[1]] | ||||||||||||||||||||||||||||||||
0x228 | AHBCLKCTRLSET[[2]] | ||||||||||||||||||||||||||||||||
0x240 | AHBCLKCTRLCLR[[0]] | ||||||||||||||||||||||||||||||||
0x244 | AHBCLKCTRLCLR[[1]] | ||||||||||||||||||||||||||||||||
0x248 | AHBCLKCTRLCLR[[2]] | ||||||||||||||||||||||||||||||||
0x280 | MAINCLKSELA | ||||||||||||||||||||||||||||||||
0x284 | MAINCLKSELB | ||||||||||||||||||||||||||||||||
0x288 | CLKOUTSELA | ||||||||||||||||||||||||||||||||
0x290 | SYSPLLCLKSEL | ||||||||||||||||||||||||||||||||
0x298 | AUDPLLCLKSEL | ||||||||||||||||||||||||||||||||
0x2a0 | SPIFICLKSEL | ||||||||||||||||||||||||||||||||
0x2a4 | ADCCLKSEL | ||||||||||||||||||||||||||||||||
0x2a8 | USB0CLKSEL | ||||||||||||||||||||||||||||||||
0x2ac | USB1CLKSEL | ||||||||||||||||||||||||||||||||
0x2b0 | FCLKSEL[[0]] | ||||||||||||||||||||||||||||||||
0x2b4 | FCLKSEL[[1]] | ||||||||||||||||||||||||||||||||
0x2b8 | FCLKSEL[[2]] | ||||||||||||||||||||||||||||||||
0x2bc | FCLKSEL[[3]] | ||||||||||||||||||||||||||||||||
0x2c0 | FCLKSEL[[4]] | ||||||||||||||||||||||||||||||||
0x2c4 | FCLKSEL[[5]] | ||||||||||||||||||||||||||||||||
0x2c8 | FCLKSEL[[6]] | ||||||||||||||||||||||||||||||||
0x2cc | FCLKSEL[[7]] | ||||||||||||||||||||||||||||||||
0x2d0 | FCLKSEL[[8]] | ||||||||||||||||||||||||||||||||
0x2d4 | FCLKSEL[[9]] | ||||||||||||||||||||||||||||||||
0x2e0 | MCLKCLKSEL | ||||||||||||||||||||||||||||||||
0x2e8 | FRGCLKSEL | ||||||||||||||||||||||||||||||||
0x2ec | DMICCLKSEL | ||||||||||||||||||||||||||||||||
0x2f0 | SCTCLKSEL | ||||||||||||||||||||||||||||||||
0x2f4 | LCDCLKSEL | ||||||||||||||||||||||||||||||||
0x2f8 | SDIOCLKSEL | ||||||||||||||||||||||||||||||||
0x300 | SYSTICKCLKDIV | ||||||||||||||||||||||||||||||||
0x304 | ARMTRACECLKDIV | ||||||||||||||||||||||||||||||||
0x308 | CAN0CLKDIV | ||||||||||||||||||||||||||||||||
0x30c | CAN1CLKDIV | ||||||||||||||||||||||||||||||||
0x310 | SC0CLKDIV | ||||||||||||||||||||||||||||||||
0x314 | SC1CLKDIV | ||||||||||||||||||||||||||||||||
0x380 | AHBCLKDIV | ||||||||||||||||||||||||||||||||
0x384 | CLKOUTDIV | ||||||||||||||||||||||||||||||||
0x388 | FROHFCLKDIV | ||||||||||||||||||||||||||||||||
0x390 | SPIFICLKDIV | ||||||||||||||||||||||||||||||||
0x394 | ADCCLKDIV | ||||||||||||||||||||||||||||||||
0x398 | USB0CLKDIV | ||||||||||||||||||||||||||||||||
0x39c | USB1CLKDIV | ||||||||||||||||||||||||||||||||
0x3a0 | FRGCTRL | ||||||||||||||||||||||||||||||||
0x3a8 | DMICCLKDIV | ||||||||||||||||||||||||||||||||
0x3ac | MCLKDIV | ||||||||||||||||||||||||||||||||
0x3b0 | LCDCLKDIV | ||||||||||||||||||||||||||||||||
0x3b4 | SCTCLKDIV | ||||||||||||||||||||||||||||||||
0x3b8 | EMCCLKDIV | ||||||||||||||||||||||||||||||||
0x3bc | SDIOCLKDIV | ||||||||||||||||||||||||||||||||
0x400 | FLASHCFG | ||||||||||||||||||||||||||||||||
0x40c | USB0CLKCTRL | ||||||||||||||||||||||||||||||||
0x410 | USB0CLKSTAT | ||||||||||||||||||||||||||||||||
0x418 | FREQMECTRL | ||||||||||||||||||||||||||||||||
0x420 | MCLKIO | ||||||||||||||||||||||||||||||||
0x424 | USB1CLKCTRL | ||||||||||||||||||||||||||||||||
0x428 | USB1CLKSTAT | ||||||||||||||||||||||||||||||||
0x444 | EMCSYSCTRL | ||||||||||||||||||||||||||||||||
0x448 | EMCDLYCTRL | ||||||||||||||||||||||||||||||||
0x44c | EMCDLYCAL | ||||||||||||||||||||||||||||||||
0x450 | ETHPHYSEL | ||||||||||||||||||||||||||||||||
0x454 | ETHSBDCTRL | ||||||||||||||||||||||||||||||||
0x460 | SDIOCLKCTRL | ||||||||||||||||||||||||||||||||
0x500 | FROCTRL | ||||||||||||||||||||||||||||||||
0x504 | SYSOSCCTRL | ||||||||||||||||||||||||||||||||
0x508 | WDTOSCCTRL | ||||||||||||||||||||||||||||||||
0x50c | RTCOSCCTRL | ||||||||||||||||||||||||||||||||
0x51c | USBPLLCTRL | ||||||||||||||||||||||||||||||||
0x520 | USBPLLSTAT | ||||||||||||||||||||||||||||||||
0x580 | SYSPLLCTRL | ||||||||||||||||||||||||||||||||
0x584 | SYSPLLSTAT | ||||||||||||||||||||||||||||||||
0x588 | SYSPLLNDEC | ||||||||||||||||||||||||||||||||
0x58c | SYSPLLPDEC | ||||||||||||||||||||||||||||||||
0x590 | SYSPLLMDEC | ||||||||||||||||||||||||||||||||
0x5a0 | AUDPLLCTRL | ||||||||||||||||||||||||||||||||
0x5a4 | AUDPLLSTAT | ||||||||||||||||||||||||||||||||
0x5a8 | AUDPLLNDEC | ||||||||||||||||||||||||||||||||
0x5ac | AUDPLLPDEC | ||||||||||||||||||||||||||||||||
0x5b0 | AUDPLLMDEC | ||||||||||||||||||||||||||||||||
0x5b4 | AUDPLLFRAC | ||||||||||||||||||||||||||||||||
0x600 | PDSLEEPCFG0 | ||||||||||||||||||||||||||||||||
0x604 | PDSLEEPCFG1 | ||||||||||||||||||||||||||||||||
0x610 | PDRUNCFG0 | ||||||||||||||||||||||||||||||||
0x614 | PDRUNCFG1 | ||||||||||||||||||||||||||||||||
0x620 | PDRUNCFGSET0 | ||||||||||||||||||||||||||||||||
0x624 | PDRUNCFGSET1 | ||||||||||||||||||||||||||||||||
0x630 | PDRUNCFGCLR0 | ||||||||||||||||||||||||||||||||
0x634 | PDRUNCFGCLR1 | ||||||||||||||||||||||||||||||||
0x680 | STARTER0 | ||||||||||||||||||||||||||||||||
0x684 | STARTER1 | ||||||||||||||||||||||||||||||||
0x6a0 | STARTERSET[[0]] | ||||||||||||||||||||||||||||||||
0x6a4 | STARTERSET[[1]] | ||||||||||||||||||||||||||||||||
0x6c0 | STARTERCLR[[0]] | ||||||||||||||||||||||||||||||||
0x6c4 | STARTERCLR[[1]] | ||||||||||||||||||||||||||||||||
0x780 | HWWAKE | ||||||||||||||||||||||||||||||||
0xe04 | AUTOCGOR | ||||||||||||||||||||||||||||||||
0xff4 | JTAGIDCODE | ||||||||||||||||||||||||||||||||
0xff8 | DEVICE_ID0 | ||||||||||||||||||||||||||||||||
0xffc | DEVICE_ID1 | ||||||||||||||||||||||||||||||||
0x20044 | BODCTRL |
System tick counter calibration
Offset: 0x40, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOREF
rw |
SKEW
rw |
CAL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAL
rw |
NMI Source Select
Offset: 0x48, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NMIENM4
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IRQM4
rw |
Asynchronous APB Control
Offset: 0x4c, reset: 0x1, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE
rw |
POR captured value of port n
Offset: 0xc0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIOPORCAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIOPORCAP
r |
POR captured value of port n
Offset: 0xc4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIOPORCAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIOPORCAP
r |
Reset captured value of port n
Offset: 0xd0, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIORESCAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIORESCAP
r |
Reset captured value of port n
Offset: 0xd4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIORESCAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIORESCAP
r |
Peripheral reset control n
Offset: 0x104, reset: 0, access: read-write
0/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTIMER1_RST
rw |
CTIMER0_RST
rw |
USB0D_RST
rw |
CTIMER2_RST
rw |
DMIC_RST
rw |
FC7_RST
rw |
FC6_RST
rw |
FC5_RST
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FC4_RST
rw |
FC3_RST
rw |
FC2_RST
rw |
FC1_RST
rw |
FC0_RST
rw |
UTICK_RST
rw |
MCAN1_RST
rw |
MCAN0_RST
rw |
SCT0_RST
rw |
MRT_RST
rw |
Peripheral reset control n
Offset: 0x108, reset: 0, access: read-write
0/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SC1_RST
rw |
SC0_RST
rw |
SHA_RST
rw |
USB0HSL_RST
rw |
USB0HMR_RST
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FC9_RST
rw |
FC8_RST
rw |
RNG_RST
rw |
OTP_RST
rw |
AES_RST
rw |
GPIO5_RST
rw |
GPIO4_RST
rw |
ETH_RST
rw |
EMC_RESET
rw |
USB1RAM_RST
rw |
USB1D_RST
rw |
USB1H_RST
rw |
SDIO_RST
rw |
LCD_RST
rw |
Set bits in PRESETCTRLn
Offset: 0x120, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_SET
w |
Set bits in PRESETCTRLn
Offset: 0x124, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_SET
w |
Set bits in PRESETCTRLn
Offset: 0x128, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_SET
w |
Clear bits in PRESETCTRLn
Offset: 0x140, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_CLR
w |
Clear bits in PRESETCTRLn
Offset: 0x144, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_CLR
w |
Clear bits in PRESETCTRLn
Offset: 0x148, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RST_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST_CLR
w |
AHB Clock control n
Offset: 0x204, reset: 0, access: read-write
0/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTIMER1
rw |
CTIMER0
rw |
USB0D
rw |
CTIMER2
rw |
DMIC
rw |
FLEXCOMM7
rw |
FLEXCOMM6
rw |
FLEXCOMM5
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLEXCOMM4
rw |
FLEXCOMM3
rw |
FLEXCOMM2
rw |
FLEXCOMM1
rw |
FLEXCOMM0
rw |
UTICK
rw |
MCAN1
rw |
MCAN0
rw |
SCT0
rw |
RIT
rw |
MRT
rw |
Set bits in AHBCLKCTRLn
Offset: 0x220, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_SET
w |
Set bits in AHBCLKCTRLn
Offset: 0x224, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_SET
w |
Set bits in AHBCLKCTRLn
Offset: 0x228, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_SET
w |
Clear bits in AHBCLKCTRLn
Offset: 0x240, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_CLR
w |
Clear bits in AHBCLKCTRLn
Offset: 0x244, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_CLR
w |
Clear bits in AHBCLKCTRLn
Offset: 0x248, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLK_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_CLR
w |
Main clock source select A
Offset: 0x280, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Main clock source select B
Offset: 0x284, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-1: Clock source for main clock source selector B. Selects the clock source for the main clock..
Allowed values:
0: MAINCLKSELA: MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
0x2: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x3: RTC_OSC_OUTPUT: RTC oscillator 32 kHz output (32k_clk)
CLKOUT clock source select A
Offset: 0x288, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: CLKOUT clock source selection.
Allowed values:
0: MAIN_CLOCK: Main clock (main_clk)
0x1: CLKIN: CLKIN (clk_in)
0x2: WATCHDOG_OSCILLATOR: Watchdog oscillator (wdt_clk)
0x3: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x4: SYSTEM_PLL_OUTPUT: PLL output (pll_clk)
0x5: USB_PLL_CLOCK: USB PLL clock (usb_pll_clk)
0x6: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x7: RTC_OSC_OUTPUT: RTC oscillator 32 kHz output (32k_clk)
PLL clock source select
Offset: 0x290, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: System PLL clock source selection..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: CLKIN: CLKIN (clk_in)
0x2: WATCHDOG_OSCILLATOR: Watchdog oscillator (wdt_clk)
0x3: RTC_OSC_OUTPUT: RTC oscillator 32 kHz output (32k_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Audio PLL clock source select
Offset: 0x298, reset: 0, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
SPIFI clock source select
Offset: 0x2a0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: System PLL clock source selection.
Allowed values:
0: MAIN_CLOCK: Main clock (main_clk)
0x1: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x2: USB_PLL_OUTPUT: USB PLL clock (usb_pll_clk)
0x3: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x4: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
ADC clock source select
Offset: 0x2a4, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: ADC clock source selection.
Allowed values:
0: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x1: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x2: USB_PLL_CLOCK: USB PLL clock (usb_pll_clk)
0x3: AUDIO_PLL_CLOCK: Audio PLL clock (audio_pll_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
USB0 clock source select
Offset: 0x2a8, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
USB1 clock source select
Offset: 0x2ac, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Flexcomm 0 clock source select
Offset: 0x2b0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2b4, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2b8, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2bc, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2c0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2c4, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2c8, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2cc, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2d0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Flexcomm 0 clock source select
Offset: 0x2d4, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Flexcomm clock source selection. One per Flexcomm..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x4: FRG_CLOCK_OUTPUT: FRG clock, the output of the fractional rate generator (frg_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
MCLK clock source select
Offset: 0x2e0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem..
Allowed values:
0: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x1: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Fractional Rate Generator clock source select
Offset: 0x2e8, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: Fractional Rate Generator clock source select..
Allowed values:
0: MAIN_CLOCK: Main clock (main_clk)
0x1: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x2: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x3: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
Digital microphone (DMIC) subsystem clock select
Offset: 0x2ec, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: DMIC (audio subsystem) clock source select..
Allowed values:
0: FRO_12_MHZ: FRO 12 MHz (fro_12m)
0x1: FRO_HF_DIV: FRO HF DIV (fro_hf_div)
0x2: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x3: MCLK_INPUT: MCLK pin input, when selected in IOCON (mclk_in)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
SCTimer/PWM clock source select
Offset: 0x2f0, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: SCT clock source select..
Allowed values:
0: MAIN_CLOCK: Main clock (main_clk)
0x1: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x2: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x3: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
LCD clock source select
Offset: 0x2f4, reset: 0x3, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
SDIO clock source select
Offset: 0x2f8, reset: 0x7, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL
rw |
Bits 0-2: SDIO clock source select..
Allowed values:
0: MAIN_CLOCK: Main clock (main_clk)
0x1: SYSTEM_PLL_OUTPUT: System PLL output (pll_clk)
0x2: USB_PLL_CLOCK: USB PLL clock (usb_pll_clk)
0x3: FRO_HF: FRO 96 or 48 MHz (fro_hf)
0x4: AUDIO_PLL_OUTPUT: Audio PLL clock (audio_pll_clk)
0x7: NONE: None, this may be selected in order to reduce power when no output is needed.
SYSTICK clock divider
Offset: 0x300, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
ARM Trace clock divider
Offset: 0x304, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
MCAN0 clock divider
Offset: 0x308, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
MCAN1 clock divider
Offset: 0x30c, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Smartcard0 clock divider
Offset: 0x310, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Smartcard1 clock divider
Offset: 0x314, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
AHB clock divider
Offset: 0x380, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
CLKOUT clock divider
Offset: 0x384, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
FROHF clock divider
Offset: 0x388, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
SPIFI clock divider
Offset: 0x390, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
ADC clock divider
Offset: 0x394, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
USB0 clock divider
Offset: 0x398, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
USB1 clock divider
Offset: 0x39c, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Fractional rate divider
Offset: 0x3a0, reset: 0xFF, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MULT
rw |
DIV
rw |
DMIC clock divider
Offset: 0x3a8, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
I2S MCLK clock divider
Offset: 0x3ac, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
LCD clock divider
Offset: 0x3b0, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
SCT/PWM clock divider
Offset: 0x3b4, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
EMC clock divider
Offset: 0x3b8, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
SDIO clock divider
Offset: 0x3bc, reset: 0x40000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REQFLAG
rw |
HALT
rw |
RESET
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
rw |
Flash wait states configuration
Offset: 0x400, reset: 0xD1A, access: read-write
6/6 fields covered.
Bits 0-1: Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches..
Allowed values:
0: NO_BUFFER: Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled.
0x1: ONE_BUFFER: One buffer is used for all instruction fetches.
0x2: ALL_BUFFERS: All buffers may be used for instruction fetches.
Bits 2-3: Data read configuration. This field determines how flash accelerator buffers are used for data accesses..
Allowed values:
0: NOT_BUFFERED: Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory.
0x1: ONE_BUFFER: One buffer is used for all data accesses.
0x2: ALL_BUFFERS: All buffers may be used for data accesses.
Bit 4: Acceleration enable..
Allowed values:
0: DISABLED: Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance.
0x1: ENABLED: Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings.
Bit 6: Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched..
Allowed values:
0: PREFETCH_COMPLETED: Any previously initiated prefetch will be completed.
0x1: PREFETCH_ABORT: Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered.
Bits 12-15: Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1..
Allowed values:
0: N_1_CLOCK_CYCLE: 1 system clock flash access time (for system clock rates up to 12 MHz).
0x1: N_2_CLOCK_CYCLES: 2 system clocks flash access time (for system clock rates up to 30 MHz).
0x2: N_3_CLOCK_CYCLES: 3 system clocks flash access time (for system clock rates up to 60 MHz).
0x3: N_4_CLOCK_CYCLES: 4 system clocks flash access time (for system clock rates up to 85 MHz).
0x4: N_5_CLOCK_CYCLES: 5 system clocks flash access time (for system clock rates up to 100 MHz).
USB0 clock control
Offset: 0x40c, reset: 0, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PU_DISABLE
rw |
POL_FS_HOST_CLK
rw |
AP_FS_HOST_CLK
rw |
POL_FS_DEV_CLK
rw |
AP_FS_DEV_CLK
rw |
USB0 clock status
Offset: 0x410, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HOST_NEED_CLKST
rw |
DEV_NEED_CLKST
rw |
Frequency measure register
Offset: 0x418, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PROG
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPVAL
rw |
MCLK input/output control
Offset: 0x420, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR
rw |
USB1 clock control
Offset: 0x424, reset: 0x10, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HS_DEV_WAKEUP_N
rw |
POL_FS_HOST_CLK
rw |
AP_FS_HOST_CLK
rw |
POL_FS_DEV_CLK
rw |
AP_FS_DEV_CLK
rw |
USB1 clock status
Offset: 0x428, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HOST_NEED_CLKST
rw |
DEV_NEED_CLKST
rw |
EMC system control
Offset: 0x444, reset: 0x1, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EMCFBCLKINSEL
rw |
EMCBC
rw |
EMCRD
rw |
EMCSC
rw |
EMC clock delay control
Offset: 0x448, reset: 0x210, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FBCLK_DELAY
rw |
CMD_DELAY
rw |
EMC delay chain calibration control
Offset: 0x44c, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DONE
rw |
START
rw |
CALVALUE
rw |
Ethernet PHY Selection
Offset: 0x450, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_SEL
rw |
Ethernet SBD flow control
Offset: 0x454, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SBD_CTRL
rw |
SDIO CCLKIN phase and delay control
Offset: 0x460, reset: 0, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCLK_SAMPLE_DELAY_ACTIVE
rw |
CCLK_SAMPLE_DELAY
rw |
CCLK_DRV_DELAY_ACTIVE
rw |
CCLK_DRV_DELAY
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE_ACTIVE
rw |
CCLK_SAMPLE_PHASE
rw |
CCLK_DRV_PHASE
rw |
System oscillator control
Offset: 0x504, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQRANGE
rw |
BYPASS
rw |
Watchdog oscillator control
Offset: 0x508, reset: 0xA0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQSEL
rw |
DIVSEL
rw |
RTC oscillator 32 kHz output control
Offset: 0x50c, reset: 0x1, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN
rw |
USB PLL status
Offset: 0x520, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK
rw |
PLL status
Offset: 0x584, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK
rw |
PLL N divider
Offset: 0x588, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NREQ
rw |
NDEC
rw |
PLL P divider
Offset: 0x58c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PREQ
rw |
PDEC
rw |
System PLL M divider
Offset: 0x590, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MREQ
rw |
MDEC
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDEC
rw |
Audio PLL status
Offset: 0x5a4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK
rw |
Audio PLL N divider
Offset: 0x5a8, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NREQ
rw |
NDEC
rw |
Audio PLL P divider
Offset: 0x5ac, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PREQ
rw |
PDEC
rw |
Audio PLL M divider
Offset: 0x5b0, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MREQ
rw |
MDEC
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDEC
rw |
Audio PLL fractional divider control
Offset: 0x5b4, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SEL_EXT
rw |
REQ
rw |
CTRL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRL
rw |
Sleep configuration register
Offset: 0x600, reset: 0xF81F40, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PDEN_VD6
rw |
PDEN_VD5
rw |
PDEN_VD4
rw |
PDEN_VD3
rw |
PDEN_VREFP
rw |
PDEN_SYS_PLL
rw |
PDEN_USB0_PHY
rw |
PDEN_WDT_OSC
rw |
PDEN_VDDA
rw |
PDEN_ROM
rw |
PDEN_USB_RAM
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_SRAM1_2_3
rw |
PDEN_SRAM0
rw |
PDEN_SRAMX
rw |
PDEN_ADC0
rw |
PDEN_VD2_ANA
rw |
PDEN_BOD_INTR
rw |
PDEN_BOD_RST
rw |
PDEN_TS
rw |
PDEN_FRO
rw |
Sleep configuration register
Offset: 0x604, reset: 0xF81F40, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_RNG
rw |
PDEN_EEPROM
rw |
PDEN_SYSOSC
rw |
PDEN_AUD_PLL
rw |
PDEN_USB1_PLL
rw |
PDEN_USB1_PHY
rw |
Power configuration register
Offset: 0x610, reset: 0x14F81F40, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PDEN_VD6
rw |
PDEN_VD5
rw |
PDEN_VD4
rw |
PDEN_VD3
rw |
PDEN_VREFP
rw |
PDEN_SYS_PLL
rw |
PDEN_USB0_PHY
rw |
PDEN_WDT_OSC
rw |
PDEN_VDDA
rw |
PDEN_ROM
rw |
PDEN_USB_RAM
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_SRAM1_2_3
rw |
PDEN_SRAM0
rw |
PDEN_SRAMX
rw |
PDEN_ADC0
rw |
PDEN_VD2_ANA
rw |
PDEN_BOD_INTR
rw |
PDEN_BOD_RST
rw |
PDEN_TS
rw |
PDEN_FRO
rw |
Power configuration register
Offset: 0x614, reset: 0x14F81F40, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_RNG
rw |
PDEN_EEPROM
rw |
PDEN_SYSOSC
rw |
PDEN_AUD_PLL
rw |
PDEN_USB1_PLL
rw |
PDEN_USB1_PHY
rw |
Power configuration set register
Offset: 0x620, reset: 0, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PDEN_VD6
rw |
PDEN_VD5
rw |
PDEN_VD4
rw |
PDEN_VD3
rw |
PDEN_VREFP
rw |
PDEN_SYS_PLL
rw |
PDEN_USB0_PHY
rw |
PDEN_WDT_OSC
rw |
PDEN_VDDA
rw |
PDEN_ROM
rw |
PDEN_USB_RAM
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_SRAM1_2_3
rw |
PDEN_SRAM0
rw |
PDEN_SRAMX
rw |
PDEN_ADC0
rw |
PDEN_VD2_ANA
rw |
PDEN_BOD_INTR
rw |
PDEN_BOD_RST
rw |
PDEN_TS
rw |
PDEN_FRO
rw |
Power configuration set register
Offset: 0x624, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_RNG
rw |
PDEN_EEPROM
rw |
PDEN_SYSOSC
rw |
PDEN_AUD_PLL
rw |
PDEN_USB1_PLL
rw |
PDEN_USB1_PHY
rw |
Power configuration clear register
Offset: 0x630, reset: 0, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PDEN_VD6
rw |
PDEN_VD5
rw |
PDEN_VD4
rw |
PDEN_VD3
rw |
PDEN_VREFP
rw |
PDEN_SYS_PLL
rw |
PDEN_USB0_PHY
rw |
PDEN_WDT_OSC
rw |
PDEN_VDDA
rw |
PDEN_ROM
rw |
PDEN_USB_RAM
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_SRAM1_2_3
rw |
PDEN_SRAM0
rw |
PDEN_SRAMX
rw |
PDEN_ADC0
rw |
PDEN_VD2_ANA
rw |
PDEN_BOD_INTR
rw |
PDEN_BOD_RST
rw |
PDEN_TS
rw |
PDEN_FRO
rw |
Power configuration clear register
Offset: 0x634, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDEN_RNG
rw |
PDEN_EEPROM
rw |
PDEN_SYSOSC
rw |
PDEN_AUD_PLL
rw |
PDEN_USB1_PLL
rw |
PDEN_USB1_PHY
rw |
Start logic 0 wake-up enable register
Offset: 0x680, reset: 0, access: read-write
0/30 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RTC
rw |
USB0
rw |
USB0_NEEDCLK
rw |
HWVAD
rw |
DMIC
rw |
ADC0_THCMP
rw |
ADC0_SEQB
rw |
ADC0_SEQA
rw |
FLEXCOMM7
rw |
FLEXCOMM6
rw |
FLEXCOMM5
rw |
FLEXCOMM4
rw |
FLEXCOMM3
rw |
FLEXCOMM2
rw |
||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLEXCOMM1
rw |
FLEXCOMM0
rw |
CTIMER3
rw |
SCT0
rw |
CTIMER1
rw |
CTIMER0
rw |
MRT
rw |
UTICK
rw |
PIN_INT3
rw |
PIN_INT2
rw |
PIN_INT1
rw |
PIN_INT0
rw |
GINT1
rw |
GINT0
rw |
DMA
rw |
WDT_BOD
rw |
Set bits in STARTER
Offset: 0x6a0, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_SET
w |
Set bits in STARTER
Offset: 0x6a4, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START_SET
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_SET
w |
Clear bits in STARTER0
Offset: 0x6c0, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_CLR
w |
Clear bits in STARTER0
Offset: 0x6c4, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
START_CLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_CLR
w |
Configures special cases of hardware wake-up
Offset: 0x780, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAKEDMA
rw |
WAKEDMIC
rw |
FCWAKE
rw |
FORCEWAKE
rw |
Bit 0: Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to continue operating while the main CPU(s) are shut down..
Bit 3: Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity..
Auto Clock-Gate Override Register
Offset: 0xe04, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM3
rw |
RAM2
rw |
RAM1
rw |
RAM0X
rw |
JTAG ID code register
Offset: 0xff4, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JTAGID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JTAGID
r |
Part ID register
Offset: 0xff8, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PARTID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PARTID
r |
Boot ROM and die revision register
Offset: 0xffc, reset: 0, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REVID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVID
r |
Brown-Out Detect control
Offset: 0x20044, reset: 0, access: read-write
4/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BODINTSTAT
rw |
BODRSTSTAT
rw |
BODINTENA
rw |
BODINTLEV
rw |
BODRSTENA
rw |
BODRSTLEV
rw |
0xe000e000: System Control Block
80/99 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x8 | ACTLR | ||||||||||||||||||||||||||||||||
0xd00 | CPUID | ||||||||||||||||||||||||||||||||
0xd04 | ICSR | ||||||||||||||||||||||||||||||||
0xd08 | VTOR | ||||||||||||||||||||||||||||||||
0xd0c | AIRCR | ||||||||||||||||||||||||||||||||
0xd10 | SCR | ||||||||||||||||||||||||||||||||
0xd14 | CCR | ||||||||||||||||||||||||||||||||
0xd18 | SHPR1 | ||||||||||||||||||||||||||||||||
0xd1c | SHPR2 | ||||||||||||||||||||||||||||||||
0xd20 | SHPR3 | ||||||||||||||||||||||||||||||||
0xd24 | SHCSR | ||||||||||||||||||||||||||||||||
0xd28 | CFSR | ||||||||||||||||||||||||||||||||
0xd2c | HFSR | ||||||||||||||||||||||||||||||||
0xd30 | DFSR | ||||||||||||||||||||||||||||||||
0xd34 | MMFAR | ||||||||||||||||||||||||||||||||
0xd38 | BFAR | ||||||||||||||||||||||||||||||||
0xd3c | AFSR | ||||||||||||||||||||||||||||||||
0xd88 | CPACR | ||||||||||||||||||||||||||||||||
0xf34 | FPCCR | ||||||||||||||||||||||||||||||||
0xf38 | FPCAR | ||||||||||||||||||||||||||||||||
0xf3c | FPDSCR |
Auxiliary Control Register,
Offset: 0x8, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
CPUID Base Register
Offset: 0xd00, reset: 0x410FC240, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IMPLEMENTER
r |
VARIANT
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PARTNO
r |
REVISION
r |
Interrupt Control and State Register
Offset: 0xd04, reset: 0, access: read-write
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
w |
PENDSTSET
rw |
PENDSTCLR
w |
ISRPREEMPT
r |
ISRPENDING
r |
VECTPENDING
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECTPENDING
r |
RETTOBASE
r |
VECTACTIVE
r |
Vector Table Offset Register
Offset: 0xd08, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TBLOFF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBLOFF
rw |
Application Interrupt and Reset Control Register
Offset: 0xd0c, reset: 0xFA050000, access: read-write
2/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VECTKEY
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENDIANNESS
r |
PRIGROUP
rw |
SYSRESETREQ
w |
VECTCLRACTIVE
w |
VECTRESET
w |
System Control Register
Offset: 0xd10, reset: 0, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEVONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
Configuration and Control Register
Offset: 0xd14, reset: 0, access: read-write
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN_TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
Bit 8: Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions..
Allowed values:
0: BFHFNMIGN_0: data bus faults caused by load and store instructions cause a lock-up
0x1: BFHFNMIGN_1: handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
System Handler Priority Register 1
Offset: 0xd18, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_6
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_5
rw |
PRI_4
rw |
System Handler Priority Register 2
Offset: 0xd1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_11
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System Handler Priority Register 3
Offset: 0xd20, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_15
rw |
PRI_14
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System Handler Control and State Register
Offset: 0xd24, reset: 0, access: read-write
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
Configurable Fault Status Registers
Offset: 0xd28, reset: 0, access: read-write
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
DACCVIOL
rw |
IACCVIOL
rw |
HardFault Status register
Offset: 0xd2c, reset: 0, access: read-write
2/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEBUGEVT
rw |
FORCED
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECTTBL
rw |
MemManage Address Register
Offset: 0xd34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDRESS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
BusFault Address Register
Offset: 0xd38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDRESS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
Auxiliary Fault Status Register
Offset: 0xd3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AUXFAULT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUXFAULT
rw |
Coprocessor Access Control Register
Offset: 0xd88, reset: 0, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CP11
rw |
CP10
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Floating-point Context Control Register
Offset: 0xf34, reset: 0xC0000000, access: read-write
9/9 fields covered.
Bit 4: Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated..
Allowed values:
0: HFRDY_0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
0x1: HFRDY_1: Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
Bit 5: Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated..
Allowed values:
0: MMRDY_0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
0x1: MMRDY_1: MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
Bit 6: Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated..
Allowed values:
0: BFRDY_0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
0x1: BFRDY_1: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
Bit 8: Permission to set the MON_PEND when the floating-point stack frame was allocated..
Allowed values:
0: MONRDY_0: DebugMonitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated.
0x1: MONRDY_1: DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
Bit 31: Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit..
Allowed values:
0: ASPEN_0: Disable CONTROL2 setting on execution of a floating-point instruction.
0x1: ASPEN_1: Enable CONTROL2 setting on execution of a floating-point instruction.
Floating-point Context Address Register
Offset: 0xf38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDRESS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
Floating-point Default Status Control Register
Offset: 0xf3c, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AHP
rw |
DN
rw |
FZ
rw |
RMode
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0xe000e010: System timer
6/9 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CSR | ||||||||||||||||||||||||||||||||
0x4 | RVR | ||||||||||||||||||||||||||||||||
0x8 | CVR | ||||||||||||||||||||||||||||||||
0xc | CALIB |
SysTick Control and Status Register
Offset: 0x0, reset: 0x4, access: read-write
3/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COUNTFLAG
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKSOURCE
rw |
TICKINT
rw |
ENABLE
rw |
SysTick Reload Value Register
Offset: 0x4, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RELOAD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RELOAD
rw |
SysTick Current Value Register
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CURRENT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CURRENT
rw |
SysTick Calibration Value Register
Offset: 0xc, reset: 0x80000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOREF
r |
SKEW
r |
TENMS
r |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TENMS
r |
0x40086000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40087000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40088000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40089000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4008a000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40096000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40097000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40098000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40099000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x4009a000: LPC5411x USARTs
75/114 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CFG | ||||||||||||||||||||||||||||||||
0x4 | CTL | ||||||||||||||||||||||||||||||||
0x8 | STAT | ||||||||||||||||||||||||||||||||
0xc | INTENSET | ||||||||||||||||||||||||||||||||
0x10 | INTENCLR | ||||||||||||||||||||||||||||||||
0x20 | BRG | ||||||||||||||||||||||||||||||||
0x24 | INTSTAT | ||||||||||||||||||||||||||||||||
0x28 | OSR | ||||||||||||||||||||||||||||||||
0x2c | ADDR | ||||||||||||||||||||||||||||||||
0xe00 | FIFOCFG | ||||||||||||||||||||||||||||||||
0xe04 | FIFOSTAT | ||||||||||||||||||||||||||||||||
0xe08 | FIFOTRIG | ||||||||||||||||||||||||||||||||
0xe10 | FIFOINTENSET | ||||||||||||||||||||||||||||||||
0xe14 | FIFOINTENCLR | ||||||||||||||||||||||||||||||||
0xe18 | FIFOINTSTAT | ||||||||||||||||||||||||||||||||
0xe20 | FIFOWR | ||||||||||||||||||||||||||||||||
0xe30 | FIFORD | ||||||||||||||||||||||||||||||||
0xe40 | FIFORDNOPOP | ||||||||||||||||||||||||||||||||
0xffc | ID |
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
Offset: 0x0, reset: 0, access: read-write
17/17 fields covered.
Bit 0: USART Enable..
Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.
Bits 4-5: Selects what type of parity is used by the USART..
Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..
Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
Bit 15: Selects data loopback mode..
Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
Bit 18: Output Enable Turnaround time enable for RS-485 operation..
Allowed values:
0: DISABLED: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1: ENABLED: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
Bit 19: Automatic Address matching enable..
Allowed values:
0: DISABLED: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1: ENABLED: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
Bit 22: Receive data polarity..
Allowed values:
0: STANDARD: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
Bit 23: Transmit data polarity..
Allowed values:
0: STANDARD: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1: INVERTED: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
USART Control register. USART control settings that are more likely to change during operation.
Offset: 0x4, reset: 0, access: read-write
6/6 fields covered.
Bit 1: Break Enable..
Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
Bit 2: Enable address detect mode..
Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..
Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
Bit 16: Autobaud enable..
Allowed values:
0: DISABLED: Disabled. USART is in normal operating mode.
0x1: ENABLED: Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
Offset: 0x8, reset: 0xA, access: read-write
5/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
rw |
PARITYERRINT
rw |
FRAMERRINT
rw |
START
rw |
DELTARXBRK
rw |
RXBRK
r |
TXDISSTAT
r |
DELTACTS
rw |
CTS
r |
TXIDLE
r |
RXIDLE
r |
Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..
Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Offset: 0xc, reset: 0, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERREN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEEN
rw |
PARITYERREN
rw |
FRAMERREN
rw |
STARTEN
rw |
DELTARXBRKEN
rw |
TXDISEN
rw |
DELTACTSEN
rw |
TXIDLEEN
rw |
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
Offset: 0x10, reset: 0, access: write-only
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRCLR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISECLR
w |
PARITYERRCLR
w |
FRAMERRCLR
w |
STARTCLR
w |
DELTARXBRKCLR
w |
TXDISCLR
w |
DELTACTSCLR
w |
TXIDLECLR
w |
Baud Rate Generator register. 16-bit integer baud rate divisor value.
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRGVAL
rw |
Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..
Interrupt status register. Reflects interrupts that are currently enabled.
Offset: 0x24, reset: 0, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ABERRINT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISEINT
r |
PARITYERRINT
r |
FRAMERRINT
r |
START
r |
DELTARXBRK
r |
TXDISINT
r |
DELTACTS
r |
TXIDLE
r |
Oversample selection register for asynchronous communication.
Offset: 0x28, reset: 0xF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSRVAL
rw |
Address register for automatic address matching.
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS
rw |
FIFO configuration and enable register.
Offset: 0xe00, reset: 0, access: read-write
8/10 fields covered.
Bit 14: Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.
Bit 15: Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register..
Allowed values:
0: DISABLED: Only enabled interrupts will wake up the device form reduced power modes.
0x1: ENABLED: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.
FIFO status register.
Offset: 0xe04, reset: 0x30, access: read-write
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
r |
RXFULL
r |
RXNOTEMPTY
r |
TXNOTFULL
r |
TXEMPTY
r |
PERINT
r |
RXERR
rw |
TXERR
rw |
FIFO trigger settings for interrupt and DMA request.
Offset: 0xe08, reset: 0, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXLVL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXLVL
rw |
RXLVLENA
rw |
TXLVLENA
rw |
Bit 0: Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set..
Allowed values:
0: DISABLED: Transmit FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Bit 1: Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set..
Allowed values:
0: DISABLED: Receive FIFO level does not generate a FIFO level trigger.
0x1: ENABLED: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
Bits 8-11: Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)..
Bits 16-19: Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)..
FIFO interrupt enable set (enable) and read register.
Offset: 0xe10, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
Bit 2: Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the TX FIFO level.
0x1: ENABLED: If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
Bit 3: Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register..
Allowed values:
0: DISABLED: No interrupt will be generated based on the RX FIFO level.
0x1: ENABLED: If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
FIFO interrupt enable clear (disable) and read register.
Offset: 0xe14, reset: 0, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXLVL
rw |
TXLVL
rw |
RXERR
rw |
TXERR
rw |
FIFO write data.
Offset: 0xe20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA
rw |
FIFO read data.
Offset: 0xe30, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
FIFO data read with no FIFO pop.
Offset: 0xe40, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNOISE
r |
PARITYERR
r |
FRAMERR
r |
RXDATA
r |
Bit 13: Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..
Peripheral identification register.
Offset: 0xffc, reset: 0, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REV
r |
MINOR_REV
r |
APERTURE
r |
0x40084000: LPC5411x USB 2.0 Device Controller
13/48 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DEVCMDSTAT | ||||||||||||||||||||||||||||||||
0x4 | INFO | ||||||||||||||||||||||||||||||||
0x8 | EPLISTSTART | ||||||||||||||||||||||||||||||||
0xc | DATABUFSTART | ||||||||||||||||||||||||||||||||
0x10 | LPM | ||||||||||||||||||||||||||||||||
0x14 | EPSKIP | ||||||||||||||||||||||||||||||||
0x18 | EPINUSE | ||||||||||||||||||||||||||||||||
0x1c | EPBUFCFG | ||||||||||||||||||||||||||||||||
0x20 | INTSTAT | ||||||||||||||||||||||||||||||||
0x24 | INTEN | ||||||||||||||||||||||||||||||||
0x28 | INTSETSTAT | ||||||||||||||||||||||||||||||||
0x34 | EPTOGGLE |
USB Device Command/Status register
Offset: 0x0, reset: 0x800, access: read-write
8/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBUSDEBOUNCED
r |
DRES_C
rw |
DSUS_C
rw |
DCON_C
rw |
LPM_REWP
r |
LPM_SUS
rw |
DSUS
rw |
DCON
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTONNAK_CI
rw |
INTONNAK_CO
rw |
INTONNAK_AI
rw |
INTONNAK_AO
rw |
LPM_SUP
rw |
FORCE_NEEDCLK
rw |
SETUP
rw |
DEV_EN
rw |
DEV_ADDR
rw |
Bits 0-6: USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request..
Bit 8: SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW..
Bit 17: Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect..
Bit 19: Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one..
Bit 20: LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction..
Bit 25: Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it..
USB Info register
Offset: 0x4, reset: 0, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MAJREV
r |
MINREV
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_CODE
rw |
FRAME_NR
r |
Bits 0-10: Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device..
Bits 11-14: The error code which last occurred:.
Allowed values:
0: NO_ERROR: No error
0x1: PID_ENCODING_ERROR: PID encoding error
0x2: PID_UNKNOWN: PID unknown
0x3: PACKET_UNEXPECTED: Packet unexpected
0x4: TOKEN_CRC_ERROR: Token CRC error
0x5: DATA_CRC_ERROR: Data CRC error
0x6: TIMEOUT: Time out
0x7: BABBLE: Babble
0x8: TRUNCATED_EOP: Truncated EOP
0x9: SENT_RECEIVED_NAK: Sent/Received NAK
0xA: SENT_STALL: Sent Stall
0xB: OVERRUN: Overrun
0xC: SENT_EMPTY_PACKET: Sent empty packet
0xD: BITSTUFF_ERROR: Bitstuff error
0xE: SYNC_ERROR: Sync error
0xF: WRONG_DATA_TOGGLE: Wrong data toggle
USB EP Command/Status List start address
Offset: 0x8, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EP_LIST
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_LIST
rw |
USB Data buffer start address
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DA_BUF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USB Link Power Management register
Offset: 0x10, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_PENDING
rw |
HIRD_SW
rw |
HIRD_HW
r |
Bit 8: As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1..
USB Endpoint skip
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SKIP
rw |
Bits 0-9: Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit..
USB Endpoint Buffer in use
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUF
rw |
USB Endpoint Buffer Configuration register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUF_SB
rw |
Bits 2-9: Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer..
USB interrupt status register
Offset: 0x20, reset: 0, access: read-write
0/12 fields covered.
Bit 0: Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it..
Bit 1: Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it..
Bit 2: Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it..
Bit 3: Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it..
Bit 4: Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it..
Bit 5: Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it..
Bit 6: Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it..
Bit 7: Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it..
Bit 8: Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it..
Bit 9: Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it..
USB interrupt enable register
Offset: 0x24, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEV_INT_EN
rw |
FRAME_INT_EN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_INT_EN
rw |
USB set interrupt status register
Offset: 0x28, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEV_SET_INT
rw |
FRAME_SET_INT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_SET_INT
rw |
USB Endpoint toggle register
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLE
rw |
0x400a2000: LPC5460x USB0 Full-speed Host controller
1/86 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | HCREVISION | ||||||||||||||||||||||||||||||||
0x4 | HCCONTROL | ||||||||||||||||||||||||||||||||
0x8 | HCCOMMANDSTATUS | ||||||||||||||||||||||||||||||||
0xc | HCINTERRUPTSTATUS | ||||||||||||||||||||||||||||||||
0x10 | HCINTERRUPTENABLE | ||||||||||||||||||||||||||||||||
0x14 | HCINTERRUPTDISABLE | ||||||||||||||||||||||||||||||||
0x18 | HCHCCA | ||||||||||||||||||||||||||||||||
0x1c | HCPERIODCURRENTED | ||||||||||||||||||||||||||||||||
0x20 | HCCONTROLHEADED | ||||||||||||||||||||||||||||||||
0x24 | HCCONTROLCURRENTED | ||||||||||||||||||||||||||||||||
0x28 | HCBULKHEADED | ||||||||||||||||||||||||||||||||
0x2c | HCBULKCURRENTED | ||||||||||||||||||||||||||||||||
0x30 | HCDONEHEAD | ||||||||||||||||||||||||||||||||
0x34 | HCFMINTERVAL | ||||||||||||||||||||||||||||||||
0x38 | HCFMREMAINING | ||||||||||||||||||||||||||||||||
0x3c | HCFMNUMBER | ||||||||||||||||||||||||||||||||
0x40 | HCPERIODICSTART | ||||||||||||||||||||||||||||||||
0x44 | HCLSTHRESHOLD | ||||||||||||||||||||||||||||||||
0x48 | HCRHDESCRIPTORA | ||||||||||||||||||||||||||||||||
0x4c | HCRHDESCRIPTORB | ||||||||||||||||||||||||||||||||
0x50 | HCRHSTATUS | ||||||||||||||||||||||||||||||||
0x54 | HCRHPORTSTATUS | ||||||||||||||||||||||||||||||||
0x5c | PORTMODE |
BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC)
Offset: 0x0, reset: 0x10, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV
r |
Contains the physical address of the host controller communication area
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HCCA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HCCA
rw |
Contains the physical address of the current isochronous or interrupt endpoint descriptor
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCED
rw |
Contains the physical address of the first endpoint descriptor of the control list
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHED
rw |
Contains the physical address of the current endpoint descriptor of the control list
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCED
rw |
Contains the physical address of the first endpoint descriptor of the bulk list
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BHED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BHED
rw |
Contains the physical address of the current endpoint descriptor of the bulk list
Offset: 0x2c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BCED
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCED
rw |
Contains the physical address of the last transfer descriptor added to the 'Done' queue
Offset: 0x30, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DH
rw |
Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun
Offset: 0x34, reset: 0x2EDF, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FIT
rw |
FSMPS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FI
rw |
A 14-bit counter showing the bit time remaining in the current frame
Offset: 0x38, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FRT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FR
rw |
Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FN
rw |
Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PS
rw |
Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF
Offset: 0x44, reset: 0x628, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LST
rw |
Second of the two registers which describes the characteristics of the Root Hub
Offset: 0x4c, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PPCM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DR
rw |
Controls the port if it is attached to the host block or the device block
Offset: 0x5c, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEV_ENABLE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID_EN
rw |
ID
rw |
0x40094000: LPC5460x USB1 High-speed Device Controller
9/60 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DEVCMDSTAT | ||||||||||||||||||||||||||||||||
0x4 | INFO | ||||||||||||||||||||||||||||||||
0x8 | EPLISTSTART | ||||||||||||||||||||||||||||||||
0xc | DATABUFSTART | ||||||||||||||||||||||||||||||||
0x10 | LPM | ||||||||||||||||||||||||||||||||
0x14 | EPSKIP | ||||||||||||||||||||||||||||||||
0x18 | EPINUSE | ||||||||||||||||||||||||||||||||
0x1c | EPBUFCFG | ||||||||||||||||||||||||||||||||
0x20 | INTSTAT | ||||||||||||||||||||||||||||||||
0x24 | INTEN | ||||||||||||||||||||||||||||||||
0x28 | INTSETSTAT | ||||||||||||||||||||||||||||||||
0x34 | EPTOGGLE | ||||||||||||||||||||||||||||||||
0x3c | ULPIDEBUG |
USB Device Command/Status register
Offset: 0x0, reset: 0x800, access: read-write
3/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PHY_TEST_MODE
rw |
VBUS_DEBOUNCED
r |
DRES_C
rw |
DSUS_C
rw |
DCON_C
rw |
Speed
r |
LPM_REWP
r |
LPM_SUS
rw |
DSUS
rw |
DCON
rw |
||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTONNAK_CI
rw |
INTONNAK_CO
rw |
INTONNAK_AI
rw |
INTONNAK_AO
rw |
LPM_SUP
rw |
FORCE_VBUS
rw |
FORCE_NEEDCLK
rw |
SETUP
rw |
DEV_EN
rw |
DEV_ADDR
rw |
USB Info register
Offset: 0x4, reset: 0x2000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Majrev
r |
Minrev
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_CODE
r |
FRAME_NR
r |
USB EP Command/Status List start address
Offset: 0x8, reset: 0, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EP_LIST_FIXED
r |
EP_LIST_PRG
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_LIST_PRG
rw |
USB Data buffer start address
Offset: 0xc, reset: 0x41000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DA_BUF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DA_BUF
rw |
USB Link Power Management register
Offset: 0x10, reset: 0, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_PENDING
rw |
HIRD_SW
rw |
HIRD_HW
r |
USB Endpoint skip
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SKIP
rw |
USB Endpoint Buffer in use
Offset: 0x18, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUF
rw |
USB Endpoint Buffer Configuration register
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUF_SB
rw |
USB interrupt enable register
Offset: 0x24, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEV_INT_EN
rw |
FRAME_INT_EN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_INT_EN
rw |
USB set interrupt status register
Offset: 0x28, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEV_SET_INT
rw |
FRAME_SET_INT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP_SET_INT
rw |
USB Endpoint toggle register
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TOGGLE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLE
rw |
UTMI/ULPI debug register
Offset: 0x3c, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PHY_MODE
rw |
PHY_ACCESS
rw |
PHY_RW
rw |
PHY_RDATA
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_WDATA
rw |
PHY_ADDR
rw |
0x400a3000: LPC5460x USB1 High-speed Host Controller
7/74 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CAPLENGTH_CHIPID | ||||||||||||||||||||||||||||||||
0x4 | HCSPARAMS | ||||||||||||||||||||||||||||||||
0x8 | HCCPARAMS | ||||||||||||||||||||||||||||||||
0xc | FLADJ_FRINDEX | ||||||||||||||||||||||||||||||||
0x10 | ATL_PTD_BASE_ADDR | ||||||||||||||||||||||||||||||||
0x14 | ISO_PTD_BASE_ADDR | ||||||||||||||||||||||||||||||||
0x18 | INT_PTD_BASE_ADDR | ||||||||||||||||||||||||||||||||
0x1c | DATA_PAYLOAD_BASE_ADDR | ||||||||||||||||||||||||||||||||
0x20 | USBCMD | ||||||||||||||||||||||||||||||||
0x24 | USBSTS | ||||||||||||||||||||||||||||||||
0x28 | USBINTR | ||||||||||||||||||||||||||||||||
0x2c | PORTSC1 | ||||||||||||||||||||||||||||||||
0x30 | ATL_PTD_DONE_MAP | ||||||||||||||||||||||||||||||||
0x34 | ATL_PTD_SKIP_MAP | ||||||||||||||||||||||||||||||||
0x38 | ISO_PTD_DONE_MAP | ||||||||||||||||||||||||||||||||
0x3c | ISO_PTD_SKIP_MAP | ||||||||||||||||||||||||||||||||
0x40 | INT_PTD_DONE_MAP | ||||||||||||||||||||||||||||||||
0x44 | INT_PTD_SKIP_MAP | ||||||||||||||||||||||||||||||||
0x48 | LAST_PTD_INUSE | ||||||||||||||||||||||||||||||||
0x4c | UTMIPLUS_ULPI_DEBUG | ||||||||||||||||||||||||||||||||
0x50 | PORTMODE |
This register contains the offset value towards the start of the operational register space and the version number of the IP block
Offset: 0x0, reset: 0x1010010, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHIPID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPLENGTH
r |
Host Controller Structural Parameters
Offset: 0x4, reset: 0x10011, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P_INDICATOR
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPC
r |
N_PORTS
r |
Host Controller Capability Parameters
Offset: 0x8, reset: 0x20006, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPMC
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Frame Length Adjustment
Offset: 0xc, reset: 0x20, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FRINDEX
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLADJ
rw |
Memory base address where ATL PTD0 is stored
Offset: 0x10, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATL_BASE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATL_BASE
rw |
ATL_CUR
rw |
Memory base address where ISO PTD0 is stored
Offset: 0x14, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ISO_BASE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISO_BASE
rw |
ISO_FIRST
rw |
Memory base address where INT PTD0 is stored
Offset: 0x18, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INT_BASE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_BASE
rw |
INT_FIRST
rw |
Memory base address that indicates the start of the data payload buffers
Offset: 0x1c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DAT_BASE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Port Status and Control register
Offset: 0x2c, reset: 0, access: read-write
1/18 fields covered.
Bit 9: Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume..
Bits 23-24: These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred..
Done map for each ATL PTD
Offset: 0x30, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATL_DONE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATL_DONE
rw |
Skip map for each ATL PTD
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATL_SKIP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATL_SKIP
rw |
Done map for each ISO PTD
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ISO_DONE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISO_DONE
rw |
Skip map for each ISO PTD
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ISO_SKIP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISO_SKIP
rw |
Done map for each INT PTD
Offset: 0x40, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INT_DONE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_DONE
rw |
Skip map for each INT PTD
Offset: 0x44, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INT_SKIP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_SKIP
rw |
Marks the last PTD in the list for ISO, INT and ATL
Offset: 0x48, reset: 0, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INT_LAST
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISO_LAST
rw |
ATL_LAST
rw |
Register to read/write registers in the attached USB PHY
Offset: 0x4c, reset: 0, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PHY_MODE
rw |
PHY_ACCESS
rw |
PHY_RW
rw |
PHY_RDATA
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_WDATA
rw |
PHY_ADDR
rw |
Controls the port if it is attached to the host block or the device block
Offset: 0x50, reset: 0x40000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SW_PDCOM
rw |
SW_CTRL_PDCOM
rw |
DEV_ENABLE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID0_EN
rw |
ID0
rw |
0x4000e000: LPC5411x Micro-tick Timer (UTICK)
8/24 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | STAT | ||||||||||||||||||||||||||||||||
0x8 | CFG | ||||||||||||||||||||||||||||||||
0xc | CAPCLR | ||||||||||||||||||||||||||||||||
0x10 | CAP[[0]] | ||||||||||||||||||||||||||||||||
0x14 | CAP[[1]] | ||||||||||||||||||||||||||||||||
0x18 | CAP[[2]] | ||||||||||||||||||||||||||||||||
0x1c | CAP[[3]] |
Control register.
Offset: 0x0, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REPEAT
rw |
DELAYVAL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DELAYVAL
rw |
Status register.
Offset: 0x4, reset: 0, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
rw |
INTR
rw |
Capture clear register.
Offset: 0xc, reset: 0, access: write-only
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPCLR3
w |
CAPCLR2
w |
CAPCLR1
w |
CAPCLR0
w |
Capture register .
Offset: 0x10, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALID
r |
CAP_VALUE
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP_VALUE
r |
Capture register .
Offset: 0x14, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALID
r |
CAP_VALUE
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP_VALUE
r |
Capture register .
Offset: 0x18, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALID
r |
CAP_VALUE
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP_VALUE
r |
Capture register .
Offset: 0x1c, reset: 0, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALID
r |
CAP_VALUE
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP_VALUE
r |
0x4000c000: LPC5411x Windowed Watchdog Timer (WWDT)
4/11 fields covered. Toggle Registers
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MOD | ||||||||||||||||||||||||||||||||
0x4 | TC | ||||||||||||||||||||||||||||||||
0x8 | FEED | ||||||||||||||||||||||||||||||||
0xc | TV | ||||||||||||||||||||||||||||||||
0x14 | WARNINT | ||||||||||||||||||||||||||||||||
0x18 | WINDOW |
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
Offset: 0x0, reset: 0, access: read-write
3/6 fields covered.
Bit 3: Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0..
Bit 4: Watchdog update mode. This bit can be set once by software and is only cleared by a reset..
Allowed values:
0: FLEXIBLE: Flexible. The watchdog time-out value (TC) can be changed at any time.
0x1: THRESHOLD: Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
Watchdog timer constant register. This 24-bit register determines the time-out value.
Offset: 0x4, reset: 0xFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COUNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT
rw |
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.
Offset: 0x8, reset: 0, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEED
w |
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
Offset: 0xc, reset: 0xFF, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COUNT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT
r |
Watchdog Warning Interrupt compare value.
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WARNINT
rw |
Watchdog Window compare value.
Offset: 0x18, reset: 0xFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WINDOW
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WINDOW
rw |