Overall: 562/1042 fields covered

ACOMP

0x40024000: analog comparator

6/11 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTRL
0x4 LAD

CTRL

Comparator control register

Offset: 0x0, reset: 0, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HYS
rw
COMPEDGE
rw
COMPSTAT
rw
EDGECLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_VM_SEL
rw
COMP_VP_SEL
rw
COMPSA
rw
EDGESEL
rw
Toggle Fields

EDGESEL

Bits 3-4: This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):.

Allowed values:
0: FALLING_EDGES: Falling edges
0x1: RISING_EDGES: Rising edges
0x2: BOTH_EDGES0: Both edges
0x3: BOTH_EDGES1: Both edges

COMPSA

Bit 6: Comparator output control.

Allowed values:
0: COMPSA_0: Comparator output is used directly.
0x1: COMPSA_1: Comparator output is synchronized to the bus clock for output to other modules.

COMP_VP_SEL

Bits 8-10: Selects positive voltage input.

Allowed values:
0: VOLTAGE_LADDER_OUTPUT: VOLTAGE_LADDER_OUTPUT
0x1: ACMP_I1: ACMP_I1
0x2: ACMP_I2: ACMP_I2
0x3: ACMP_I3: ACMP_I3
0x4: ACMP_I4: ACMP_I4
0x5: ACMP_I5: ACMP_I5
0x6: BAND_GAP: Band gap. Internal reference voltage.
0x7: DACOUT0: DAC0 output

COMP_VM_SEL

Bits 11-13: Selects negative voltage input.

Allowed values:
0: VOLTAGE_LADDER_OUTPUT: VOLTAGE_LADDER_OUTPUT
0x1: ACMP_I1: ACMP_I1
0x2: ACMP_I2: ACMP_I2
0x3: ACMP_I3: ACMP_I3
0x4: ACMP_I4: ACMP_I4
0x5: ACMP_I5: ACMP_I5
0x6: BAND_GAP: Band gap. Internal reference voltage.
0x7: DACOUT0: DAC0 output

EDGECLR

Bit 20: Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0..

COMPSTAT

Bit 21: Comparator status. This bit reflects the state of the comparator output..

COMPEDGE

Bit 23: Comparator edge-detect status..

HYS

Bits 25-26: Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output..

Allowed values:
0: HYS_0: None (the output will switch as the voltages cross)
0x1: HYS_1: 5 mv
0x2: HYS_2: 10 mv
0x3: HYS_3: 20 mv

LAD

Voltage ladder register

Offset: 0x4, reset: 0, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LADREF
rw
LADSEL
rw
LADEN
rw
Toggle Fields

LADEN

Bit 0: Voltage ladder enable.

LADSEL

Bits 1-5: Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref.

LADREF

Bit 6: Selects the reference voltage Vref for the voltage ladder..

Allowed values:
0: LADREF_0: Supply pin VDD
0x1: LADREF_1: VDDCMP pin

CRC

0x50000000: LPC5411x CRC engine

1/8 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODE
0x4 SEED
0x8 SUM
0x8 WR_DATA

MODE

CRC mode register

Offset: 0x0, reset: 0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPL_SUM
rw
BIT_RVS_SUM
rw
CMPL_WR
rw
BIT_RVS_WR
rw
CRC_POLY
rw
Toggle Fields

CRC_POLY

Bits 0-1: CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial.

BIT_RVS_WR

Bit 2: Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte).

CMPL_WR

Bit 3: Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA.

BIT_RVS_SUM

Bit 4: CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM.

CMPL_SUM

Bit 5: CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM.

SEED

CRC seed register

Offset: 0x4, reset: 0xFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_SEED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_SEED
rw
Toggle Fields

CRC_SEED

Bits 0-31: A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses..

SUM

CRC checksum register

Offset: 0x8, reset: 0xFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_SUM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_SUM
r
Toggle Fields

CRC_SUM

Bits 0-31: The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes..

WR_DATA

CRC data register

Offset: 0x8, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_WR_DATA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_WR_DATA
w
Toggle Fields

CRC_WR_DATA

Bits 0-31: Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions..

FLASH_CTRL

0x40040000: NVMC flash controller

2/5 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x10 FLASHCFG
0x20 FMSSTART
0x24 FMSSTOP
0x2c FMSW0

FLASHCFG

Flash configuration register

Offset: 0x10, reset: 0x2, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHTIM
rw
Toggle Fields

FLASHTIM

Bits 0-1: Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access..

Allowed values:
0: ONE_SYSTEM_CLOCK_FLASH_ACCESS: 1 system clock flash access time.
0x1: TWO_SYSTEM_CLOCK_FLASH_ACCESS: 2 system clock flash access time.
0x2: THREE_SYSTEM_CLOCK_FLASH_ACCESS: 3 system clock flash access time.

FMSSTART

Flash signature start address register

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
START
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START
rw
Toggle Fields

START

Bits 0-16: Signature generation start address (corresponds to AHB byte address bits[18:2])..

FMSSTOP

Flash signaure stop address register

Offset: 0x24, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STRTBIST
rw
STOPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPA
rw
Toggle Fields

STOPA

Bits 0-16: Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes..

STRTBIST

Bit 31: When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared..

FMSW0

Flash signature generation result register returns the flash signature produced by the embedded signature generator..

Offset: 0x2c, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIG
r
Toggle Fields

SIG

Bits 0-31: 32-bit signature..

GPIO

0xa0000000: General Purpose I/O (GPIO)

0/43 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 B0_0
0x1 B0_1
0x2 B0_2
0x3 B0_3
0x4 B0_4
0x5 B0_5
0x6 B0_6
0x7 B0_7
0x8 B0_8
0x9 B0_9
0xa B0_10
0xb B0_11
0xc B0_12
0xd B0_13
0xe B0_14
0xf B0_15
0x10 B0_16
0x11 B0_17
0x1000 W0_0
0x1004 W0_1
0x1008 W0_2
0x100c W0_3
0x1010 W0_4
0x1014 W0_5
0x1018 W0_6
0x101c W0_7
0x1020 W0_8
0x1024 W0_9
0x1028 W0_10
0x102c W0_11
0x1030 W0_12
0x1034 W0_13
0x1038 W0_14
0x103c W0_15
0x1040 W0_16
0x1044 W0_17
0x2000 DIR0
0x2080 MASK0
0x2100 PIN0
0x2180 MPIN0
0x2200 SET0
0x2280 CLR0
0x2300 NOT0

B0_0

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x0, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_1

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x1, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_2

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x2, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_3

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x3, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_4

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x4, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_5

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x5, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_6

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x6, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_7

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x7, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_8

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_9

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x9, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_10

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xa, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_11

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xb, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_12

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xc, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_13

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xd, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_14

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xe, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_15

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0xf, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_16

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

B0_17

Byte pin registers for all port 0 and 1 GPIO pins

Offset: 0x11, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBYTE
rw
Toggle Fields

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_0

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1000, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_1

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1004, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_2

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1008, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_3

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x100c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_4

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1010, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_5

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1014, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_6

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1018, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_7

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x101c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_8

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1020, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_9

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1024, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_10

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1028, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_11

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x102c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_12

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1030, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_13

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1034, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_14

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1038, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_15

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x103c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_16

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1040, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

W0_17

Word pin registers for all port 0 and 1 GPIO pins

Offset: 0x1044, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWORD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWORD
rw
Toggle Fields

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

DIR0

Direction registers

Offset: 0x2000, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRP
rw
Toggle Fields

DIRP

Bits 0-17: Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output..

MASK0

Mask register

Offset: 0x2080, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASKP
rw
Toggle Fields

MASKP

Bits 0-17: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..

PIN0

Port pin register

Offset: 0x2100, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PORT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT
rw
Toggle Fields

PORT

Bits 0-17: Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit..

MPIN0

Masked port register

Offset: 0x2180, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MPORTP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPORTP
rw
Toggle Fields

MPORTP

Bits 0-17: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..

SET0

Write: Set register for port Read: output bits for port

Offset: 0x2200, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETP
rw
Toggle Fields

SETP

Bits 0-17: Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit..

CLR0

Clear port

Offset: 0x2280, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRP
w
Toggle Fields

CLRP

Bits 0-17: Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit..

NOT0

Toggle port

Offset: 0x2300, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOTP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTP
w
Toggle Fields

NOTP

Bits 0-17: Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit..

I2C0

0x40050000: I2C-bus interfaces

59/80 fields covered. Toggle Registers

Show register map

CFG

Configuration for shared functions.

Offset: 0x0, reset: 0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONCLKSTR
rw
TIMEOUTEN
rw
MONEN
rw
SLVEN
rw
MSTEN
rw
Toggle Fields

MSTEN

Bit 0: Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C Master function is disabled.
0x1: ENABLED: Enabled. The I2C Master function is enabled.

SLVEN

Bit 1: Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C slave function is disabled.
0x1: ENABLED: Enabled. The I2C slave function is enabled.

MONEN

Bit 2: Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C Monitor function is disabled.
0x1: ENABLED: Enabled. The I2C Monitor function is enabled.

TIMEOUTEN

Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..

Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.

MONCLKSTR

Bit 4: Monitor function Clock Stretching..

Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.

STAT

Status register for Master, Slave, and Monitor functions.

Offset: 0x4, reset: 0x801, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCLTIMEOUT
rw
EVENTTIMEOUT
rw
MONIDLE
rw
MONACTIVE
r
MONOV
rw
MONRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVDESEL
rw
SLVSEL
r
SLVIDX
r
SLVNOTSTR
r
SLVSTATE
r
SLVPENDING
r
MSTSTSTPERR
rw
MSTARBLOSS
rw
MSTSTATE
r
MSTPENDING
r
Toggle Fields

MSTPENDING

Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..

Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.

MSTSTATE

Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..

Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.

MSTARBLOSS

Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..

Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.

MSTSTSTPERR

Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..

Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.

SLVPENDING

Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..

Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.

SLVSTATE

Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..

Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).

SLVNOTSTR

Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..

Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.

SLVIDX

Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..

Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.

SLVSEL

Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..

Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.

SLVDESEL

Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..

Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.

MONRDY

Bit 16: Monitor Ready. This flag is cleared when the MONRXDAT register is read..

Allowed values:
0: NO_DATA: No data. The Monitor function does not currently have data available.
0x1: DATA_WAITING: Data waiting. The Monitor function has data waiting to be read.

MONOV

Bit 17: Monitor Overflow flag..

Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.

MONACTIVE

Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..

Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.

MONIDLE

Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..

Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.

EVENTTIMEOUT

Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..

Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.

SCLTIMEOUT

Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..

Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.

INTENSET

Interrupt Enable Set and read register.

Offset: 0x8, reset: 0, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCLTIMEOUTEN
rw
EVENTTIMEOUTEN
rw
MONIDLEEN
rw
MONOVEN
rw
MONRDYEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVDESELEN
rw
SLVNOTSTREN
rw
SLVPENDINGEN
rw
MSTSTSTPERREN
rw
MSTARBLOSSEN
rw
MSTPENDINGEN
rw
Toggle Fields

MSTPENDINGEN

Bit 0: Master Pending interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstPending interrupt is disabled.
0x1: ENABLED: Enabled. The MstPending interrupt is enabled.

MSTARBLOSSEN

Bit 4: Master Arbitration Loss interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstArbLoss interrupt is disabled.
0x1: ENABLED: Enabled. The MstArbLoss interrupt is enabled.

MSTSTSTPERREN

Bit 6: Master Start/Stop Error interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstStStpErr interrupt is disabled.
0x1: ENABLED: Enabled. The MstStStpErr interrupt is enabled.

SLVPENDINGEN

Bit 8: Slave Pending interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvPending interrupt is disabled.
0x1: ENABLED: Enabled. The SlvPending interrupt is enabled.

SLVNOTSTREN

Bit 11: Slave Not Stretching interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvNotStr interrupt is disabled.
0x1: ENABLED: Enabled. The SlvNotStr interrupt is enabled.

SLVDESELEN

Bit 15: Slave Deselect interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvDeSel interrupt is disabled.
0x1: ENABLED: Enabled. The SlvDeSel interrupt is enabled.

MONRDYEN

Bit 16: Monitor data Ready interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonRdy interrupt is disabled.
0x1: ENABLED: Enabled. The MonRdy interrupt is enabled.

MONOVEN

Bit 17: Monitor Overrun interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonOv interrupt is disabled.
0x1: ENABLED: Enabled. The MonOv interrupt is enabled.

MONIDLEEN

Bit 19: Monitor Idle interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonIdle interrupt is disabled.
0x1: ENABLED: Enabled. The MonIdle interrupt is enabled.

EVENTTIMEOUTEN

Bit 24: Event time-out interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The Event time-out interrupt is disabled.
0x1: ENABLED: Enabled. The Event time-out interrupt is enabled.

SCLTIMEOUTEN

Bit 25: SCL time-out interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SCL time-out interrupt is disabled.
0x1: ENABLED: Enabled. The SCL time-out interrupt is enabled.

INTENCLR

Interrupt Enable Clear register.

Offset: 0xc, reset: 0, access: write-only

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCLTIMEOUTCLR
w
EVENTTIMEOUTCLR
w
MONIDLECLR
w
MONOVCLR
w
MONRDYCLR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVDESELCLR
w
SLVNOTSTRCLR
w
SLVPENDINGCLR
w
MSTSTSTPERRCLR
w
MSTARBLOSSCLR
w
MSTPENDINGCLR
w
Toggle Fields

MSTPENDINGCLR

Bit 0: Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented..

MSTARBLOSSCLR

Bit 4: Master Arbitration Loss interrupt clear..

MSTSTSTPERRCLR

Bit 6: Master Start/Stop Error interrupt clear..

SLVPENDINGCLR

Bit 8: Slave Pending interrupt clear..

SLVNOTSTRCLR

Bit 11: Slave Not Stretching interrupt clear..

SLVDESELCLR

Bit 15: Slave Deselect interrupt clear..

MONRDYCLR

Bit 16: Monitor data Ready interrupt clear..

MONOVCLR

Bit 17: Monitor Overrun interrupt clear..

MONIDLECLR

Bit 19: Monitor Idle interrupt clear..

EVENTTIMEOUTCLR

Bit 24: Event time-out interrupt clear..

SCLTIMEOUTCLR

Bit 25: SCL time-out interrupt clear..

TIMEOUT

Time-out value register.

Offset: 0x10, reset: 0xFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
TOMIN
rw
Toggle Fields

TOMIN

Bits 0-3: Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks..

TO

Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..

CLKDIV

Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.

Offset: 0x14, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVVAL
rw
Toggle Fields

DIVVAL

Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..

INTSTAT

Interrupt Status register for Master, Slave, and Monitor functions.

Offset: 0x18, reset: 0x801, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCLTIMEOUT
r
EVENTTIMEOUT
r
MONIDLE
r
MONOV
r
MONRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVDESEL
r
SLVNOTSTR
r
SLVPENDING
r
MSTSTSTPERR
r
MSTARBLOSS
r
MSTPENDING
r
Toggle Fields

MSTPENDING

Bit 0: Master Pending..

MSTARBLOSS

Bit 4: Master Arbitration Loss flag..

MSTSTSTPERR

Bit 6: Master Start/Stop Error flag..

SLVPENDING

Bit 8: Slave Pending..

SLVNOTSTR

Bit 11: Slave Not Stretching status..

SLVDESEL

Bit 15: Slave Deselected flag..

MONRDY

Bit 16: Monitor Ready..

MONOV

Bit 17: Monitor Overflow flag..

MONIDLE

Bit 19: Monitor Idle flag..

EVENTTIMEOUT

Bit 24: Event time-out Interrupt flag..

SCLTIMEOUT

Bit 25: SCL time-out Interrupt flag..

MSTCTL

Master control register.

Offset: 0x20, reset: 0, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSTSTOP
rw
MSTSTART
rw
MSTCONTINUE
rw
Toggle Fields

MSTCONTINUE

Bit 0: Master Continue..

Allowed values:
0: NO_EFFECT: No effect.
0x1: Continue: Informs the Master function to continue to the next operation.

MSTSTART

Bit 1: Master Start control..

Allowed values:
0: NO_EFFECT: No effect.
0x1: START: Start. A Start will be generated on the I2C bus at the next allowed time.

MSTSTOP

Bit 2: Master Stop control..

Allowed values:
0: NO_EFFECT: No effect.
0x1: STOP: Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).

MSTTIME

Master timing configuration.

Offset: 0x24, reset: 0x77, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSTSCLHIGH
rw
MSTSCLLOW
rw
Toggle Fields

MSTSCLLOW

Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..

Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.

MSTSCLHIGH

Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..

Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.

MSTDAT

Combined Master receiver and transmitter data register.

Offset: 0x28, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-7: Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function..

SLVCTL

Slave control register.

Offset: 0x40, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVNACK
rw
SLVCONTINUE
rw
Toggle Fields

SLVCONTINUE

Bit 0: Slave Continue..

Allowed values:
0: NO_EFFECT: No effect.
0x1: Continue: Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.

SLVNACK

Bit 1: Slave NACK..

Allowed values:
0: NO_EFFECT: No effect.
0x1: NACK: NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).

SLVDAT

Combined Slave receiver and transmitter data register.

Offset: 0x44, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-7: Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function..

SLVADR[[0]]

Slave address register.

Offset: 0x48, reset: 0x1, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVADR
rw
SADISABLE
rw
Toggle Fields

SADISABLE

Bit 0: Slave Address n Disable..

Allowed values:
0: ENABLED: Enabled. Slave Address n is enabled.
0x1: DISABLED: Ignored Slave Address n is ignored.

SLVADR

Bits 1-7: Slave Address. Seven bit slave address that is compared to received addresses if enabled..

SLVADR[[1]]

Slave address register.

Offset: 0x4c, reset: 0x1, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVADR
rw
SADISABLE
rw
Toggle Fields

SADISABLE

Bit 0: Slave Address n Disable..

Allowed values:
0: ENABLED: Enabled. Slave Address n is enabled.
0x1: DISABLED: Ignored Slave Address n is ignored.

SLVADR

Bits 1-7: Slave Address. Seven bit slave address that is compared to received addresses if enabled..

SLVADR[[2]]

Slave address register.

Offset: 0x50, reset: 0x1, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVADR
rw
SADISABLE
rw
Toggle Fields

SADISABLE

Bit 0: Slave Address n Disable..

Allowed values:
0: ENABLED: Enabled. Slave Address n is enabled.
0x1: DISABLED: Ignored Slave Address n is ignored.

SLVADR

Bits 1-7: Slave Address. Seven bit slave address that is compared to received addresses if enabled..

SLVADR[[3]]

Slave address register.

Offset: 0x54, reset: 0x1, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVADR
rw
SADISABLE
rw
Toggle Fields

SADISABLE

Bit 0: Slave Address n Disable..

Allowed values:
0: ENABLED: Enabled. Slave Address n is enabled.
0x1: DISABLED: Ignored Slave Address n is ignored.

SLVADR

Bits 1-7: Slave Address. Seven bit slave address that is compared to received addresses if enabled..

SLVQUAL0

Slave Qualification for address 0.

Offset: 0x58, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLVQUAL0
rw
QUALMODE0
rw
Toggle Fields

QUALMODE0

Bit 0: Qualify mode for slave address 0..

Allowed values:
0: MASK: Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
0x1: EXTEND: Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.

SLVQUAL0

Bits 1-7: Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1])..

MONRXDAT

Monitor receiver data register.

Offset: 0x80, reset: 0, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONNACK
r
MONRESTART
r
MONSTART
r
MONRXDAT
r
Toggle Fields

MONRXDAT

Bits 0-7: Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins..

MONSTART

Bit 8: Monitor Received Start..

Allowed values:
0: NO_START_DETECTED: No start detected. The Monitor function has not detected a Start event on the I2C bus.
0x1: START_DETECTED: Start detected. The Monitor function has detected a Start event on the I2C bus.

MONRESTART

Bit 9: Monitor Received Repeated Start..

Allowed values:
0: NOT_DETECTED: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1: DETECTED: Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.

MONNACK

Bit 10: Monitor Received NACK..

Allowed values:
0: ACKNOWLEDGED: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1: NOT_ACKNOWLEDGED: Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.

IOCON

0x40044000: I/O pin configuration (IOCON)

104/104 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PIO0_17
0x4 PIO0_13
0x8 PIO0_12
0xc PIO0_5
0x10 PIO0_4
0x14 PIO0_3
0x18 PIO0_2
0x1c PIO0_11
0x20 PIO0_10
0x24 PIO0_16
0x28 PIO0_15
0x2c PIO0_1
0x34 PIO0_9
0x38 PIO0_8
0x3c PIO0_7
0x40 PIO0_6
0x44 PIO0_0
0x48 PIO0_14

PIO0_17

Digital I/O control for pins PIO0_17

Offset: 0x0, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_13

Digital I/O control for pins PIO0_13

Offset: 0x4, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_12

Digital I/O control for pins PIO0_12

Offset: 0x8, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_5

Digital I/O control for pins PIO0_5

Offset: 0xc, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_4

Digital I/O control for pins PIO0_4

Offset: 0x10, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_3

Digital I/O control for pins PIO0_3

Offset: 0x14, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_2

Digital I/O control for pins PIO0_2

Offset: 0x18, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_11

Digital I/O control for pins PIO0_11

Offset: 0x1c, reset: 0x80, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
I2CMODE
rw
INV
rw
Toggle Fields

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

I2CMODE

Bits 8-9: Selects I2C mode..

Allowed values:
0: STANDARAD_I2C: Standard mode/ Fast-mode I2C.
0x1: Standard_GPIO: Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2: FAST_PLUS_I2C: Fast-mode Plus I2C

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_10

Digital I/O control for pins PIO0_10

Offset: 0x20, reset: 0x80, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
I2CMODE
rw
INV
rw
Toggle Fields

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

I2CMODE

Bits 8-9: Selects I2C mode..

Allowed values:
0: STANDARAD_I2C: Standard mode/ Fast-mode I2C.
0x1: Standard_GPIO: Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2: FAST_PLUS_I2C: Fast-mode Plus I2C

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_16

Digital I/O control for pins PIO0_16

Offset: 0x24, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_15

Digital I/O control for pins PIO0_15

Offset: 0x28, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_1

Digital I/O control for pins PIO0_1

Offset: 0x2c, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_9

Digital I/O control for pins PIO0_9

Offset: 0x34, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_8

Digital I/O control for pins PIO0_8

Offset: 0x38, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_7

Digital I/O control for pins PIO0_7

Offset: 0x3c, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_6

Digital I/O control for pins PIO0_6

Offset: 0x40, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_0

Digital I/O control for pins PIO0_0

Offset: 0x44, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

PIO0_14

Digital I/O control for pins PIO0_14

Offset: 0x48, reset: 0x90, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_DIV
rw
S_MODE
rw
OD
rw
INV
rw
HYS
rw
MODE
rw
Toggle Fields

MODE

Bits 3-4: Selects function mode (on-chip pull-up/pull-down resistor control)..

Allowed values:
0: INACTIVE: Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1: PULL_DOWN: Pull-down. Pull-down resistor enabled.
0x2: PULL_UP: Pull-up. Pull-up resistor enabled.
0x3: REPEATER: Repeater. Repeater mode.

HYS

Bit 5: Hysteresis..

Allowed values:
0: DISABLE: Disable
0x1: ENABLE: Enable

INV

Bit 6: Invert input.

Allowed values:
0: NOT_INVERTED: Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1: INVERTED: Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

OD

Bit 10: Open-drain mode..

Allowed values:
0: DISABLE: Disable.
0x1: ENABLED: Open-drain mode enabled. Remark: This is not a true open-drain mode.

S_MODE

Bits 11-12: Digital filter sample mode..

Allowed values:
0: S_MODE_0: Bypass input filter.
0x1: S_MODE_1: 1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2: S_MODE_2: 2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3: S_MODE_3: 3 clock cycles. Input pulses shorter than three filter clocks are rejected.

CLK_DIV

Bits 13-15: Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved..

Allowed values:
0: CLK_DIV_0: IOCONCLKDIV0
0x1: CLK_DIV_1: IOCONCLKDIV1
0x2: CLK_DIV_2: IOCONCLKDIV2
0x3: CLK_DIV_3: IOCONCLKDIV3
0x4: CLK_DIV_4: IOCONCLKDIV4
0x5: CLK_DIV_5: IOCONCLKDIV5
0x6: CLK_DIV_6: IOCONCLKDIV6

MRT0

0x40004000: Multi-Rate Timer (MRT)

28/35 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 INTVAL [0]
0x4 TIMER [0]
0x8 CTRL [0]
0xc STAT [0]
0x10 INTVAL [1]
0x14 TIMER [1]
0x18 CTRL [1]
0x1c STAT [1]
0x20 INTVAL [2]
0x24 TIMER [2]
0x28 CTRL [2]
0x2c STAT [2]
0x30 INTVAL [3]
0x34 TIMER [3]
0x38 CTRL [3]
0x3c STAT [3]
0xf0 MODCFG
0xf4 IDLE_CH
0xf8 IRQ_FLAG

INTVAL [0]

MRT Time interval value register. This value is loaded into the TIMER register.

Offset: 0x0, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOAD
rw
IVALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVALUE
rw
Toggle Fields

IVALUE

Bits 0-30: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..

LOAD

Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..

Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.

TIMER [0]

MRT Timer register. This register reads the value of the down-counter.

Offset: 0x4, reset: 0xFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
r
Toggle Fields

VALUE

Bits 0-30: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..

CTRL [0]

MRT Control register. This register controls the MRT modes.

Offset: 0x8, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
INTEN
rw
Toggle Fields

INTEN

Bit 0: Enable the TIMERn interrupt..

Allowed values:
0: DISABLED: Disabled. TIMERn interrupt is disabled.
0x1: ENABLED: Enabled. TIMERn interrupt is enabled.

MODE

Bits 1-2: Selects timer mode..

Allowed values:
0: REPEAT_INTERRUPT_MODE: Repeat interrupt mode.
0x1: ONE_SHOT_INTERRUPT_MODE: One-shot interrupt mode.
0x2: ONE_SHOT_STALL_MODE: One-shot stall mode.

STAT [0]

MRT Status register.

Offset: 0xc, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN
rw
INTFLAG
rw
Toggle Fields

INTFLAG

Bit 0: Monitors the interrupt flag..

Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

RUN

Bit 1: Indicates the state of TIMERn. This bit is read-only..

Allowed values:
0: IDLE_STATE: Idle state. TIMERn is stopped.
0x1: RUNNING: Running. TIMERn is running.

INTVAL [1]

MRT Time interval value register. This value is loaded into the TIMER register.

Offset: 0x10, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOAD
rw
IVALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVALUE
rw
Toggle Fields

IVALUE

Bits 0-30: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..

LOAD

Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..

Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.

TIMER [1]

MRT Timer register. This register reads the value of the down-counter.

Offset: 0x14, reset: 0xFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
r
Toggle Fields

VALUE

Bits 0-30: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..

CTRL [1]

MRT Control register. This register controls the MRT modes.

Offset: 0x18, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
INTEN
rw
Toggle Fields

INTEN

Bit 0: Enable the TIMERn interrupt..

Allowed values:
0: DISABLED: Disabled. TIMERn interrupt is disabled.
0x1: ENABLED: Enabled. TIMERn interrupt is enabled.

MODE

Bits 1-2: Selects timer mode..

Allowed values:
0: REPEAT_INTERRUPT_MODE: Repeat interrupt mode.
0x1: ONE_SHOT_INTERRUPT_MODE: One-shot interrupt mode.
0x2: ONE_SHOT_STALL_MODE: One-shot stall mode.

STAT [1]

MRT Status register.

Offset: 0x1c, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN
rw
INTFLAG
rw
Toggle Fields

INTFLAG

Bit 0: Monitors the interrupt flag..

Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

RUN

Bit 1: Indicates the state of TIMERn. This bit is read-only..

Allowed values:
0: IDLE_STATE: Idle state. TIMERn is stopped.
0x1: RUNNING: Running. TIMERn is running.

INTVAL [2]

MRT Time interval value register. This value is loaded into the TIMER register.

Offset: 0x20, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOAD
rw
IVALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVALUE
rw
Toggle Fields

IVALUE

Bits 0-30: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..

LOAD

Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..

Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.

TIMER [2]

MRT Timer register. This register reads the value of the down-counter.

Offset: 0x24, reset: 0xFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
r
Toggle Fields

VALUE

Bits 0-30: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..

CTRL [2]

MRT Control register. This register controls the MRT modes.

Offset: 0x28, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
INTEN
rw
Toggle Fields

INTEN

Bit 0: Enable the TIMERn interrupt..

Allowed values:
0: DISABLED: Disabled. TIMERn interrupt is disabled.
0x1: ENABLED: Enabled. TIMERn interrupt is enabled.

MODE

Bits 1-2: Selects timer mode..

Allowed values:
0: REPEAT_INTERRUPT_MODE: Repeat interrupt mode.
0x1: ONE_SHOT_INTERRUPT_MODE: One-shot interrupt mode.
0x2: ONE_SHOT_STALL_MODE: One-shot stall mode.

STAT [2]

MRT Status register.

Offset: 0x2c, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN
rw
INTFLAG
rw
Toggle Fields

INTFLAG

Bit 0: Monitors the interrupt flag..

Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

RUN

Bit 1: Indicates the state of TIMERn. This bit is read-only..

Allowed values:
0: IDLE_STATE: Idle state. TIMERn is stopped.
0x1: RUNNING: Running. TIMERn is running.

INTVAL [3]

MRT Time interval value register. This value is loaded into the TIMER register.

Offset: 0x30, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOAD
rw
IVALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVALUE
rw
Toggle Fields

IVALUE

Bits 0-30: Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval..

LOAD

Bit 31: Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0..

Allowed values:
0: NO_FORCE_LOAD: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1: FORCE_LOAD: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.

TIMER [3]

MRT Timer register. This register reads the value of the down-counter.

Offset: 0x34, reset: 0xFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
r
Toggle Fields

VALUE

Bits 0-30: Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF)..

CTRL [3]

MRT Control register. This register controls the MRT modes.

Offset: 0x38, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
INTEN
rw
Toggle Fields

INTEN

Bit 0: Enable the TIMERn interrupt..

Allowed values:
0: DISABLED: Disabled. TIMERn interrupt is disabled.
0x1: ENABLED: Enabled. TIMERn interrupt is enabled.

MODE

Bits 1-2: Selects timer mode..

Allowed values:
0: REPEAT_INTERRUPT_MODE: Repeat interrupt mode.
0x1: ONE_SHOT_INTERRUPT_MODE: One-shot interrupt mode.
0x2: ONE_SHOT_STALL_MODE: One-shot stall mode.

STAT [3]

MRT Status register.

Offset: 0x3c, reset: 0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN
rw
INTFLAG
rw
Toggle Fields

INTFLAG

Bit 0: Monitors the interrupt flag..

Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

RUN

Bit 1: Indicates the state of TIMERn. This bit is read-only..

Allowed values:
0: IDLE_STATE: Idle state. TIMERn is stopped.
0x1: RUNNING: Running. TIMERn is running.

MODCFG

Module Configuration register. This register provides information about this particular MRT instance.

Offset: 0xf0, reset: 0x1F4, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOB
r
NOC
r
Toggle Fields

NOC

Bits 0-3: Identifies the number of channels in this MRT.(4 channels on this device.).

NOB

Bits 4-8: Identifies the number of timer bits in this MRT. (31 bits wide on this device.).

IDLE_CH

Idle channel register. This register returns the number of the first idle channel.

Offset: 0xf4, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHAN
r
Toggle Fields

CHAN

Bits 4-7: Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details..

IRQ_FLAG

Global interrupt flag register

Offset: 0xf8, reset: 0, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GFLAG3
rw
GFLAG2
rw
GFLAG1
rw
GFLAG0
rw
Toggle Fields

GFLAG0

Bit 0: Monitors the interrupt flag of TIMER0..

Allowed values:
0: NO_PENDING_INTERRUPT: No pending interrupt. Writing a zero is equivalent to no operation.
0x1: PENDING_INTERRUPT: Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

GFLAG1

Bit 1: Monitors the interrupt flag of TIMER1. See description of channel 0..

GFLAG2

Bit 2: Monitors the interrupt flag of TIMER2. See description of channel 0..

GFLAG3

Bit 3: Monitors the interrupt flag of TIMER3. See description of channel 0..

MTB

0x14000000: Micro Trace Buffer

1/13 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POSITION
0x4 MASTER
0x8 FLOW
0xc BASE

POSITION

POSITION Register

Offset: 0x0, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POINTER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POINTER
rw
WRAP
rw
Toggle Fields

WRAP

Bit 2: This bit is set to 1 automatically when the POINTER value wraps as determined by the MASTER.MASK field in the MASTER Trace Control Register..

POINTER

Bits 3-31: Trace packet location pointer. Because a packet consists of two words, the POINTER field is the location of the first word of a packet. This field contains bits [31:3] of the address, in the SRAM, where the next trace packet will be written. The field points to an unused location and is automatically incremented. A debug agent can calculate the system address, on the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P = POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value.

MASTER

MASTER Register

Offset: 0x4, reset: 0x80, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTREQ
rw
RAMPRIV
rw
SFRWPRIV
rw
TSTOPEN
rw
TSTARTEN
rw
MASK
rw
Toggle Fields

MASK

Bits 0-4: This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum..

TSTARTEN

Bit 5: Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs..

TSTOPEN

Bit 6: Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped..

SFRWPRIV

Bit 7: Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT[1] signal determines if an access is User or Privileged..

RAMPRIV

Bit 8: SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal determines if an access is User or Privileged..

HALTREQ

Bit 9: Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field..

EN

Bit 31: Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH..

FLOW

FLOW Register

Offset: 0x8, reset: 0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WATERMARK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WATERMARK
rw
AUTOHALT
rw
AUTOSTOP
rw
Toggle Fields

AUTOSTOP

Bit 0: If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit is automatically set to 0. This stops tracing..

AUTOHALT

Bit 1: If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal..

WATERMARK

Bits 3-31: WATERMARK value. This field contains an address in the same format as the POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed..

BASE

Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent.

Offset: 0xc, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE
r
Toggle Fields

BASE

Bits 0-31: The value provided is the value of the SRAMBASEADDR[31:0] signal..

PINT

0xa0004000: Pin interrupt and pattern match (PINT)

25/36 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISEL
0x4 IENR
0x8 SIENR
0xc CIENR
0x10 IENF
0x14 SIENF
0x18 CIENF
0x1c RISE
0x20 FALL
0x24 IST
0x28 PMCTRL
0x2c PMSRC
0x30 PMCFG

ISEL

Pin Interrupt Mode register

Offset: 0x0, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMODE
rw
Toggle Fields

PMODE

Bits 0-7: Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive.

IENR

Pin interrupt level or rising edge interrupt enable register

Offset: 0x4, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENRL
rw
Toggle Fields

ENRL

Bits 0-7: Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt..

SIENR

Pin interrupt level or rising edge interrupt set register

Offset: 0x8, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENRL
w
Toggle Fields

SETENRL

Bits 0-7: Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt..

CIENR

Pin interrupt level (rising edge interrupt) clear register

Offset: 0xc, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CENRL
w
Toggle Fields

CENRL

Bits 0-7: Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt..

IENF

Pin interrupt active level or falling edge interrupt enable register

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENAF
rw
Toggle Fields

ENAF

Bits 0-7: Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH..

SIENF

Pin interrupt active level or falling edge interrupt set register

Offset: 0x14, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENAF
w
Toggle Fields

SETENAF

Bits 0-7: Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt..

CIENF

Pin interrupt active level or falling edge interrupt clear register

Offset: 0x18, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CENAF
w
Toggle Fields

CENAF

Bits 0-7: Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled..

RISE

Pin interrupt rising edge register

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDET
rw
Toggle Fields

RDET

Bits 0-7: Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin..

FALL

Pin interrupt falling edge register

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDET
rw
Toggle Fields

FDET

Bits 0-7: Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin..

IST

Pin interrupt status register

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSTAT
rw
Toggle Fields

PSTAT

Bits 0-7: Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)..

PMCTRL

Pattern match interrupt control register

Offset: 0x28, reset: 0, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PMAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA_RXEV
rw
SEL_PMATCH
rw
Toggle Fields

SEL_PMATCH

Bit 0: Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function..

Allowed values:
0: PIN_INTERRUPT: Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
0x1: PATTERN_MATCH: Pattern match. Interrupts are driven in response to pattern matches.

ENA_RXEV

Bit 1: Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true..

Allowed values:
0: DISABLED: Disabled. RXEV output to the CPU is disabled.
0x1: ENABLED: Enabled. RXEV output to the CPU is enabled.

PMAT

Bits 24-31: This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs..

PMSRC

Pattern match interrupt bit-slice source register

Offset: 0x2c, reset: 0, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC7
rw
SRC6
rw
SRC5
rw
SRC4
rw
SRC3
rw
SRC2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC2
rw
SRC1
rw
SRC0
rw
Toggle Fields

SRC0

Bits 8-10: Selects the input source for bit slice 0.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.

SRC1

Bits 11-13: Selects the input source for bit slice 1.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.

SRC2

Bits 14-16: Selects the input source for bit slice 2.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.

SRC3

Bits 17-19: Selects the input source for bit slice 3.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.

SRC4

Bits 20-22: Selects the input source for bit slice 4.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.

SRC5

Bits 23-25: Selects the input source for bit slice 5.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.

SRC6

Bits 26-28: Selects the input source for bit slice 6.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.

SRC7

Bits 29-31: Selects the input source for bit slice 7.

Allowed values:
0: INPUT0: Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
0x1: INPUT1: Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
0x2: INPUT2: Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
0x3: INPUT3: Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
0x4: INPUT4: Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
0x5: INPUT5: Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
0x6: INPUT6: Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
0x7: INPUT7: Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.

PMCFG

Pattern match interrupt bit slice configuration register

Offset: 0x30, reset: 0, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG7
rw
CFG6
rw
CFG5
rw
CFG4
rw
CFG3
rw
CFG2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
rw
CFG1
rw
CFG0
rw
PROD_ENDPTS6
rw
PROD_ENDPTS5
rw
PROD_ENDPTS4
rw
PROD_ENDPTS3
rw
PROD_ENDPTS2
rw
PROD_ENDPTS1
rw
PROD_ENDPTS0
rw
Toggle Fields

PROD_ENDPTS0

Bit 0: Determines whether slice 0 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 0 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS1

Bit 1: Determines whether slice 1 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 1 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS2

Bit 2: Determines whether slice 2 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 2 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS3

Bit 3: Determines whether slice 3 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 3 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS4

Bit 4: Determines whether slice 4 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 4 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS5

Bit 5: Determines whether slice 5 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 5 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.

PROD_ENDPTS6

Bit 6: Determines whether slice 6 is an endpoint..

Allowed values:
0: NO_EFFECT: No effect. Slice 6 is not an endpoint.
0x1: ENDPOINT: endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.

CFG0

Bits 8-10: Specifies the match contribution condition for bit slice 0..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG1

Bits 11-13: Specifies the match contribution condition for bit slice 1..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG2

Bits 14-16: Specifies the match contribution condition for bit slice 2..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG3

Bits 17-19: Specifies the match contribution condition for bit slice 3..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG4

Bits 20-22: Specifies the match contribution condition for bit slice 4..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG5

Bits 23-25: Specifies the match contribution condition for bit slice 5..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG6

Bits 26-28: Specifies the match contribution condition for bit slice 6..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

CFG7

Bits 29-31: Specifies the match contribution condition for bit slice 7..

Allowed values:
0: CONSTANT_HIGH: Constant HIGH. This bit slice always contributes to a product term match.
0x1: STICKY_RISING_EDGE: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2: STICKY_FALLING_EDGE: Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3: STICKY_RISING_FALLING_EDGE: Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x4: HIGH_LEVEL: High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5: LOW_LEVEL: Low level. Match occurs when there is a low level on the specified input.
0x6: CONSTANT_ZERO: Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x7: EVENT: Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.

PMU

0x40020000: PMU

7/13 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PCON
0x4 GPREG[[0]]
0x8 GPREG[[1]]
0xc GPREG[[2]]
0x10 GPREG[[3]]
0x14 DPDCTRL

PCON

Power control register

Offset: 0x0, reset: 0, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPDFLAG
rw
SLEEPFLAG
rw
NODPD
rw
PM
rw
Toggle Fields

PM

Bits 0-2: Power mode.

Allowed values:
0: DEFAULT: Default. The part is in active or sleep mode.
0x1: DEEP_SLEEP_MODE: Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
0x2: POWER_DOWN_MODE: Power-down mode. ARM WFI will enter Power-down mode.
0x3: DEEP_POWER_DOWN_MODE: Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).

NODPD

Bit 3: A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked..

SLEEPFLAG

Bit 8: Sleep mode flag.

Allowed values:
0: ACTIVE_MODE: Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
0x1: LOW_POWER_MODE: Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.

DPDFLAG

Bit 11: Deep power-down flag.

Allowed values:
0: NOT_DEEP_POWER_DOWN: Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
0x1: DEEP_POWER_DOWN: Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.

GPREG[[0]]

General purpose register N

Offset: 0x4, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDATA
rw
Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[[1]]

General purpose register N

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDATA
rw
Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[[2]]

General purpose register N

Offset: 0xc, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDATA
rw
Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

GPREG[[3]]

General purpose register N

Offset: 0x10, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDATA
rw
Toggle Fields

GPDATA

Bits 0-31: Data retained during Deep power-down mode..

DPDCTRL

Deep power-down control register. Also includes bits for general purpose storage.

Offset: 0x14, reset: 0, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDATA
rw
LPOSCDPDEN
rw
LPOSCEN
rw
WAKEPAD_DISABLE
rw
WAKEUPHYS
rw
Toggle Fields

WAKEUPHYS

Bit 0: WAKEUP pin hysteresis enable.

Allowed values:
0: DISABLED: Disabled. Hysteresis for WAKEUP pin disabled.
0x1: ENABLED: Enabled. Hysteresis for WAKEUP pin enabled.

WAKEPAD_DISABLE

Bit 1: WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used..

Allowed values:
0: ENABLED: Enabled. The wake-up function is enabled on pin PIO0_4.
0x1: DISABLED: Disabled. Setting this bit disables the wake-up function on pin PIO0_4.

LPOSCEN

Bit 2: Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the external clock input..

Allowed values:
0: DISABLED: Disabled.
0x1: ENABLED: Enabled.

LPOSCDPDEN

Bit 3: causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit unless you use the self wake-up timer with the low-power oscillator clock source to wake up from Deep power-down mode..

Allowed values:
0: DISABLED: Disabled.
0x1: ENABLED: Enabled.

GPDATA

Bits 4-31: Data retained during Deep power-down mode..

SCT0

0x50004000: SCTimer/PWM (SCT)

57/177 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CONFIG
0x4 CTRL
0x8 LIMIT
0xc HALT
0x10 STOP
0x14 START
0x40 COUNT
0x44 STATE
0x48 INPUT
0x4c REGMODE
0x50 OUTPUT
0x54 OUTPUTDIRCTRL
0x58 RES
0xf0 EVEN
0xf4 EVFLAG
0xf8 CONEN
0xfc CONFLAG
0x100 CAP0
0x100 MATCH0
0x104 CAP1
0x104 MATCH1
0x108 CAP2
0x108 MATCH2
0x10c CAP3
0x10c MATCH3
0x110 CAP4
0x110 MATCH4
0x200 CAPCTRL0
0x200 MATCHREL0
0x204 CAPCTRL1
0x204 MATCHREL1
0x208 CAPCTRL2
0x208 MATCHREL2
0x20c CAPCTRL3
0x20c MATCHREL3
0x210 CAPCTRL4
0x210 MATCHREL4
0x300 EV_STATE [0]
0x304 EV_CTRL [0]
0x308 EV_STATE [1]
0x30c EV_CTRL [1]
0x310 EV_STATE [2]
0x314 EV_CTRL [2]
0x318 EV_STATE [3]
0x31c EV_CTRL [3]
0x320 EV_STATE [4]
0x324 EV_CTRL [4]
0x328 EV_STATE [5]
0x32c EV_CTRL [5]
0x500 OUT_SET [0]
0x504 OUT_CLR [0]
0x508 OUT_SET [1]
0x50c OUT_CLR [1]
0x510 OUT_SET [2]
0x514 OUT_CLR [2]
0x518 OUT_SET [3]
0x51c OUT_CLR [3]

CONFIG

SCT configuration register

Offset: 0x0, reset: 0x1E00, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUTOLIMIT_H
rw
AUTOLIMIT_L
rw
INSYNC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSYNC
rw
NORELOAD_H
rw
NORELOAD_L
rw
CKSEL
rw
CLKMODE
rw
UNIFY
rw
Toggle Fields

UNIFY

Bit 0: SCT operation.

Allowed values:
0: DUAL_COUNTER: The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
0x1: UNIFIED_COUNTER: The SCT operates as a unified 32-bit counter.

CLKMODE

Bits 1-2: SCT clock mode.

Allowed values:
0: SYSTEM_CLOCK_MODE: System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
0x1: SAMPLED_SYSTEM_CLOCK_MODE: Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
0x2: SCT_INPUT_CLOCK_MODE: SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
0x3: ASYNCHRONOUS_MODE: Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.

CKSEL

Bits 3-6: SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register..

Allowed values:
0: INPUT_0_RISING_EDGES: Rising edges on input 0.
0x1: INPUT_0_FALLING_EDGE: Falling edges on input 0.
0x2: INPUT_1_RISING_EDGES: Rising edges on input 1.
0x3: INPUT_1_FALLING_EDGE: Falling edges on input 1.
0x4: INPUT_2_RISING_EDGES: Rising edges on input 2.
0x5: INPUT_2_FALLING_EDGE: Falling edges on input 2.
0x6: INPUT_3_RISING_EDGES: Rising edges on input 3.
0x7: INPUT_3_FALLING_EDGE: Falling edges on input 3.

NORELOAD_L

Bit 7: A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set..

NORELOAD_H

Bit 8: A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set..

INSYNC

Bits 9-16: Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field..

AUTOLIMIT_L

Bit 17: A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set..

AUTOLIMIT_H

Bit 18: A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set..

CTRL

SCT control register

Offset: 0x4, reset: 0x40004, access: read-write

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRE_H
rw
BIDIR_H
rw
CLRCTR_H
rw
HALT_H
rw
STOP_H
rw
DOWN_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRE_L
rw
BIDIR_L
rw
CLRCTR_L
rw
HALT_L
rw
STOP_L
rw
DOWN_L
rw
Toggle Fields

DOWN_L

Bit 0: This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0..

STOP_L

Bit 1: When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes..

HALT_L

Bit 2: When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset..

CLRCTR_L

Bit 3: Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0..

BIDIR_L

Bit 4: L or unified counter direction select.

Allowed values:
0: UP: Up. The counter counts up to a limit condition, then is cleared to zero.
0x1: UP_DOWN: Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.

PRE_L

Bits 5-12: Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value..

DOWN_H

Bit 16: This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0..

STOP_H

Bit 17: When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes..

HALT_H

Bit 18: When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset..

CLRCTR_H

Bit 19: Writing a 1 to this bit clears the H counter. This bit always reads as 0..

BIDIR_H

Bit 20: Direction select.

Allowed values:
0: UP: The H counter counts up to its limit condition, then is cleared to zero.
0x1: UP_DOWN: The H counter counts up to its limit, then counts down to a limit condition or to 0.

PRE_H

Bits 21-28: Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value..

LIMIT

SCT limit event select register

Offset: 0x8, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LIMMSK_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIMMSK_L
rw
Toggle Fields

LIMMSK_L

Bits 0-5: If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

LIMMSK_H

Bits 16-21: If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT..

HALT

SCT halt event select register

Offset: 0xc, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HALTMSK_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTMSK_L
rw
Toggle Fields

HALTMSK_L

Bits 0-5: If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

HALTMSK_H

Bits 16-21: If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT..

STOP

SCT stop event select register

Offset: 0x10, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STOPMSK_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPMSK_L
rw
Toggle Fields

STOPMSK_L

Bits 0-5: If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

STOPMSK_H

Bits 16-21: If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT..

START

SCT start event select register

Offset: 0x14, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STARTMSK_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STARTMSK_L
rw
Toggle Fields

STARTMSK_L

Bits 0-5: If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

STARTMSK_H

Bits 16-21: If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT..

COUNT

SCT counter register

Offset: 0x40, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_L
rw
Toggle Fields

CTR_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter..

CTR_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter..

STATE

SCT state register

Offset: 0x44, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STATE_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATE_L
rw
Toggle Fields

STATE_L

Bits 0-4: State variable..

STATE_H

Bits 16-20: State variable..

INPUT

SCT input register

Offset: 0x48, reset: 0, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIN3
r
SIN2
r
SIN1
r
SIN0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIN3
r
AIN2
r
AIN1
r
AIN0
r
Toggle Fields

AIN0

Bit 0: Input 0 state. Input 0 state on the last SCT clock edge..

AIN1

Bit 1: Input 1 state. Input 1 state on the last SCT clock edge..

AIN2

Bit 2: Input 2 state. Input 2 state on the last SCT clock edge..

AIN3

Bit 3: Input 3 state. Input 3 state on the last SCT clock edge..

SIN0

Bit 16: Input 0 state. Input 0 state following the synchronization specified by INSYNC..

SIN1

Bit 17: Input 1 state. Input 1 state following the synchronization specified by INSYNC..

SIN2

Bit 18: Input 2 state. Input 2 state following the synchronization specified by INSYNC..

SIN3

Bit 19: Input 3 state. Input 3 state following the synchronization specified by INSYNC..

REGMODE

SCT match/capture mode register

Offset: 0x4c, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGMOD_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGMOD_L
rw
Toggle Fields

REGMOD_L

Bits 0-4: Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register..

REGMOD_H

Bits 16-20: Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers..

OUTPUT

SCT output register

Offset: 0x50, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT
rw
Toggle Fields

OUT

Bits 0-3: Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT..

OUTPUTDIRCTRL

SCT output counter direction control register

Offset: 0x54, reset: 0, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETCLR3
rw
SETCLR2
rw
SETCLR1
rw
SETCLR0
rw
Toggle Fields

SETCLR0

Bits 0-1: Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value..

Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR1

Bits 2-3: Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value..

Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR2

Bits 4-5: Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value..

Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR3

Bits 6-7: Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value..

Allowed values:
0: INDEPENDENT: Set and clear do not depend on the direction of any counter.
0x1: L_REVERSED: Set and clear are reversed when counter L or the unified counter is counting down.
0x2: H_REVERSED: Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

RES

SCT conflict resolution register

Offset: 0x58, reset: 0, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O3RES
rw
O2RES
rw
O1RES
rw
O0RES
rw
Toggle Fields

O0RES

Bits 0-1: Effect of simultaneous set and clear on output 0..

Allowed values:
0: NO_CHANGE: No change.
0x1: SET: Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
0x2: CLEAR: Clear output (or set based on the SETCLR0 field).
0x3: TOGGLE_OUTPUT: Toggle output.

O1RES

Bits 2-3: Effect of simultaneous set and clear on output 1..

Allowed values:
0: NO_CHANGE: No change.
0x1: SET: Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
0x2: CLEAR: Clear output (or set based on the SETCLR1 field).
0x3: TOGGLE_OUTPUT: Toggle output.

O2RES

Bits 4-5: Effect of simultaneous set and clear on output 2..

Allowed values:
0: NO_CHANGE: No change.
0x1: SET: Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
0x2: CLEAR: Clear output n (or set based on the SETCLR2 field).
0x3: TOGGLE_OUTPUT: Toggle output.

O3RES

Bits 6-7: Effect of simultaneous set and clear on output 3..

Allowed values:
0: NO_CHANGE: No change.
0x1: SET: Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
0x2: CLEAR: Clear output (or set based on the SETCLR3 field).
0x3: TOGGLE_OUTPUT: Toggle output.

EVEN

SCT event interrupt enable register

Offset: 0xf0, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEN
rw
Toggle Fields

IEN

Bits 0-5: The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

EVFLAG

SCT event flag register

Offset: 0xf4, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLAG
rw
Toggle Fields

FLAG

Bits 0-5: Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT..

CONEN

SCT conflict interrupt enable register

Offset: 0xf8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCEN
rw
Toggle Fields

NCEN

Bits 0-3: The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT..

CONFLAG

SCT conflict flag register

Offset: 0xfc, reset: 0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSERRH
rw
BUSERRL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCFLAG
rw
Toggle Fields

NCFLAG

Bits 0-3: Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT..

BUSERRL

Bit 30: The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful..

BUSERRH

Bit 31: The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted..

CAP0

SCT capture register of capture channel

Offset: 0x100, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPn_L
rw
Toggle Fields

CAPn_L

Bits 0-15: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured..

CAPn_H

Bits 16-31: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured..

MATCH0

SCT match value register of match channels

Offset: 0x100, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCHn_L
rw
Toggle Fields

MATCHn_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter..

MATCHn_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter..

CAP1

SCT capture register of capture channel

Offset: 0x104, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPn_L
rw
Toggle Fields

CAPn_L

Bits 0-15: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured..

CAPn_H

Bits 16-31: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured..

MATCH1

SCT match value register of match channels

Offset: 0x104, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCHn_L
rw
Toggle Fields

MATCHn_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter..

MATCHn_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter..

CAP2

SCT capture register of capture channel

Offset: 0x108, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPn_L
rw
Toggle Fields

CAPn_L

Bits 0-15: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured..

CAPn_H

Bits 16-31: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured..

MATCH2

SCT match value register of match channels

Offset: 0x108, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCHn_L
rw
Toggle Fields

MATCHn_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter..

MATCHn_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter..

CAP3

SCT capture register of capture channel

Offset: 0x10c, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPn_L
rw
Toggle Fields

CAPn_L

Bits 0-15: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured..

CAPn_H

Bits 16-31: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured..

MATCH3

SCT match value register of match channels

Offset: 0x10c, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCHn_L
rw
Toggle Fields

MATCHn_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter..

MATCHn_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter..

CAP4

SCT capture register of capture channel

Offset: 0x110, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPn_L
rw
Toggle Fields

CAPn_L

Bits 0-15: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured..

CAPn_H

Bits 16-31: When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured..

MATCH4

SCT match value register of match channels

Offset: 0x110, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCHn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCHn_L
rw
Toggle Fields

MATCHn_L

Bits 0-15: When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter..

MATCHn_H

Bits 16-31: When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter..

CAPCTRL0

SCT capture control register

Offset: 0x200, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPCONn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCONn_L
rw
Toggle Fields

CAPCONn_L

Bits 0-15: If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT..

CAPCONn_H

Bits 16-31: If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT..

MATCHREL0

SCT match reload value register

Offset: 0x200, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOADn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOADn_L
rw
Toggle Fields

RELOADn_L

Bits 0-15: When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register..

RELOADn_H

Bits 16-31: When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register..

CAPCTRL1

SCT capture control register

Offset: 0x204, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPCONn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCONn_L
rw
Toggle Fields

CAPCONn_L

Bits 0-15: If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT..

CAPCONn_H

Bits 16-31: If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT..

MATCHREL1

SCT match reload value register

Offset: 0x204, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOADn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOADn_L
rw
Toggle Fields

RELOADn_L

Bits 0-15: When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register..

RELOADn_H

Bits 16-31: When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register..

CAPCTRL2

SCT capture control register

Offset: 0x208, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPCONn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCONn_L
rw
Toggle Fields

CAPCONn_L

Bits 0-15: If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT..

CAPCONn_H

Bits 16-31: If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT..

MATCHREL2

SCT match reload value register

Offset: 0x208, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOADn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOADn_L
rw
Toggle Fields

RELOADn_L

Bits 0-15: When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register..

RELOADn_H

Bits 16-31: When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register..

CAPCTRL3

SCT capture control register

Offset: 0x20c, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPCONn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCONn_L
rw
Toggle Fields

CAPCONn_L

Bits 0-15: If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT..

CAPCONn_H

Bits 16-31: If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT..

MATCHREL3

SCT match reload value register

Offset: 0x20c, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOADn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOADn_L
rw
Toggle Fields

RELOADn_L

Bits 0-15: When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register..

RELOADn_H

Bits 16-31: When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register..

CAPCTRL4

SCT capture control register

Offset: 0x210, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAPCONn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCONn_L
rw
Toggle Fields

CAPCONn_L

Bits 0-15: If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT..

CAPCONn_H

Bits 16-31: If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT..

MATCHREL4

SCT match reload value register

Offset: 0x210, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOADn_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOADn_L
rw
Toggle Fields

RELOADn_L

Bits 0-15: When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register..

RELOADn_H

Bits 16-31: When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register..

EV_STATE [0]

SCT event state register 0

Offset: 0x300, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [0]

SCT event control register 0

Offset: 0x304, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

EV_STATE [1]

SCT event state register 0

Offset: 0x308, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [1]

SCT event control register 0

Offset: 0x30c, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

EV_STATE [2]

SCT event state register 0

Offset: 0x310, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [2]

SCT event control register 0

Offset: 0x314, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

EV_STATE [3]

SCT event state register 0

Offset: 0x318, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [3]

SCT event control register 0

Offset: 0x31c, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

EV_STATE [4]

SCT event state register 0

Offset: 0x320, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [4]

SCT event control register 0

Offset: 0x324, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

EV_STATE [5]

SCT event state register 0

Offset: 0x328, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEMSK1
rw
STATEMSK0
rw
Toggle Fields

STATEMSK0

Bit 0: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

STATEMSK1

Bit 1: If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT..

EV_CTRL [5]

SCT event control register 0

Offset: 0x32c, reset: 0, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
rw
MATCHMEM
rw
STATEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATEV
rw
STATELD
rw
COMBMODE
rw
IOCOND
rw
IOSEL
rw
OUTSEL
rw
HEVENT
rw
MATCHSEL
rw
Toggle Fields

MATCHSEL

Bits 0-3: Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running..

HEVENT

Bit 4: Select L/H counter. Do not set this bit if UNIFY = 1..

Allowed values:
0: L_COUNTER: Selects the L state and the L match register selected by MATCHSEL.
0x1: H_COUNTER: Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

Bit 5: Input/output select.

Allowed values:
0: INPUT: Selects the inputs selected by IOSEL.
0x1: OUTPUT: Selects the outputs selected by IOSEL.

IOSEL

Bits 6-9: Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event..

IOCOND

Bits 10-11: Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ..

Allowed values:
0: LOW: LOW
0x1: RISE: Rise
0x2: FALL: Fall
0x3: HIGH: HIGH

COMBMODE

Bits 12-13: Selects how the specified match and I/O condition are used and combined..

Allowed values:
0: OR: OR. The event occurs when either the specified match or I/O condition occurs.
0x1: MATCH: MATCH. Uses the specified match only.
0x2: IO: IO. Uses the specified I/O condition only.
0x3: AND: AND. The event occurs when the specified match and I/O condition occur simultaneously.

STATELD

Bit 14: This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state..

Allowed values:
0: ADD: STATEV value is added into STATE (the carry-out is ignored).
0x1: LOAD: STATEV value is loaded into STATE.

STATEV

Bits 15-19: This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value..

MATCHMEM

Bit 20: If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value..

DIRECTION

Bits 21-22: Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved..

Allowed values:
0: DIRECTION_INDEPENDENT: Direction independent. This event is triggered regardless of the count direction.
0x1: COUNTING_UP: Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2: COUNTING_DOWN: Counting down. This event is triggered only during down-counting when BIDIR = 1.

OUT_SET [0]

SCT output 0 set register

Offset: 0x500, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET
rw
Toggle Fields

SET

Bits 0-5: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_CLR [0]

SCT output 0 clear register

Offset: 0x504, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR
rw
Toggle Fields

CLR

Bits 0-5: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_SET [1]

SCT output 0 set register

Offset: 0x508, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET
rw
Toggle Fields

SET

Bits 0-5: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_CLR [1]

SCT output 0 clear register

Offset: 0x50c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR
rw
Toggle Fields

CLR

Bits 0-5: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_SET [2]

SCT output 0 set register

Offset: 0x510, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET
rw
Toggle Fields

SET

Bits 0-5: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_CLR [2]

SCT output 0 clear register

Offset: 0x514, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR
rw
Toggle Fields

CLR

Bits 0-5: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_SET [3]

SCT output 0 set register

Offset: 0x518, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET
rw
Toggle Fields

SET

Bits 0-5: A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

OUT_CLR [3]

SCT output 0 clear register

Offset: 0x51c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR
rw
Toggle Fields

CLR

Bits 0-5: A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register..

SPI0

0x40058000: Serial Peripheral Interfaces (SPI)

31/54 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFG
0x4 DLY
0x8 STAT
0xc INTENSET
0x10 INTENCLR
0x14 RXDAT
0x18 TXDATCTL
0x1c TXDAT
0x20 TXCTL
0x24 DIV
0x28 INTSTAT

CFG

SPI Configuration register

Offset: 0x0, reset: 0, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPOL0
rw
LOOP
rw
CPOL
rw
CPHA
rw
LSBF
rw
MASTER
rw
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: SPI enable..

Allowed values:
0: DISABLED: Disabled. The SPI is disabled and the internal state machine and counters are reset.
0x1: ENABLED: Enabled. The SPI is enabled for operation.

MASTER

Bit 2: Master mode select..

Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.

LSBF

Bit 3: LSB First mode enable..

Allowed values:
0: STANDARD: Standard. Data is transmitted and received in standard MSB first order.
0x1: REVERSE: Reverse. Data is transmitted and received in reverse order (LSB first).

CPHA

Bit 4: Clock Phase select..

Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.

CPOL

Bit 5: Clock Polarity select..

Allowed values:
0: LOW: Low. The rest state of the clock (between transfers) is low.
0x1: HIGH: High. The rest state of the clock (between transfers) is high.

LOOP

Bit 7: Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing..

Allowed values:
0: DISABLED: Disabled.
0x1: ENABLED: Enabled.

SPOL0

Bit 8: SSEL0 Polarity select..

Allowed values:
0: LOW: Low. The SSEL0 pin is active low.
0x1: HIGH: High. The SSEL0 pin is active high.

DLY

SPI Delay register

Offset: 0x4, reset: 0, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANSFER_DELAY
rw
FRAME_DELAY
rw
POST_DELAY
rw
PRE_DELAY
rw
Toggle Fields

PRE_DELAY

Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

POST_DELAY

Bits 4-7: Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

FRAME_DELAY

Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

TRANSFER_DELAY

Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..

STAT

SPI Status. Some status flags can be cleared by writing a 1 to that bit position

Offset: 0x8, reset: 0x102, access: read-write

4/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSTIDLE
r
ENDTRANSFER
rw
STALLED
r
SSD
w
SSA
w
TXUR
w
RXOV
w
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register..

TXRDY

Bit 1: Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register..

RXOV

Bit 2: Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set..

TXUR

Bit 3: Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set..

SSA

Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..

SSD

Bit 5: Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software..

STALLED

Bit 6: Stalled status flag. This indicates whether the SPI is currently in a stall condition..

ENDTRANSFER

Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..

MSTIDLE

Bit 8: Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data..

INTENSET

SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Offset: 0xc, reset: 0, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSDEN
rw
SSAEN
rw
TXUREN
rw
RXOVEN
rw
TXRDYEN
rw
RXRDYEN
rw
Toggle Fields

RXRDYEN

Bit 0: Determines whether an interrupt occurs when receiver data is available..

Allowed values:
0: RXRDYEN_0: No interrupt will be generated when receiver data is available.
0x1: RXRDYEN_1: An interrupt will be generated when receiver data is available in the RXDAT register.

TXRDYEN

Bit 1: Determines whether an interrupt occurs when the transmitter holding register is available..

Allowed values:
0: TXRDYEN_0: No interrupt will be generated when the transmitter holding register is available.
0x1: TXRDYEN_1: An interrupt will be generated when data may be written to TXDAT.

RXOVEN

Bit 2: Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur..

Allowed values:
0: RXOVEN_0: No interrupt will be generated when a receiver overrun occurs.
0x1: RXOVEN_1: An interrupt will be generated if a receiver overrun occurs.

TXUREN

Bit 3: Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available..

Allowed values:
0: TXUREN_0: No interrupt will be generated when the transmitter underruns.
0x1: TXUREN_1: An interrupt will be generated if the transmitter underruns.

SSAEN

Bit 4: Determines whether an interrupt occurs when the Slave Select is asserted..

Allowed values:
0: SSAEN_0: No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: SSAEN_1: An interrupt will be generated when any Slave Select transitions from deasserted to asserted.

SSDEN

Bit 5: Determines whether an interrupt occurs when the Slave Select is deasserted..

Allowed values:
0: SSDEN_0: No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: SSDEN_1: An interrupt will be generated when all asserted Slave Selects transition to deasserted.

INTENCLR

SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

Offset: 0x10, reset: 0, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSDEN
w
SSAEN
w
TXUREN
w
RXOVEN
w
TXRDYEN
w
RXRDYEN
w
Toggle Fields

RXRDYEN

Bit 0: Writing 1 clears the corresponding bits in the INTENSET register..

TXRDYEN

Bit 1: Writing 1 clears the corresponding bits in the INTENSET register..

RXOVEN

Bit 2: Writing 1 clears the corresponding bits in the INTENSET register..

TXUREN

Bit 3: Writing 1 clears the corresponding bits in the INTENSET register..

SSAEN

Bit 4: Writing 1 clears the corresponding bits in the INTENSET register..

SSDEN

Bit 5: Writing 1 clears the corresponding bits in the INTENSET register..

RXDAT

SPI Receive Data

Offset: 0x14, reset: 0, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOT
r
RXSSEL0_N
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDAT
r
Toggle Fields

RXDAT

Bits 0-15: Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL..

RXSSEL0_N

Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..

SOT

Bit 20: Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit..

TXDATCTL

SPI Transmit Data with Control

Offset: 0x18, reset: 0, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEN
rw
RXIGNORE
rw
EOF
rw
EOT
rw
TXSSEL0_N
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDAT
rw
Toggle Fields

TXDAT

Bits 0-15: Transmit Data. This field provides from 1 to 16 bits of data to be transmitted..

TXSSEL0_N

Bit 16: Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register..

Allowed values:
0: TXSSEL0_N_0: SSEL0 asserted.
0x1: TXSSEL0_N_1: SSEL0 not asserted.

EOT

Bit 20: End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register..

Allowed values:
0: SSEL_deasserted: This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: SSEL_not_deasserted: This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.

EOF

Bit 21: End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..

Allowed values:
0: Data_not_EOF: This piece of data transmitted is not treated as the end of a frame.
0x1: Data_EOF: This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.

RXIGNORE

Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA..

Allowed values:
0: Read_received_data: Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: Ignore_received_data: Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.

LEN

Bits 24-27: Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length..

Allowed values:
0: LEN_0: no description available
0x1: LEN_1: Data transfer is 1 bit in length.
0x2: LEN_2: Data transfer is 2 bit in length.
0x3: LEN_3: Data transfer is 3 bit in length.
0x4: LEN_4: Data transfer is 4 bit in length.
0x5: LEN_5: Data transfer is 5 bit in length.
0x6: LEN_6: Data transfer is 6 bit in length.
0x7: LEN_7: Data transfer is 7 bit in length.
0x8: LEN_8: Data transfer is 8 bit in length.
0x9: LEN_9: Data transfer is 9 bit in length.
0xA: LEN_10: Data transfer is 10 bit in length.
0xB: LEN_11: Data transfer is 11 bit in length.
0xC: LEN_12: Data transfer is 12 bit in length.
0xD: LEN_13: Data transfer is 13 bit in length.
0xE: LEN_14: Data transfer is 14 bit in length.
0xF: LEN_15: Data transfer is 15 bit in length.

TXDAT

SPI Transmit Data.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-15: Transmit Data. This field provides from 4 to 16 bits of data to be transmitted..

TXCTL

SPI Transmit Control

Offset: 0x20, reset: 0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEN
rw
RXIGNORE
rw
EOF
rw
EOT
rw
TXSSEL0_N
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

TXSSEL0_N

Bit 16: Transmit Slave Select 0..

EOT

Bit 20: End of Transfer..

EOF

Bit 21: End of Frame..

RXIGNORE

Bit 22: Receive Ignore..

LEN

Bits 24-27: Data transfer Length..

DIV

SPI clock Divider

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVVAL
rw
Toggle Fields

DIVVAL

Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..

INTSTAT

SPI Interrupt Status

Offset: 0x28, reset: 0x2, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSD
r
SSA
r
TXUR
r
RXOV
r
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag..

TXRDY

Bit 1: Transmitter Ready flag..

RXOV

Bit 2: Receiver Overrun interrupt flag..

TXUR

Bit 3: Transmitter Underrun interrupt flag..

SSA

Bit 4: Slave Select Assert..

SSD

Bit 5: Slave Select Deassert..

SPI1

0x4005c000: Serial Peripheral Interfaces (SPI)

31/54 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFG
0x4 DLY
0x8 STAT
0xc INTENSET
0x10 INTENCLR
0x14 RXDAT
0x18 TXDATCTL
0x1c TXDAT
0x20 TXCTL
0x24 DIV
0x28 INTSTAT

CFG

SPI Configuration register

Offset: 0x0, reset: 0, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPOL0
rw
LOOP
rw
CPOL
rw
CPHA
rw
LSBF
rw
MASTER
rw
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: SPI enable..

Allowed values:
0: DISABLED: Disabled. The SPI is disabled and the internal state machine and counters are reset.
0x1: ENABLED: Enabled. The SPI is enabled for operation.

MASTER

Bit 2: Master mode select..

Allowed values:
0: SLAVE_MODE: Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1: MASTER_MODE: Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.

LSBF

Bit 3: LSB First mode enable..

Allowed values:
0: STANDARD: Standard. Data is transmitted and received in standard MSB first order.
0x1: REVERSE: Reverse. Data is transmitted and received in reverse order (LSB first).

CPHA

Bit 4: Clock Phase select..

Allowed values:
0: CHANGE: Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1: CAPTURE: Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.

CPOL

Bit 5: Clock Polarity select..

Allowed values:
0: LOW: Low. The rest state of the clock (between transfers) is low.
0x1: HIGH: High. The rest state of the clock (between transfers) is high.

LOOP

Bit 7: Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing..

Allowed values:
0: DISABLED: Disabled.
0x1: ENABLED: Enabled.

SPOL0

Bit 8: SSEL0 Polarity select..

Allowed values:
0: LOW: Low. The SSEL0 pin is active low.
0x1: HIGH: High. The SSEL0 pin is active high.

DLY

SPI Delay register

Offset: 0x4, reset: 0, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANSFER_DELAY
rw
FRAME_DELAY
rw
POST_DELAY
rw
PRE_DELAY
rw
Toggle Fields

PRE_DELAY

Bits 0-3: Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

POST_DELAY

Bits 4-7: Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

FRAME_DELAY

Bits 8-11: If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted..

TRANSFER_DELAY

Bits 12-15: Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times..

STAT

SPI Status. Some status flags can be cleared by writing a 1 to that bit position

Offset: 0x8, reset: 0x102, access: read-write

4/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSTIDLE
r
ENDTRANSFER
rw
STALLED
r
SSD
w
SSA
w
TXUR
w
RXOV
w
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register..

TXRDY

Bit 1: Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register..

RXOV

Bit 2: Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set..

TXUR

Bit 3: Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set..

SSA

Bit 4: Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software..

SSD

Bit 5: Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software..

STALLED

Bit 6: Stalled status flag. This indicates whether the SPI is currently in a stall condition..

ENDTRANSFER

Bit 7: End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted..

MSTIDLE

Bit 8: Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data..

INTENSET

SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Offset: 0xc, reset: 0, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSDEN
rw
SSAEN
rw
TXUREN
rw
RXOVEN
rw
TXRDYEN
rw
RXRDYEN
rw
Toggle Fields

RXRDYEN

Bit 0: Determines whether an interrupt occurs when receiver data is available..

Allowed values:
0: RXRDYEN_0: No interrupt will be generated when receiver data is available.
0x1: RXRDYEN_1: An interrupt will be generated when receiver data is available in the RXDAT register.

TXRDYEN

Bit 1: Determines whether an interrupt occurs when the transmitter holding register is available..

Allowed values:
0: TXRDYEN_0: No interrupt will be generated when the transmitter holding register is available.
0x1: TXRDYEN_1: An interrupt will be generated when data may be written to TXDAT.

RXOVEN

Bit 2: Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur..

Allowed values:
0: RXOVEN_0: No interrupt will be generated when a receiver overrun occurs.
0x1: RXOVEN_1: An interrupt will be generated if a receiver overrun occurs.

TXUREN

Bit 3: Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available..

Allowed values:
0: TXUREN_0: No interrupt will be generated when the transmitter underruns.
0x1: TXUREN_1: An interrupt will be generated if the transmitter underruns.

SSAEN

Bit 4: Determines whether an interrupt occurs when the Slave Select is asserted..

Allowed values:
0: SSAEN_0: No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1: SSAEN_1: An interrupt will be generated when any Slave Select transitions from deasserted to asserted.

SSDEN

Bit 5: Determines whether an interrupt occurs when the Slave Select is deasserted..

Allowed values:
0: SSDEN_0: No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1: SSDEN_1: An interrupt will be generated when all asserted Slave Selects transition to deasserted.

INTENCLR

SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

Offset: 0x10, reset: 0, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSDEN
w
SSAEN
w
TXUREN
w
RXOVEN
w
TXRDYEN
w
RXRDYEN
w
Toggle Fields

RXRDYEN

Bit 0: Writing 1 clears the corresponding bits in the INTENSET register..

TXRDYEN

Bit 1: Writing 1 clears the corresponding bits in the INTENSET register..

RXOVEN

Bit 2: Writing 1 clears the corresponding bits in the INTENSET register..

TXUREN

Bit 3: Writing 1 clears the corresponding bits in the INTENSET register..

SSAEN

Bit 4: Writing 1 clears the corresponding bits in the INTENSET register..

SSDEN

Bit 5: Writing 1 clears the corresponding bits in the INTENSET register..

RXDAT

SPI Receive Data

Offset: 0x14, reset: 0, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOT
r
RXSSEL0_N
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDAT
r
Toggle Fields

RXDAT

Bits 0-15: Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL..

RXSSEL0_N

Bit 16: Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG..

SOT

Bit 20: Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit..

TXDATCTL

SPI Transmit Data with Control

Offset: 0x18, reset: 0, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEN
rw
RXIGNORE
rw
EOF
rw
EOT
rw
TXSSEL0_N
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDAT
rw
Toggle Fields

TXDAT

Bits 0-15: Transmit Data. This field provides from 1 to 16 bits of data to be transmitted..

TXSSEL0_N

Bit 16: Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register..

Allowed values:
0: TXSSEL0_N_0: SSEL0 asserted.
0x1: TXSSEL0_N_1: SSEL0 not asserted.

EOT

Bit 20: End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register..

Allowed values:
0: SSEL_deasserted: This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1: SSEL_not_deasserted: This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.

EOF

Bit 21: End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits..

Allowed values:
0: Data_not_EOF: This piece of data transmitted is not treated as the end of a frame.
0x1: Data_EOF: This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.

RXIGNORE

Bit 22: Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA..

Allowed values:
0: Read_received_data: Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1: Ignore_received_data: Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.

LEN

Bits 24-27: Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length..

Allowed values:
0: LEN_0: no description available
0x1: LEN_1: Data transfer is 1 bit in length.
0x2: LEN_2: Data transfer is 2 bit in length.
0x3: LEN_3: Data transfer is 3 bit in length.
0x4: LEN_4: Data transfer is 4 bit in length.
0x5: LEN_5: Data transfer is 5 bit in length.
0x6: LEN_6: Data transfer is 6 bit in length.
0x7: LEN_7: Data transfer is 7 bit in length.
0x8: LEN_8: Data transfer is 8 bit in length.
0x9: LEN_9: Data transfer is 9 bit in length.
0xA: LEN_10: Data transfer is 10 bit in length.
0xB: LEN_11: Data transfer is 11 bit in length.
0xC: LEN_12: Data transfer is 12 bit in length.
0xD: LEN_13: Data transfer is 13 bit in length.
0xE: LEN_14: Data transfer is 14 bit in length.
0xF: LEN_15: Data transfer is 15 bit in length.

TXDAT

SPI Transmit Data.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-15: Transmit Data. This field provides from 4 to 16 bits of data to be transmitted..

TXCTL

SPI Transmit Control

Offset: 0x20, reset: 0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEN
rw
RXIGNORE
rw
EOF
rw
EOT
rw
TXSSEL0_N
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

TXSSEL0_N

Bit 16: Transmit Slave Select 0..

EOT

Bit 20: End of Transfer..

EOF

Bit 21: End of Frame..

RXIGNORE

Bit 22: Receive Ignore..

LEN

Bits 24-27: Data transfer Length..

DIV

SPI clock Divider

Offset: 0x24, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVVAL
rw
Toggle Fields

DIVVAL

Bits 0-15: Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536..

INTSTAT

SPI Interrupt Status

Offset: 0x28, reset: 0x2, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSD
r
SSA
r
TXUR
r
RXOV
r
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag..

TXRDY

Bit 1: Transmitter Ready flag..

RXOV

Bit 2: Receiver Overrun interrupt flag..

TXUR

Bit 3: Transmitter Underrun interrupt flag..

SSA

Bit 4: Slave Select Assert..

SSD

Bit 5: Slave Select Deassert..

SWM0

0x4000c000: LPC81x SWM

9/81 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PINASSIGN0
0x0 PINASSIGN_DATA0
0x4 PINASSIGN1
0x4 PINASSIGN_DATA1
0x8 PINASSIGN2
0x8 PINASSIGN_DATA2
0xc PINASSIGN3
0xc PINASSIGN_DATA3
0x10 PINASSIGN4
0x10 PINASSIGN_DATA4
0x14 PINASSIGN5
0x14 PINASSIGN_DATA5
0x18 PINASSIGN6
0x18 PINASSIGN_DATA6
0x1c PINASSIGN7
0x1c PINASSIGN_DATA7
0x20 PINASSIGN8
0x20 PINASSIGN_DATA8
0x1c0 PINENABLE0

PINASSIGN0

Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U0_CTS_I
rw
U0_RTS_O
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U0_RXD_I
rw
U0_TXD_O
rw
Toggle Fields

U0_TXD_O

Bits 0-7: U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U0_RXD_I

Bits 8-15: U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U0_RTS_O

Bits 16-23: U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U0_CTS_I

Bits 24-31: U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA0

Pin assign register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN1

Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U1_RTS_O
rw
U1_RXD_I
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U1_TXD_O
rw
U0_SCLK_IO
rw
Toggle Fields

U0_SCLK_IO

Bits 0-7: U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U1_TXD_O

Bits 8-15: U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U1_RXD_I

Bits 16-23: U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U1_RTS_O

Bits 24-31: U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA1

Pin assign register

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN2

Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.

Offset: 0x8, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U2_RXD_I
rw
U2_TXD_O
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U1_SCLK_IO
rw
U1_CTS_I
rw
Toggle Fields

U1_CTS_I

Bits 0-7: U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U1_SCLK_IO

Bits 8-15: U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U2_TXD_O

Bits 16-23: U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U2_RXD_I

Bits 24-31: U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA2

Pin assign register

Offset: 0x8, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN3

Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK.

Offset: 0xc, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI0_SCK_IO
rw
U2_SCLK_IO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U2_CTS_I
rw
U2_RTS_O
rw
Toggle Fields

U2_RTS_O

Bits 0-7: U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U2_CTS_I

Bits 8-15: U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

U2_SCLK_IO

Bits 16-23: U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI0_SCK_IO

Bits 24-31: SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA3

Pin assign register

Offset: 0xc, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN4

Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO,SPI0_SSEL, SPI1_SCK.

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1_SCK_IO
rw
SPI0_SSEL_IO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI0_MISO_IO
rw
SPI0_MOSI_IO
rw
Toggle Fields

SPI0_MOSI_IO

Bits 0-7: SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI0_MISO_IO

Bits 8-15: SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI0_SSEL_IO

Bits 16-23: SPI0_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI1_SCK_IO

Bits 24-31: SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA4

Pin assign register

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN5

Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO,SPI1_SSEL, CTIN_0

Offset: 0x14, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTIN_0_I
rw
SPI1_SSEL_IO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI1_MISO_IO
rw
SPI1_MOSI_IO
rw
Toggle Fields

SPI1_MOSI_IO

Bits 0-7: SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI1_MISO_IO

Bits 8-15: SPI1_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

SPI1_SSEL_IO

Bits 16-23: SPI1_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTIN_0_I

Bits 24-31: CTIN_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA5

Pin assign register

Offset: 0x14, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN6

Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3,CTOUT_0.

Offset: 0x18, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTOUT_0_O
rw
CTIN_3_I
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTIN_2_I
rw
CTIN_1_I
rw
Toggle Fields

CTIN_1_I

Bits 0-7: CTIN_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTIN_2_I

Bits 8-15: CTIN_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTIN_3_I

Bits 16-23: CTIN_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTOUT_0_O

Bits 24-31: CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA6

Pin assign register

Offset: 0x18, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN7

Pin assign register 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3,I2C_SDA.

Offset: 0x1c, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C_SDA_IO
rw
CTOUT_3_O
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOUT_2_O
rw
CTOUT_1_O
rw
Toggle Fields

CTOUT_1_O

Bits 0-7: CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTOUT_2_O

Bits 8-15: CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CTOUT_3_O

Bits 16-23: CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

I2C_SDA_IO

Bits 24-31: I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA7

Pin assign register

Offset: 0x1c, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINASSIGN8

Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT,GPIO_INT_BMAT.

Offset: 0x20, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_INT_BMAT_O
rw
CLKOUT_O
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACMP_O_O
rw
I2C_SCL_IO
rw
Toggle Fields

I2C_SCL_IO

Bits 0-7: I2C_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

ACMP_O_O

Bits 8-15: ACMP_O_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

CLKOUT_O

Bits 16-23: CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

GPIO_INT_BMAT_O

Bits 24-31: GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11)..

PINASSIGN_DATA8

Pin assign register

Offset: 0x20, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw
DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw
DATA0
rw
Toggle Fields

DATA0

Bits 0-7: T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA1

Bits 8-15: T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA2

Bits 16-23: T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

DATA3

Bits 24-31: T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)..

PINENABLE0

Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on.

Offset: 0x1c0, reset: 0x1B3, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDCMP
rw
CLKIN
rw
RESETN
rw
XTALOUT
rw
XTALIN
rw
SWDIO
rw
SWCLK
rw
ACMP_I2
rw
ACMP_I1
rw
Toggle Fields

ACMP_I1

Bit 0: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin..

Allowed values:
0: ENABLED: Enable ACMP_I1. This function is enabled on pin PIO0_0.
0x1: DISABLED: Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0.

ACMP_I2

Bit 1: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2..

Allowed values:
0: ACMP_I2_0: Enable ACMP_I2. This function is enabled on pin PIO0_1.
0x1: ACMP_I2_1: Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1.

SWCLK

Bit 2: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default..

Allowed values:
0: ENABLED: Enable SWCLK. This function is enabled on pin PIO0_3.
0x1: DISABLED: Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3.

SWDIO

Bit 3: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default..

Allowed values:
0: ENABLED: Enable SWDIO. This function is enabled on pin PIO0_2.
0x1: DISABLED: Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2.

XTALIN

Bit 4: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin..

Allowed values:
0: ENABLED: Enable XTALIN. This function is enabled on pin PIO0_8.
0x1: DISABLED: Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8.

XTALOUT

Bit 5: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin..

Allowed values:
0: ENABLED: Enable XTALOUT. This function is enabled on pin PIO0_9.
0x1: DISABLED: Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9.

RESETN

Bit 6: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default..

Allowed values:
0: ENABLED: Enable RESETN. This function is enabled on pin PIO0_5.
0x1: DISABLED: Disable RESETN. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5.

CLKIN

Bit 7: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN..

Allowed values:
0: ENABLED: Enable CLKIN. This function is enabled on pin PIO0_1.
0x1: DISABLED: Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN.

VDDCMP

Bit 8: Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin..

Allowed values:
0: ENABLED: Enable VDDCMP. This function is enabled on pin PIO0_6.
0x1: DISABLED: Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6.

SYSCON

0x40048000: System configuration (SYSCON)

86/118 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SYSMEMREMAP
0x4 PRESETCTRL
0x8 SYSPLLCTRL
0xc SYSPLLSTAT
0x20 SYSOSCCTRL
0x24 WDTOSCCTRL
0x30 SYSRSTSTAT
0x40 SYSPLLCLKSEL
0x44 SYSPLLCLKUEN
0x70 MAINCLKSEL
0x74 MAINCLKUEN
0x78 SYSAHBCLKDIV
0x80 SYSAHBCLKCTRL
0x94 UARTCLKDIV
0xe0 CLKOUTSEL
0xe4 CLKOUTUEN
0xe8 CLKOUTDIV
0xf0 UARTFRGDIV
0xf4 UARTFRGMULT
0xfc EXTTRACECMD
0x100 PIOPORCAP0
0x134 IOCONCLKDIV6
0x138 IOCONCLKDIV5
0x13c IOCONCLKDIV4
0x140 IOCONCLKDIV3
0x144 IOCONCLKDIV2
0x148 IOCONCLKDIV1
0x14c IOCONCLKDIV0
0x150 BODCTRL
0x154 SYSTCKCAL
0x170 IRQLATENCY
0x174 NMISRC
0x178 PINTSEL[[0]]
0x17c PINTSEL[[1]]
0x180 PINTSEL[[2]]
0x184 PINTSEL[[3]]
0x188 PINTSEL[[4]]
0x18c PINTSEL[[5]]
0x190 PINTSEL[[6]]
0x194 PINTSEL[[7]]
0x204 STARTERP0
0x214 STARTERP1
0x230 PDSLEEPCFG
0x234 PDAWAKECFG
0x238 PDRUNCFG
0x3f8 DEVICE_ID

SYSMEMREMAP

System Remap register

Offset: 0x0, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAP
rw
Toggle Fields

MAP

Bits 0-1: System memory remap. Value 0x3 is reserved..

Allowed values:
0: BOOT_LOADER_MODE: Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
0x1: USER_RAM_MODE: User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
0x2: USER_FLASH_MODE: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.

PRESETCTRL

Peripheral reset control register

Offset: 0x4, reset: 0x2101DFFF, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACMP_RST_N
rw
FLASH_RST_N
rw
GPIO_RST_N
rw
WKT_RST_N
rw
SCT_RST_N
rw
MRT_RST_N
rw
I2C0_RST_N
rw
UART2_RST_N
rw
UART1_RST_N
rw
UART0_RST_N
rw
UARTFRG_RST_N
rw
SPI1_RST_N
rw
SPI0_RST_N
rw
Toggle Fields

SPI0_RST_N

Bit 0: SPI0 reset control..

Allowed values:
0: SPI0_RST_N_0: Assert the SPI0 reset.
0x1: SPI0_RST_N_1: Clear the SPI0 reset.

SPI1_RST_N

Bit 1: SPI1 reset control..

Allowed values:
0: SPI1_RST_N_0: Assert the SPI1 reset.
0x1: SPI1_RST_N_1: Clear the SPI1 reset.

UARTFRG_RST_N

Bit 2: USART fractional baud rate generator(UARTFRG) reset control..

Allowed values:
0: UARTFRG_RST_N_0: Assert the UARTFRG reset.
0x1: UARTFRG_RST_N_1: Clear the UARTFRG reset.

UART0_RST_N

Bit 3: USART0 reset control..

Allowed values:
0: UART0_RST_N_0: Assert the USART0 reset.
0x1: UART0_RST_N_1: Clear the USART0 reset.

UART1_RST_N

Bit 4: USART1 reset control..

Allowed values:
0: UART1_RST_N_0: Assert the USART1 reset.
0x1: UART1_RST_N_1: Clear the USART1 reset.

UART2_RST_N

Bit 5: USART2 reset control..

Allowed values:
0: UART2_RST_N_0: Assert the USART2 reset.
0x1: UART2_RST_N_1: Clear the USART2 reset.

I2C0_RST_N

Bit 6: I2C0 reset control..

Allowed values:
0: I2C0_RST_N_0: Assert the I2C0 reset.
0x1: I2C0_RST_N_1: Clear the I2C0 reset.

MRT_RST_N

Bit 7: Multi-rate timer (MRT) reset control..

Allowed values:
0: MRT_RST_N_0: Assert the MRT reset.
0x1: MRT_RST_N_1: Clear the MRT reset.

SCT_RST_N

Bit 8: SCT reset control..

Allowed values:
0: SCT_RST_N_0: Assert the SCT reset.
0x1: SCT_RST_N_1: Clear the SCT reset.

WKT_RST_N

Bit 9: Self-wake-up timer (WKT) reset control..

Allowed values:
0: WKT_RST_N_0: Assert the WKT reset.
0x1: WKT_RST_N_1: Clear the WKT reset.

GPIO_RST_N

Bit 10: GPIO and GPIO pin interrupt reset control..

Allowed values:
0: GPIO_RST_N_0: Assert the GPIO reset.
0x1: GPIO_RST_N_1: Clear the GPIO reset.

FLASH_RST_N

Bit 11: Flash controller reset control..

Allowed values:
0: FLASH_RST_N_0: Assert the flash controller reset.
0x1: FLASH_RST_N_1: Clear the flash controller reset.

ACMP_RST_N

Bit 12: Analog comparator reset control..

Allowed values:
0: ACMP_RST_N_0: Assert the analog comparator reset.
0x1: ACMP_RST_N_1: Clear the analog comparator controller reset.

SYSPLLCTRL

PLL control

Offset: 0x8, reset: 0, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSEL
rw
MSEL
rw
Toggle Fields

MSEL

Bits 0-4: Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.

PSEL

Bits 5-6: Post divider ratio P. The division ratio is 2 x P..

Allowed values:
0: PSEL_0: P = 1
0x1: PSEL_1: P = 2
0x2: PSEL_2: P = 4
0x3: PSEL_3: P = 8

SYSPLLSTAT

PLL status

Offset: 0xc, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
r
Toggle Fields

LOCK

Bit 0: PLL0 lock indicator.

SYSOSCCTRL

system oscillator control

Offset: 0x20, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREQRANGE
rw
BYPASS
rw
Toggle Fields

BYPASS

Bit 0: Bypass system oscillator.

FREQRANGE

Bit 1: oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'.

WDTOSCCTRL

Watchdog oscillator control

Offset: 0x24, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREQSEL
rw
DIVSEL
rw
Toggle Fields

DIVSEL

Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64.

FREQSEL

Bits 5-8: Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz.

SYSRSTSTAT

System reset status register

Offset: 0x30, reset: 0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRST
rw
BOD
rw
WDT
rw
EXTRST
rw
POR
rw
Toggle Fields

POR

Bit 0: POR reset status..

Allowed values:
0: POR_0: No POR detected.
0x1: POR_1: POR detected. Writing a one clears this reset.

EXTRST

Bit 1: Status of the external RESET pin. External reset status..

Allowed values:
0: EXTRST_0: No reset event detected.
0x1: EXTRST_1: Reset detected. Writing a one clears this reset.

WDT

Bit 2: Status of the Watchdog reset..

Allowed values:
0: WDT_0: No WDT reset detected.
0x1: WDT_1: WDT reset detected. Writing a one clears this reset.

BOD

Bit 3: Status of the Brown-out detect reset..

Allowed values:
0: BOD_0: No BOD reset detected.
0x1: BOD_1: BOD reset detected. Writing a one clears this reset.

SYSRST

Bit 4: Status of the software system reset..

Allowed values:
0: SYSRST_0: No System reset detected.
0x1: SYSRST_1: System reset detected. Writing a one clears this reset.

SYSPLLCLKSEL

System PLL clock source select register

Offset: 0x40, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL
rw
Toggle Fields

SEL

Bits 0-1: System PLL clock source.

Allowed values:
0: IRC: IRC
0x1: SYSOSC: Crystal Oscillator (SYSOSC)
0x3: CLKIN: CLKIN. External clock input.

SYSPLLCLKUEN

System PLL clock source update enable register

Offset: 0x44, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA
rw
Toggle Fields

ENA

Bit 0: Enable system PLL clock source update.

Allowed values:
0: NO_CHANGE: no change
0x1: UPDATED: update clock source

MAINCLKSEL

Main clock source select

Offset: 0x70, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL
rw
Toggle Fields

SEL

Bits 0-1: Clock source for main clock..

Allowed values:
0: IRC: IRC Oscillator.
0x1: PLL_input: PLL input.
0x2: Watchdog: Watchdog oscillator.
0x3: PLL_output: PLL output.

MAINCLKUEN

Main clock source update enable

Offset: 0x74, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA
rw
Toggle Fields

ENA

Bit 0: Enable main clock source update..

Allowed values:
0: ENA_0: No change.
0x1: ENA_1: Update clock source.

SYSAHBCLKDIV

System clock divider

Offset: 0x78, reset: 0x1, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255..

SYSAHBCLKCTRL

System clock control

Offset: 0x80, reset: 0xDF, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACMP
rw
IOCON
rw
WWDT
rw
UART2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART1
rw
UART0
rw
CRC
rw
SPI1
rw
SPI0
rw
MRT
rw
WKT
rw
SCT
rw
SWM
rw
GPIO
rw
I2C0
rw
FLASH
rw
FLASHREG
rw
RAM0_1
rw
ROM
rw
SYS
rw
Toggle Fields

SYS

Bit 0: Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1..

ROM

Bit 1: Enables clock for ROM..

Allowed values:
0: ROM_0: Disable.
0x1: ROM_1: Enable.

RAM0_1

Bit 2: Enables clock for SRAM0 and SRAM1..

Allowed values:
0: RAM0_1_0: Disable.
0x1: RAM0_1_1: Enable.

FLASHREG

Bit 3: Enables clock for flash register interface..

Allowed values:
0: FLASHREG_0: Disable.
0x1: FLASHREG_1: Enable.

FLASH

Bit 4: Enables clock for flash..

Allowed values:
0: FLASH_0: Disable.
0x1: FLASH_1: Enable.

I2C0

Bit 5: Enables clock for I2C0..

Allowed values:
0: I2C0_0: Disable.
0x1: I2C0_1: Enable.

GPIO

Bit 6: Enables clock for GPIO port registers and GPIO pin interrupt registers..

Allowed values:
0: GPIO_0: Disable.
0x1: GPIO_1: Enable.

SWM

Bit 7: Enables clock for switch matrix..

Allowed values:
0: SWM_0: Disable.
0x1: SWM_1: Enable.

SCT

Bit 8: Enables clock for state configurable timer SCTimer/PWM..

Allowed values:
0: SCT_0: Disable.
0x1: SCT_1: Enable.

WKT

Bit 9: Enables clock for self-wake-up timer..

Allowed values:
0: WKT_0: Disable.
0x1: WKT_1: Enable.

MRT

Bit 10: Enables clock for multi-rate timer..

Allowed values:
0: MRT_0: Disable.
0x1: MRT_1: Enable.

SPI0

Bit 11: Enables clock for SPI0..

Allowed values:
0: SPI0_0: Disable.
0x1: SPI0_1: Enable.

SPI1

Bit 12: Enables clock for SPI1..

Allowed values:
0: SPI1_0: Disable.
0x1: SPI1_1: Enable.

CRC

Bit 13: Enables clock for CRC..

Allowed values:
0: CRC_0: Disable.
0x1: CRC_1: Enable.

UART0

Bit 14: Enables clock for USART0..

Allowed values:
0: UART0_0: Disable.
0x1: UART0_1: Enable.

UART1

Bit 15: Enables clock for USART1..

Allowed values:
0: UART1_0: Disable.
0x1: UART1_1: Enable.

UART2

Bit 16: Enables clock for USART2..

Allowed values:
0: UART2_0: Disable.
0x1: UART2_1: Enable.

WWDT

Bit 17: Enables clock for WWDT..

Allowed values:
0: WWDT_0: Disable.
0x1: WWDT_1: Enable.

IOCON

Bit 18: Enables clock for IOCON block..

Allowed values:
0: IOCON_0: Disable.
0x1: IOCON_1: Enable.

ACMP

Bit 19: Enables clock to analog comparator..

Allowed values:
0: ACMP_0: Disable.
0x1: ACMP_1: Enable.

UARTCLKDIV

USART clock divider

Offset: 0x94, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255..

CLKOUTSEL

CLKOUT clock source select

Offset: 0xe0, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL
rw
Toggle Fields

SEL

Bits 0-1: CLKOUT clock source..

Allowed values:
0: IRC: IRC oscillator
0x1: SYSOSC: Crystal oscillator (SYSOSC)
0x2: Watchdog: Watchdog oscillator
0x3: main_clk: Main clock

CLKOUTUEN

CLKOUT clock source update enable

Offset: 0xe4, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA
rw
Toggle Fields

ENA

Bit 0: Enable CLKOUT clock source update..

Allowed values:
0: ENA_0: No change
0x1: ENA_1: Update clock source

CLKOUTDIV

clock out divider

Offset: 0xe8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: CLKOUT clock divider values. 0: Disable CLKOUT clock divider 1: Divide by 1 to 255: Divide by 255.

UARTFRGDIV

USART common fractional generator divider value

Offset: 0xf0, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator..

UARTFRGMULT

USART common fractional generator divider value

Offset: 0xf4, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MULT
rw
Toggle Fields

MULT

Bits 0-7: Numerator of the fractional divider. MULT is equal to the programmed value..

EXTTRACECMD

External trace buffer command register

Offset: 0xfc, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
rw
START
rw
Toggle Fields

START

Bit 0: Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well..

STOP

Bit 1: Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well..

PIOPORCAP0

POR captured PIO status 0

Offset: 0x100, reset: 0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIOSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIOSTAT
r
Toggle Fields

PIOSTAT

Bits 0-17: State of PIO0_17 through PIO0_0 at power-on reset.

IOCONCLKDIV6

Peripheral clock 6 to the IOCON block for programmable glitch filter

Offset: 0x134, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV5

Peripheral clock 6 to the IOCON block for programmable glitch filter

Offset: 0x138, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV4

Peripheral clock 4 to the IOCON block for programmable glitch filter

Offset: 0x13c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV3

Peripheral clock 3 to the IOCON block for programmable glitch filter

Offset: 0x140, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV2

Peripheral clock 2 to the IOCON block for programmable glitch filter

Offset: 0x144, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV1

Peripheral clock 1 to the IOCON block for programmable glitch filter

Offset: 0x148, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

IOCONCLKDIV0

Peripheral clock 0 to the IOCON block for programmable glitch filter

Offset: 0x14c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-7: IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255..

BODCTRL

BOD control register

Offset: 0x150, reset: 0, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BODRSTENA
rw
BODINTVAL
rw
BODRSTLEV
rw
Toggle Fields

BODRSTLEV

Bits 0-1: BOD reset level.

Allowed values:
0x1: LEVEL_1: Level 1
0x2: LEVEL_2: Level 2
0x3: LEVEL_3: Level 3

BODINTVAL

Bits 2-3: BOD interrupt level.

Allowed values:
0x1: LEVEL_1: Level 1
0x2: LEVEL_2: Level 2
0x3: LEVEL_3: Level 3

BODRSTENA

Bit 4: BOD reset enable.

Allowed values:
0: DISABLE: Disable reset function.
0x1: ENABLE: Enable reset function.

SYSTCKCAL

System tick timer calibration register

Offset: 0x154, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL
rw
Toggle Fields

CAL

Bits 0-25: System tick timer calibration value..

IRQLATENCY

IRQ latency register

Offset: 0x170, reset: 0x10, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LATENCY
rw
Toggle Fields

LATENCY

Bits 0-7: 8-bit latency value..

NMISRC

NMI source selection register

Offset: 0x174, reset: 0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQN
rw
Toggle Fields

IRQN

Bits 0-4: The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1.

NMIEN

Bit 31: Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0..

PINTSEL[[0]]

Pin interrupt select registers N

Offset: 0x178, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[1]]

Pin interrupt select registers N

Offset: 0x17c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[2]]

Pin interrupt select registers N

Offset: 0x180, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[3]]

Pin interrupt select registers N

Offset: 0x184, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[4]]

Pin interrupt select registers N

Offset: 0x188, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[5]]

Pin interrupt select registers N

Offset: 0x18c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[6]]

Pin interrupt select registers N

Offset: 0x190, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

PINTSEL[[7]]

Pin interrupt select registers N

Offset: 0x194, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPIN
rw
Toggle Fields

INTPIN

Bits 0-5: Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17)..

STARTERP0

Start logic 0 pin wake-up enable register 0

Offset: 0x204, reset: 0, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINT7
rw
PINT6
rw
PINT5
rw
PINT4
rw
PINT3
rw
PINT2
rw
PINT1
rw
PINT0
rw
Toggle Fields

PINT0

Bit 0: GPIO pin interrupt 0 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT1

Bit 1: GPIO pin interrupt 1 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT2

Bit 2: GPIO pin interrupt 2 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT3

Bit 3: GPIO pin interrupt 3 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT4

Bit 4: GPIO pin interrupt 4 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT5

Bit 5: GPIO pin interrupt 5 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT6

Bit 6: GPIO pin interrupt 6 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PINT7

Bit 7: GPIO pin interrupt 7 wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

STARTERP1

Start logic 0 pin wake-up enable register 1

Offset: 0x214, reset: 0, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKT
rw
BOD
rw
WWDT
rw
I2C0
rw
USART2
rw
USART1
rw
USART0
rw
SPI1
rw
SPI0
rw
Toggle Fields

SPI0

Bit 0: SPI0 interrupt wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

SPI1

Bit 1: SPI1 interrupt wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

USART0

Bit 3: USART0 interrupt wake-up. Configure USART in synchronous slave mode..

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

USART1

Bit 4: USART1 interrupt wake-up. Configure USART in synchronous slave mode..

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

USART2

Bit 5: USART2 interrupt wake-up. Configure USART in synchronous slave mode..

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

I2C0

Bit 8: I2C0 interrupt wake-up..

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

WWDT

Bit 12: WWDT interrupt wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

BOD

Bit 13: BOD interrupt wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

WKT

Bit 15: Self-wake-up timer interrupt wake-up.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PDSLEEPCFG

Deep-sleep configuration register

Offset: 0x230, reset: 0xFFFF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTOSC_PD
rw
BOD_PD
rw
Toggle Fields

BOD_PD

Bit 3: BOD power-down control for Deep-sleep and Power-down mode.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

WDTOSC_PD

Bit 6: Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running..

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PDAWAKECFG

Wake-up configuration register

Offset: 0x234, reset: 0xEDF8, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACMP
rw
SYSPLL_PD
rw
WDTOSC_PD
rw
SYSOSC_PD
rw
BOD_PD
rw
FLASH_PD
rw
IRC_PD
rw
IRCOUT_PD
rw
Toggle Fields

IRCOUT_PD

Bit 0: IRC oscillator output wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

IRC_PD

Bit 1: IRC oscillator power-down wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

FLASH_PD

Bit 2: Flash wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

BOD_PD

Bit 3: BOD wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

SYSOSC_PD

Bit 5: Crystal oscillator wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

WDTOSC_PD

Bit 6: Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

SYSPLL_PD

Bit 7: System PLL wake-up configuration.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

ACMP

Bit 15: Analog comparator wake-up configuration.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

PDRUNCFG

Power configuration register

Offset: 0x238, reset: 0xEDF0, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACMP
rw
SYSPLL_PD
rw
WDTOSC_PD
rw
SYSOSC_PD
rw
BOD_PD
rw
FLASH_PD
rw
IRC_PD
rw
IRCOUT_PD
rw
Toggle Fields

IRCOUT_PD

Bit 0: IRC oscillator output wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

IRC_PD

Bit 1: IRC oscillator power-down wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

FLASH_PD

Bit 2: Flash wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

BOD_PD

Bit 3: BOD wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

SYSOSC_PD

Bit 5: Crystal oscillator wake-up configuration.

Allowed values:
0: POWERED: powered
0x1: POWERED_DOWN: powered down

WDTOSC_PD

Bit 6: Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

SYSPLL_PD

Bit 7: System PLL wake-up configuration.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

ACMP

Bit 15: Analog comparator wake-up configuration.

Allowed values:
0: DISABLED: Disabled
0x1: ENABLED: Enabled

DEVICE_ID

Part ID register

Offset: 0x3f8, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICEID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEVICEID
r
Toggle Fields

DEVICEID

Bits 0-31: Part ID.

USART0

0x40064000: USARTs

36/65 fields covered. Toggle Registers

Show register map

CFG

USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

Offset: 0x0, reset: 0, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP
rw
SYNCMST
rw
CLKPOL
rw
SYNCEN
rw
CTSEN
rw
STOPLEN
rw
PARITYSEL
rw
DATALEN
rw
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: USART Enable..

Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.

DATALEN

Bits 2-3: Selects the data size for the USART..

Allowed values:
0: BIT_7: 7 bit Data length.
0x1: BIT_8: 8 bit Data length.
0x2: BIT_9: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.

PARITYSEL

Bits 4-5: Selects what type of parity is used by the USART..

Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.

STOPLEN

Bit 6: Number of stop bits appended to transmitted data. Only a single stop bit is required for received data..

Allowed values:
0: BIT_1: 1 stop bit.
0x1: BITS_2: 2 stop bits. This setting should only be used for asynchronous communication.

CTSEN

Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..

Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.

SYNCEN

Bit 11: Selects synchronous or asynchronous operation..

Allowed values:
0: ASYNCHRONOUS_MODE: Asynchronous mode.
0x1: SYNCHRONOUS_MODE: Synchronous mode.

CLKPOL

Bit 12: Selects the clock polarity and sampling edge of received data in synchronous mode..

Allowed values:
0: FALLING_EDGE: Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0x1: RISING_EDGE: Rising edge. Un_RXD is sampled on the rising edge of SCLK.

SYNCMST

Bit 14: Synchronous mode Master select..

Allowed values:
0: SLAVE: Slave. When synchronous mode is enabled, the USART is a slave.
0x1: MASTER: Master. When synchronous mode is enabled, the USART is a master.

LOOP

Bit 15: Selects data loopback mode..

Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.

CTL

USART Control register. USART control settings that are more likely to change during operation.

Offset: 0x4, reset: 0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRCCONRX
rw
CC
rw
TXDIS
rw
ADDRDET
rw
TXBRKEN
rw
Toggle Fields

TXBRKEN

Bit 1: Break Enable..

Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.

ADDRDET

Bit 2: Enable address detect mode..

Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.

TXDIS

Bit 6: Transmit Disable..

Allowed values:
0: ENABLED: Not disabled. USART transmitter is not disabled.
0x1: DISABLED: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.

CC

Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..

Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).

CLRCCONRX

Bit 9: Clear Continuous Clock..

Allowed values:
0: NO_EFFECT: No effect. No effect on the CC bit.
0x1: AUTO_CLEAR: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.

STAT

USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

Offset: 0x8, reset: 0xE, access: read-write

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
w
PARITYERRINT
w
FRAMERRINT
w
START
w
DELTARXBRK
w
RXBRK
r
OVERRUNINT
w
TXDISSTAT
r
DELTACTS
w
CTS
r
TXIDLE
r
TXRDY
r
RXIDLE
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers..

RXIDLE

Bit 1: Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data..

TXRDY

Bit 2: Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register..

TXIDLE

Bit 3: Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data..

CTS

Bit 4: This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled..

DELTACTS

Bit 5: This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software..

TXDISSTAT

Bit 6: Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)..

OVERRUNINT

Bit 8: Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost..

RXBRK

Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs.Cleared by software..

START

Bit 12: This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software..

FRAMERRINT

Bit 13: Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERRINT

Bit 14: Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..

RXNOISEINT

Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..

INTENSET

Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Offset: 0xc, reset: 0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEEN
rw
PARITYERREN
rw
FRAMERREN
rw
STARTEN
rw
DELTARXBRKEN
rw
OVERRUNEN
rw
TXDISEN
rw
DELTACTSEN
rw
TXRDYEN
rw
RXRDYEN
rw
Toggle Fields

RXRDYEN

Bit 0: When 1, enables an interrupt when there is a received character available to be read from the RXDAT register..

TXRDYEN

Bit 2: When 1, enables an interrupt when the TXDAT register is available to take another character to transmit..

DELTACTSEN

Bit 5: When 1, enables an interrupt when there is a change in the state of the CTS input..

TXDISEN

Bit 6: When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details..

OVERRUNEN

Bit 8: When 1, enables an interrupt when an overrun error occurred..

DELTARXBRKEN

Bit 11: When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)..

STARTEN

Bit 12: When 1, enables an interrupt when a received start bit has been detected..

FRAMERREN

Bit 13: When 1, enables an interrupt when a framing error has been detected..

PARITYERREN

Bit 14: When 1, enables an interrupt when a parity error has been detected..

RXNOISEEN

Bit 15: When 1, enables an interrupt when noise is detected..

INTENCLR

Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

Offset: 0x10, reset: 0, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISECLR
w
PARITYERRCLR
w
FRAMERRCLR
w
STARTCLR
w
DELTARXBRKCLR
w
OVERRUNCLR
w
TXDISINTCLR
w
DELTACTSCLR
w
TXRDYCLR
w
RXRDYCLR
w
Toggle Fields

RXRDYCLR

Bit 0: Writing 1 clears the corresponding bit in the INTENSET register..

TXRDYCLR

Bit 2: Writing 1 clears the corresponding bit in the INTENSET register..

DELTACTSCLR

Bit 5: Writing 1 clears the corresponding bit in the INTENSET register..

TXDISINTCLR

Bit 6: Writing 1 clears the corresponding bit in the INTENSET register..

OVERRUNCLR

Bit 8: Writing 1 clears the corresponding bit in the INTENSET register..

DELTARXBRKCLR

Bit 11: Writing 1 clears the corresponding bit in the INTENSET register..

STARTCLR

Bit 12: Writing 1 clears the corresponding bit in the INTENSET register..

FRAMERRCLR

Bit 13: Writing 1 clears the corresponding bit in the INTENSET register..

PARITYERRCLR

Bit 14: Writing 1 clears the corresponding bit in the INTENSET register..

RXNOISECLR

Bit 15: Writing 1 clears the corresponding bit in the INTENSET register..

RXDAT

Receiver Data register. Contains the last character received.

Offset: 0x14, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

RXDATSTAT

Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.

Offset: 0x18, reset: 0, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISE
r
PARITYERR
r
FRAMERR
r
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

FRAMERR

Bit 13: Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERR

Bit 14: Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character..

RXNOISE

Bit 15: Received Noise flag..

TXDAT

Transmit Data register. Data to be transmitted is written here.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDAT
rw
Toggle Fields

TXDAT

Bits 0-8: Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0..

BRG

Baud Rate Generator register. 16-bit integer baud rate divisor value.

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRGVAL
rw
Toggle Fields

BRGVAL

Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..

INTSTAT

Interrupt status register. Reflects interrupts that are currently enabled.

Offset: 0x24, reset: 0x5, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
r
PARITYERRINT
r
FRAMERRINT
r
START
r
DELTARXBRK
r
OVERRUNINT
r
TXDISINT
r
DELTACTS
r
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag..

TXRDY

Bit 2: Transmitter Ready flag..

DELTACTS

Bit 5: This bit is set when a change in the state of the CTS input is detected..

TXDISINT

Bit 6: Transmitter Disabled Interrupt flag..

OVERRUNINT

Bit 8: Overrun Error interrupt flag..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs..

START

Bit 12: This bit is set when a start is detected on the receiver input..

FRAMERRINT

Bit 13: Framing Error interrupt flag..

PARITYERRINT

Bit 14: Parity Error interrupt flag..

RXNOISEINT

Bit 15: Received Noise interrupt flag..

USART1

0x40068000: USARTs

36/65 fields covered. Toggle Registers

Show register map

CFG

USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

Offset: 0x0, reset: 0, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP
rw
SYNCMST
rw
CLKPOL
rw
SYNCEN
rw
CTSEN
rw
STOPLEN
rw
PARITYSEL
rw
DATALEN
rw
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: USART Enable..

Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.

DATALEN

Bits 2-3: Selects the data size for the USART..

Allowed values:
0: BIT_7: 7 bit Data length.
0x1: BIT_8: 8 bit Data length.
0x2: BIT_9: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.

PARITYSEL

Bits 4-5: Selects what type of parity is used by the USART..

Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.

STOPLEN

Bit 6: Number of stop bits appended to transmitted data. Only a single stop bit is required for received data..

Allowed values:
0: BIT_1: 1 stop bit.
0x1: BITS_2: 2 stop bits. This setting should only be used for asynchronous communication.

CTSEN

Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..

Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.

SYNCEN

Bit 11: Selects synchronous or asynchronous operation..

Allowed values:
0: ASYNCHRONOUS_MODE: Asynchronous mode.
0x1: SYNCHRONOUS_MODE: Synchronous mode.

CLKPOL

Bit 12: Selects the clock polarity and sampling edge of received data in synchronous mode..

Allowed values:
0: FALLING_EDGE: Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0x1: RISING_EDGE: Rising edge. Un_RXD is sampled on the rising edge of SCLK.

SYNCMST

Bit 14: Synchronous mode Master select..

Allowed values:
0: SLAVE: Slave. When synchronous mode is enabled, the USART is a slave.
0x1: MASTER: Master. When synchronous mode is enabled, the USART is a master.

LOOP

Bit 15: Selects data loopback mode..

Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.

CTL

USART Control register. USART control settings that are more likely to change during operation.

Offset: 0x4, reset: 0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRCCONRX
rw
CC
rw
TXDIS
rw
ADDRDET
rw
TXBRKEN
rw
Toggle Fields

TXBRKEN

Bit 1: Break Enable..

Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.

ADDRDET

Bit 2: Enable address detect mode..

Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.

TXDIS

Bit 6: Transmit Disable..

Allowed values:
0: ENABLED: Not disabled. USART transmitter is not disabled.
0x1: DISABLED: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.

CC

Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..

Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).

CLRCCONRX

Bit 9: Clear Continuous Clock..

Allowed values:
0: NO_EFFECT: No effect. No effect on the CC bit.
0x1: AUTO_CLEAR: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.

STAT

USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

Offset: 0x8, reset: 0xE, access: read-write

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
w
PARITYERRINT
w
FRAMERRINT
w
START
w
DELTARXBRK
w
RXBRK
r
OVERRUNINT
w
TXDISSTAT
r
DELTACTS
w
CTS
r
TXIDLE
r
TXRDY
r
RXIDLE
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers..

RXIDLE

Bit 1: Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data..

TXRDY

Bit 2: Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register..

TXIDLE

Bit 3: Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data..

CTS

Bit 4: This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled..

DELTACTS

Bit 5: This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software..

TXDISSTAT

Bit 6: Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)..

OVERRUNINT

Bit 8: Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost..

RXBRK

Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs.Cleared by software..

START

Bit 12: This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software..

FRAMERRINT

Bit 13: Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERRINT

Bit 14: Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..

RXNOISEINT

Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..

INTENSET

Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Offset: 0xc, reset: 0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEEN
rw
PARITYERREN
rw
FRAMERREN
rw
STARTEN
rw
DELTARXBRKEN
rw
OVERRUNEN
rw
TXDISEN
rw
DELTACTSEN
rw
TXRDYEN
rw
RXRDYEN
rw
Toggle Fields

RXRDYEN

Bit 0: When 1, enables an interrupt when there is a received character available to be read from the RXDAT register..

TXRDYEN

Bit 2: When 1, enables an interrupt when the TXDAT register is available to take another character to transmit..

DELTACTSEN

Bit 5: When 1, enables an interrupt when there is a change in the state of the CTS input..

TXDISEN

Bit 6: When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details..

OVERRUNEN

Bit 8: When 1, enables an interrupt when an overrun error occurred..

DELTARXBRKEN

Bit 11: When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)..

STARTEN

Bit 12: When 1, enables an interrupt when a received start bit has been detected..

FRAMERREN

Bit 13: When 1, enables an interrupt when a framing error has been detected..

PARITYERREN

Bit 14: When 1, enables an interrupt when a parity error has been detected..

RXNOISEEN

Bit 15: When 1, enables an interrupt when noise is detected..

INTENCLR

Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

Offset: 0x10, reset: 0, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISECLR
w
PARITYERRCLR
w
FRAMERRCLR
w
STARTCLR
w
DELTARXBRKCLR
w
OVERRUNCLR
w
TXDISINTCLR
w
DELTACTSCLR
w
TXRDYCLR
w
RXRDYCLR
w
Toggle Fields

RXRDYCLR

Bit 0: Writing 1 clears the corresponding bit in the INTENSET register..

TXRDYCLR

Bit 2: Writing 1 clears the corresponding bit in the INTENSET register..

DELTACTSCLR

Bit 5: Writing 1 clears the corresponding bit in the INTENSET register..

TXDISINTCLR

Bit 6: Writing 1 clears the corresponding bit in the INTENSET register..

OVERRUNCLR

Bit 8: Writing 1 clears the corresponding bit in the INTENSET register..

DELTARXBRKCLR

Bit 11: Writing 1 clears the corresponding bit in the INTENSET register..

STARTCLR

Bit 12: Writing 1 clears the corresponding bit in the INTENSET register..

FRAMERRCLR

Bit 13: Writing 1 clears the corresponding bit in the INTENSET register..

PARITYERRCLR

Bit 14: Writing 1 clears the corresponding bit in the INTENSET register..

RXNOISECLR

Bit 15: Writing 1 clears the corresponding bit in the INTENSET register..

RXDAT

Receiver Data register. Contains the last character received.

Offset: 0x14, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

RXDATSTAT

Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.

Offset: 0x18, reset: 0, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISE
r
PARITYERR
r
FRAMERR
r
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

FRAMERR

Bit 13: Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERR

Bit 14: Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character..

RXNOISE

Bit 15: Received Noise flag..

TXDAT

Transmit Data register. Data to be transmitted is written here.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDAT
rw
Toggle Fields

TXDAT

Bits 0-8: Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0..

BRG

Baud Rate Generator register. 16-bit integer baud rate divisor value.

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRGVAL
rw
Toggle Fields

BRGVAL

Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..

INTSTAT

Interrupt status register. Reflects interrupts that are currently enabled.

Offset: 0x24, reset: 0x5, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
r
PARITYERRINT
r
FRAMERRINT
r
START
r
DELTARXBRK
r
OVERRUNINT
r
TXDISINT
r
DELTACTS
r
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag..

TXRDY

Bit 2: Transmitter Ready flag..

DELTACTS

Bit 5: This bit is set when a change in the state of the CTS input is detected..

TXDISINT

Bit 6: Transmitter Disabled Interrupt flag..

OVERRUNINT

Bit 8: Overrun Error interrupt flag..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs..

START

Bit 12: This bit is set when a start is detected on the receiver input..

FRAMERRINT

Bit 13: Framing Error interrupt flag..

PARITYERRINT

Bit 14: Parity Error interrupt flag..

RXNOISEINT

Bit 15: Received Noise interrupt flag..

USART2

0x4006c000: USARTs

36/65 fields covered. Toggle Registers

Show register map

CFG

USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

Offset: 0x0, reset: 0, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP
rw
SYNCMST
rw
CLKPOL
rw
SYNCEN
rw
CTSEN
rw
STOPLEN
rw
PARITYSEL
rw
DATALEN
rw
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: USART Enable..

Allowed values:
0: DISABLED: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1: ENABLED: Enabled. The USART is enabled for operation.

DATALEN

Bits 2-3: Selects the data size for the USART..

Allowed values:
0: BIT_7: 7 bit Data length.
0x1: BIT_8: 8 bit Data length.
0x2: BIT_9: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.

PARITYSEL

Bits 4-5: Selects what type of parity is used by the USART..

Allowed values:
0: NO_PARITY: No parity.
0x2: EVEN_PARITY: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3: ODD_PARITY: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.

STOPLEN

Bit 6: Number of stop bits appended to transmitted data. Only a single stop bit is required for received data..

Allowed values:
0: BIT_1: 1 stop bit.
0x1: BITS_2: 2 stop bits. This setting should only be used for asynchronous communication.

CTSEN

Bit 9: CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled..

Allowed values:
0: DISABLED: No flow control. The transmitter does not receive any automatic flow control signal.
0x1: ENABLED: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.

SYNCEN

Bit 11: Selects synchronous or asynchronous operation..

Allowed values:
0: ASYNCHRONOUS_MODE: Asynchronous mode.
0x1: SYNCHRONOUS_MODE: Synchronous mode.

CLKPOL

Bit 12: Selects the clock polarity and sampling edge of received data in synchronous mode..

Allowed values:
0: FALLING_EDGE: Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0x1: RISING_EDGE: Rising edge. Un_RXD is sampled on the rising edge of SCLK.

SYNCMST

Bit 14: Synchronous mode Master select..

Allowed values:
0: SLAVE: Slave. When synchronous mode is enabled, the USART is a slave.
0x1: MASTER: Master. When synchronous mode is enabled, the USART is a master.

LOOP

Bit 15: Selects data loopback mode..

Allowed values:
0: NORMAL: Normal operation.
0x1: LOOPBACK: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.

CTL

USART Control register. USART control settings that are more likely to change during operation.

Offset: 0x4, reset: 0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRCCONRX
rw
CC
rw
TXDIS
rw
ADDRDET
rw
TXBRKEN
rw
Toggle Fields

TXBRKEN

Bit 1: Break Enable..

Allowed values:
0: NORMAL: Normal operation.
0x1: CONTINOUS: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.

ADDRDET

Bit 2: Enable address detect mode..

Allowed values:
0: DISABLED: Disabled. The USART presents all incoming data.
0x1: ENABLED: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.

TXDIS

Bit 6: Transmit Disable..

Allowed values:
0: ENABLED: Not disabled. USART transmitter is not disabled.
0x1: DISABLED: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.

CC

Bit 8: Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode..

Allowed values:
0: CLOCK_ON_CHARACTER: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1: CONTINOUS_CLOCK: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).

CLRCCONRX

Bit 9: Clear Continuous Clock..

Allowed values:
0: NO_EFFECT: No effect. No effect on the CC bit.
0x1: AUTO_CLEAR: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.

STAT

USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

Offset: 0x8, reset: 0xE, access: read-write

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
w
PARITYERRINT
w
FRAMERRINT
w
START
w
DELTARXBRK
w
RXBRK
r
OVERRUNINT
w
TXDISSTAT
r
DELTACTS
w
CTS
r
TXIDLE
r
TXRDY
r
RXIDLE
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers..

RXIDLE

Bit 1: Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data..

TXRDY

Bit 2: Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register..

TXIDLE

Bit 3: Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data..

CTS

Bit 4: This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled..

DELTACTS

Bit 5: This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software..

TXDISSTAT

Bit 6: Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)..

OVERRUNINT

Bit 8: Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost..

RXBRK

Bit 10: Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs.Cleared by software..

START

Bit 12: This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software..

FRAMERRINT

Bit 13: Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERRINT

Bit 14: Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..

RXNOISEINT

Bit 15: Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception..

INTENSET

Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Offset: 0xc, reset: 0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEEN
rw
PARITYERREN
rw
FRAMERREN
rw
STARTEN
rw
DELTARXBRKEN
rw
OVERRUNEN
rw
TXDISEN
rw
DELTACTSEN
rw
TXRDYEN
rw
RXRDYEN
rw
Toggle Fields

RXRDYEN

Bit 0: When 1, enables an interrupt when there is a received character available to be read from the RXDAT register..

TXRDYEN

Bit 2: When 1, enables an interrupt when the TXDAT register is available to take another character to transmit..

DELTACTSEN

Bit 5: When 1, enables an interrupt when there is a change in the state of the CTS input..

TXDISEN

Bit 6: When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details..

OVERRUNEN

Bit 8: When 1, enables an interrupt when an overrun error occurred..

DELTARXBRKEN

Bit 11: When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)..

STARTEN

Bit 12: When 1, enables an interrupt when a received start bit has been detected..

FRAMERREN

Bit 13: When 1, enables an interrupt when a framing error has been detected..

PARITYERREN

Bit 14: When 1, enables an interrupt when a parity error has been detected..

RXNOISEEN

Bit 15: When 1, enables an interrupt when noise is detected..

INTENCLR

Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

Offset: 0x10, reset: 0, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISECLR
w
PARITYERRCLR
w
FRAMERRCLR
w
STARTCLR
w
DELTARXBRKCLR
w
OVERRUNCLR
w
TXDISINTCLR
w
DELTACTSCLR
w
TXRDYCLR
w
RXRDYCLR
w
Toggle Fields

RXRDYCLR

Bit 0: Writing 1 clears the corresponding bit in the INTENSET register..

TXRDYCLR

Bit 2: Writing 1 clears the corresponding bit in the INTENSET register..

DELTACTSCLR

Bit 5: Writing 1 clears the corresponding bit in the INTENSET register..

TXDISINTCLR

Bit 6: Writing 1 clears the corresponding bit in the INTENSET register..

OVERRUNCLR

Bit 8: Writing 1 clears the corresponding bit in the INTENSET register..

DELTARXBRKCLR

Bit 11: Writing 1 clears the corresponding bit in the INTENSET register..

STARTCLR

Bit 12: Writing 1 clears the corresponding bit in the INTENSET register..

FRAMERRCLR

Bit 13: Writing 1 clears the corresponding bit in the INTENSET register..

PARITYERRCLR

Bit 14: Writing 1 clears the corresponding bit in the INTENSET register..

RXNOISECLR

Bit 15: Writing 1 clears the corresponding bit in the INTENSET register..

RXDAT

Receiver Data register. Contains the last character received.

Offset: 0x14, reset: 0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

RXDATSTAT

Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.

Offset: 0x18, reset: 0, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISE
r
PARITYERR
r
FRAMERR
r
RXDAT
r
Toggle Fields

RXDAT

Bits 0-8: The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings..

FRAMERR

Bit 13: Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source..

PARITYERR

Bit 14: Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character..

RXNOISE

Bit 15: Received Noise flag..

TXDAT

Transmit Data register. Data to be transmitted is written here.

Offset: 0x1c, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDAT
rw
Toggle Fields

TXDAT

Bits 0-8: Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0..

BRG

Baud Rate Generator register. 16-bit integer baud rate divisor value.

Offset: 0x20, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRGVAL
rw
Toggle Fields

BRGVAL

Bits 0-15: This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function..

INTSTAT

Interrupt status register. Reflects interrupts that are currently enabled.

Offset: 0x24, reset: 0x5, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNOISEINT
r
PARITYERRINT
r
FRAMERRINT
r
START
r
DELTARXBRK
r
OVERRUNINT
r
TXDISINT
r
DELTACTS
r
TXRDY
r
RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready flag..

TXRDY

Bit 2: Transmitter Ready flag..

DELTACTS

Bit 5: This bit is set when a change in the state of the CTS input is detected..

TXDISINT

Bit 6: Transmitter Disabled Interrupt flag..

OVERRUNINT

Bit 8: Overrun Error interrupt flag..

DELTARXBRK

Bit 11: This bit is set when a change in the state of receiver break detection occurs..

START

Bit 12: This bit is set when a start is detected on the receiver input..

FRAMERRINT

Bit 13: Framing Error interrupt flag..

PARITYERRINT

Bit 14: Parity Error interrupt flag..

RXNOISEINT

Bit 15: Received Noise interrupt flag..

WKT

0x40008000: Wake Up Timer(WKT)

3/4 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
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17
16
15
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12
11
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9
8
7
6
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4
3
2
1
0
0x0 CTRL
0xc COUNT

CTRL

Self wake-up timer control register.

Offset: 0x0, reset: 0, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLEARCTR
rw
ALARMFLAG
rw
CLKSEL
rw
Toggle Fields

CLKSEL

Bit 0: Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set..

Allowed values:
0: DIVIDED_IRC_CLOCK: Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes.
0x1: LOW_POWER_CLOCK: This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.

ALARMFLAG

Bit 1: Wake-up or alarm timer flag..

Allowed values:
0: NO_TIME_OUT: No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.
0x1: TIME_OUT: Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit.

CLEARCTR

Bit 2: Clears the self wake-up timer..

Allowed values:
0: NO_EFFECT: No effect. Reading this bit always returns 0.
0x1: CLEAR_THE_COUNTER: Clear the counter. Counting is halted until a new count value is loaded.

COUNT

Counter register.

Offset: 0xc, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
rw
Toggle Fields

VALUE

Bits 0-31: A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer..

WWDT

0x40000000: Windowed Watchdog Timer (WWDT)

4/11 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
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15
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7
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4
3
2
1
0
0x0 MOD
0x4 TC
0x8 FEED
0xc TV
0x14 WARNINT
0x18 WINDOW

MOD

Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.

Offset: 0x0, reset: 0, access: read-write

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw
WDPROTECT
rw
WDINT
rw
WDTOF
rw
WDRESET
rw
WDEN
rw
Toggle Fields

WDEN

Bit 0: Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently..

Allowed values:
0: STOP: Stop. The watchdog timer is stopped.
0x1: RUN: Run. The watchdog timer is running.

WDRESET

Bit 1: Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0..

Allowed values:
0: INTERRUPT: Interrupt. A watchdog time-out will not cause a chip reset.
0x1: RESET: Reset. A watchdog time-out will cause a chip reset.

WDTOF

Bit 2: Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1..

WDINT

Bit 3: Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0..

WDPROTECT

Bit 4: Watchdog update mode. This bit can be set once by software and is only cleared by a reset..

Allowed values:
0: FLEXIBLE: Flexible. The watchdog time-out value (TC) can be changed at any time.
0x1: THRESHOLD: Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.

LOCK

Bit 5: Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset..

TC

Watchdog timer constant register. This 24-bit register determines the time-out value.

Offset: 0x4, reset: 0xFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
rw
Toggle Fields

COUNT

Bits 0-23: Watchdog time-out value..

FEED

Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.

Offset: 0x8, reset: 0, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEED
w
Toggle Fields

FEED

Bits 0-7: Feed value should be 0xAA followed by 0x55..

TV

Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.

Offset: 0xc, reset: 0xFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle Fields

COUNT

Bits 0-23: Counter timer value..

WARNINT

Watchdog Warning Interrupt compare value.

Offset: 0x14, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WARNINT
rw
Toggle Fields

WARNINT

Bits 0-9: Watchdog warning interrupt compare value..

WINDOW

Watchdog Window compare value.

Offset: 0x18, reset: 0xFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WINDOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WINDOW
rw
Toggle Fields

WINDOW

Bits 0-23: Watchdog window value..