EDGESEL

Bits 3-4: This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):.

Allowed values:
0: FALLING_EDGES: Falling edges
0x1: RISING_EDGES: Rising edges
0x2: BOTH_EDGES0: Both edges
0x3: BOTH_EDGES1: Both edges

COMPSA

Bit 6: Comparator output control.

Allowed values:
0: COMPSA_0: Comparator output is used directly.
0x1: COMPSA_1: Comparator output is synchronized to the bus clock for output to other modules.

COMP_VP_SEL

Bits 8-10: Selects positive voltage input.

Allowed values:
0: VOLTAGE_LADDER_OUTPUT: VOLTAGE_LADDER_OUTPUT
0x1: ACMP_I1: ACMP_I1
0x2: ACMP_I2: ACMP_I2
0x3: ACMP_I3: ACMP_I3
0x4: ACMP_I4: ACMP_I4
0x5: ACMP_I5: ACMP_I5
0x6: BAND_GAP: Band gap. Internal reference voltage.
0x7: DACOUT0: DAC0 output

COMP_VM_SEL

Bits 11-13: Selects negative voltage input.

Allowed values:
0: VOLTAGE_LADDER_OUTPUT: VOLTAGE_LADDER_OUTPUT
0x1: ACMP_I1: ACMP_I1
0x2: ACMP_I2: ACMP_I2
0x3: ACMP_I3: ACMP_I3
0x4: ACMP_I4: ACMP_I4
0x5: ACMP_I5: ACMP_I5
0x6: BAND_GAP: Band gap. Internal reference voltage.
0x7: DACOUT0: DAC0 output

EDGECLR

Bit 20: Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0..

COMPSTAT

Bit 21: Comparator status. This bit reflects the state of the comparator output..

COMPEDGE

Bit 23: Comparator edge-detect status..

HYS

Bits 25-26: Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output..

Allowed values:
0: HYS_0: None (the output will switch as the voltages cross)
0x1: HYS_1: 5 mv
0x2: HYS_2: 10 mv
0x3: HYS_3: 20 mv

LADEN

Bit 0: Voltage ladder enable.

LADSEL

Bits 1-5: Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref.

LADREF

Bit 6: Selects the reference voltage Vref for the voltage ladder..

Allowed values:
0: LADREF_0: Supply pin VDD
0x1: LADREF_1: VDDCMP pin

CRC_POLY

Bits 0-1: CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial.

BIT_RVS_WR

Bit 2: Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte).

CMPL_WR

Bit 3: Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA.

BIT_RVS_SUM

Bit 4: CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM.

CMPL_SUM

Bit 5: CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM.

CRC_SEED

Bits 0-31: A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses..

CRC_SUM

Bits 0-31: The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes..

CRC_WR_DATA

Bits 0-31: Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions..

FLASHTIM

Bits 0-1: Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access..

Allowed values:
0: ONE_SYSTEM_CLOCK_FLASH_ACCESS: 1 system clock flash access time.
0x1: TWO_SYSTEM_CLOCK_FLASH_ACCESS: 2 system clock flash access time.
0x2: THREE_SYSTEM_CLOCK_FLASH_ACCESS: 3 system clock flash access time.

START

Bits 0-16: Signature generation start address (corresponds to AHB byte address bits[18:2])..

STOPA

Bits 0-16: Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes..

STRTBIST

Bit 31: When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared..

SIG

Bits 0-31: 32-bit signature..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PBYTE

Bit 0: Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

PWORD

Bits 0-31: Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package..

DIRP

Bits 0-17: Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output..

MASKP

Bits 0-17: Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected..

PORT

Bits 0-17: Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit..

MPORTP

Bits 0-17: Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0..

SETP

Bits 0-17: Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit..

CLRP

Bits 0-17: Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit..

NOTP

Bits 0-17: Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit..

MSTEN

Bit 0: Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C Master function is disabled.
0x1: ENABLED: Enabled. The I2C Master function is enabled.

SLVEN

Bit 1: Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C slave function is disabled.
0x1: ENABLED: Enabled. The I2C slave function is enabled.

MONEN

Bit 2: Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset..

Allowed values:
0: DISABLED: Disabled. The I2C Monitor function is disabled.
0x1: ENABLED: Enabled. The I2C Monitor function is enabled.

TIMEOUTEN

Bit 3: I2C bus Time-out Enable. When disabled, the time-out function is internally reset..

Allowed values:
0: DISABLED: Disabled. Time-out function is disabled.
0x1: ENABLED: Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.

MONCLKSTR

Bit 4: Monitor function Clock Stretching..

Allowed values:
0: DISABLED: Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1: ENABLED: Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.

MSTPENDING

Bit 0: Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt..

Allowed values:
0: IN_PROGRESS: In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1: PENDING: Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.

MSTSTATE

Bits 1-3: Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses..

Allowed values:
0: IDLE: Idle. The Master function is available to be used for a new transaction.
0x1: RECEIVE_READY: Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2: TRANSMIT_READY: Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3: NACK_ADDRESS: NACK Address. Slave NACKed address.
0x4: NACK_DATA: NACK Data. Slave NACKed transmitted data.

MSTARBLOSS

Bit 4: Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..

Allowed values:
0: NO_LOSS: No Arbitration Loss has occurred.
0x1: ARBITRATION_LOSS: Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.

MSTSTSTPERR

Bit 6: Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE..

Allowed values:
0: NO_ERROR: No Start/Stop Error has occurred.
0x1: ERROR: The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.

SLVPENDING

Bit 8: Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched..

Allowed values:
0: IN_PROGRESS: In progress. The Slave function does not currently need service.
0x1: PENDING: Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.

SLVSTATE

Bits 9-10: Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes..

Allowed values:
0: SLAVE_ADDRESS: Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1: SLAVE_RECEIVE: Slave receive. Received data is available (Slave Receiver mode).
0x2: SLAVE_TRANSMIT: Slave transmit. Data can be transmitted (Slave Transmitter mode).

SLVNOTSTR

Bit 11: Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time..

Allowed values:
0: STRETCHING: Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1: NOT_STRETCHING: Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.

SLVIDX

Bits 12-13: Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here..

Allowed values:
0: ADDRESS0: Address 0. Slave address 0 was matched.
0x1: ADDRESS1: Address 1. Slave address 1 was matched.
0x2: ADDRESS2: Address 2. Slave address 2 was matched.
0x3: ADDRESS3: Address 3. Slave address 3 was matched.

SLVSEL

Bit 14: Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data..

Allowed values:
0: NOT_SELECTED: Not selected. The Slave function is not currently selected.
0x1: SELECTED: Selected. The Slave function is currently selected.

SLVDESEL

Bit 15: Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit..

Allowed values:
0: NOT_DESELECTED: Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1: DESELECTED: Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.

MONRDY

Bit 16: Monitor Ready. This flag is cleared when the MONRXDAT register is read..

Allowed values:
0: NO_DATA: No data. The Monitor function does not currently have data available.
0x1: DATA_WAITING: Data waiting. The Monitor function has data waiting to be read.

MONOV

Bit 17: Monitor Overflow flag..

Allowed values:
0: NO_OVERRUN: No overrun. Monitor data has not overrun.
0x1: OVERRUN: Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.

MONACTIVE

Bit 18: Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop..

Allowed values:
0: INACTIVE: Inactive. The Monitor function considers the I2C bus to be inactive.
0x1: ACTIVE: Active. The Monitor function considers the I2C bus to be active.

MONIDLE

Bit 19: Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit..

Allowed values:
0: NOT_IDLE: Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1: IDLE: Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.

EVENTTIMEOUT

Bit 24: Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle..

Allowed values:
0: NO_TIMEOUT: No time-out. I2C bus events have not caused a time-out.
0x1: EVEN_TIMEOUT: Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.

SCLTIMEOUT

Bit 25: SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit..

Allowed values:
0: NO_TIMEOUT: No time-out. SCL low time has not caused a time-out.
0x1: TIMEOUT: Time-out. SCL low time has caused a time-out.

MSTPENDINGEN

Bit 0: Master Pending interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstPending interrupt is disabled.
0x1: ENABLED: Enabled. The MstPending interrupt is enabled.

MSTARBLOSSEN

Bit 4: Master Arbitration Loss interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstArbLoss interrupt is disabled.
0x1: ENABLED: Enabled. The MstArbLoss interrupt is enabled.

MSTSTSTPERREN

Bit 6: Master Start/Stop Error interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MstStStpErr interrupt is disabled.
0x1: ENABLED: Enabled. The MstStStpErr interrupt is enabled.

SLVPENDINGEN

Bit 8: Slave Pending interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvPending interrupt is disabled.
0x1: ENABLED: Enabled. The SlvPending interrupt is enabled.

SLVNOTSTREN

Bit 11: Slave Not Stretching interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvNotStr interrupt is disabled.
0x1: ENABLED: Enabled. The SlvNotStr interrupt is enabled.

SLVDESELEN

Bit 15: Slave Deselect interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SlvDeSel interrupt is disabled.
0x1: ENABLED: Enabled. The SlvDeSel interrupt is enabled.

MONRDYEN

Bit 16: Monitor data Ready interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonRdy interrupt is disabled.
0x1: ENABLED: Enabled. The MonRdy interrupt is enabled.

MONOVEN

Bit 17: Monitor Overrun interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonOv interrupt is disabled.
0x1: ENABLED: Enabled. The MonOv interrupt is enabled.

MONIDLEEN

Bit 19: Monitor Idle interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The MonIdle interrupt is disabled.
0x1: ENABLED: Enabled. The MonIdle interrupt is enabled.

EVENTTIMEOUTEN

Bit 24: Event time-out interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The Event time-out interrupt is disabled.
0x1: ENABLED: Enabled. The Event time-out interrupt is enabled.

SCLTIMEOUTEN

Bit 25: SCL time-out interrupt Enable..

Allowed values:
0: DISABLED: Disabled. The SCL time-out interrupt is disabled.
0x1: ENABLED: Enabled. The SCL time-out interrupt is enabled.

MSTPENDINGCLR

Bit 0: Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented..

MSTARBLOSSCLR

Bit 4: Master Arbitration Loss interrupt clear..

MSTSTSTPERRCLR

Bit 6: Master Start/Stop Error interrupt clear..

SLVPENDINGCLR

Bit 8: Slave Pending interrupt clear..

SLVNOTSTRCLR

Bit 11: Slave Not Stretching interrupt clear..

SLVDESELCLR

Bit 15: Slave Deselect interrupt clear..

MONRDYCLR

Bit 16: Monitor data Ready interrupt clear..

MONOVCLR

Bit 17: Monitor Overrun interrupt clear..

MONIDLECLR

Bit 19: Monitor Idle interrupt clear..

EVENTTIMEOUTCLR

Bit 24: Event time-out interrupt clear..

SCLTIMEOUTCLR

Bit 25: SCL time-out interrupt clear..

TOMIN

Bits 0-3: Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks..

TO

Bits 4-15: Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock..

DIVVAL

Bits 0-15: This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use..

MSTPENDING

Bit 0: Master Pending..

MSTARBLOSS

Bit 4: Master Arbitration Loss flag..

MSTSTSTPERR

Bit 6: Master Start/Stop Error flag..

SLVPENDING

Bit 8: Slave Pending..

SLVNOTSTR

Bit 11: Slave Not Stretching status..

SLVDESEL

Bit 15: Slave Deselected flag..

MONRDY

Bit 16: Monitor Ready..

MONOV

Bit 17: Monitor Overflow flag..

MONIDLE

Bit 19: Monitor Idle flag..

EVENTTIMEOUT

Bit 24: Event time-out Interrupt flag..

SCLTIMEOUT

Bit 25: SCL time-out Interrupt flag..

MSTCONTINUE

Bit 0: Master Continue..

Allowed values:
0: NO_EFFECT: No effect.
0x1: Continue: Informs the Master function to continue to the next operation.

MSTSTART

Bit 1: Master Start control..

Allowed values:
0: NO_EFFECT: No effect.
0x1: START: Start. A Start will be generated on the I2C bus at the next allowed time.

MSTSTOP

Bit 2: Master Stop control..

Allowed values:
0: NO_EFFECT: No effect.
0x1: STOP: Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).

MSTSCLLOW

Bits 0-2: Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW..

Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2: CLOCKS_4: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.

MSTSCLHIGH

Bits 4-6: Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH..

Allowed values:
0: CLOCKS_2: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1: CLOCKS_3: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2: CLOCKS_4: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3: CLOCKS_5: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4: CLOCKS_6: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5: CLOCKS_7: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6: CLOCKS_8: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7: CLOCKS_9: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.

DATA

Bits 0-7: Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function..

SLVCONTINUE

Bit 0: Slave Continue..

Allowed values:
0: NO_EFFECT: No effect.
0x1: Continue: Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.

SLVNACK

Bit 1: Slave NACK..

Allowed values:
0: NO_EFFECT: No effect.
0x1: NACK: NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).

DATA

Bits 0-7: Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function..