nxp.com LPC54628 1.0 LPC54628J512ET180 Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause CM4 r0p1 little true true true 3 false 8 32 SYSCON LPC5460x System configuration (SYSCON) SYSCON 0x40000000 0 0x20048 registers AHBMATPRIO AHB multilayer matrix priority control 0x10 32 read-write 0 0x3FFFFFF PRI_ICODE I-Code bus priority. 0 2 read-write PRI_DCODE D-Code bus priority. 2 2 read-write PRI_SYS System bus priority. 4 2 read-write PRI_DMA DMA controller priority. 6 4 read-write PRI_ETH Ethernet DMA priority. 10 2 read-write PRI_LCD LCD DMA priority. 12 2 read-write PRI_USB0 USB0 DMA priority. 14 2 read-write PRI_USB1 USB1 DMA priority. 16 2 read-write PRI_SDIO SDIO priority. 18 2 read-write PRI_MCAN1 MCAN1 priority. 20 2 read-write PRI_MCAN2 MCAN2 priority. 22 2 read-write PRI_SHA SHA priority. 24 2 read-write SYSTCKCAL System tick counter calibration 0x40 32 read-write 0 0x3FFFFFF CAL System tick timer calibration value. 0 24 read-write SKEW Initial value for the Systick timer. 24 1 read-write NOREF Initial value for the Systick timer. 25 1 read-write NMISRC NMI Source Select 0x48 32 read-write 0 0xC0003F3F IRQM4 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4. 0 6 read-write NMIENM4 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. 31 1 read-write ASYNCAPBCTRL Asynchronous APB Control 0x4C 32 read-write 0x1 0x1 ENABLE Enables the asynchronous APB bridge and subsystem. 0 1 read-write DISABLED Disabled. Asynchronous APB bridge is disabled. 0 ENABLED Enabled. Asynchronous APB bridge is enabled. 0x1 2 0x4 PIOPORCAP[%s] POR captured value of port n 0xC0 32 read-only 0 0xFFFFFFFF PIOPORCAP State of PIOn_31 through PIOn_0 at power-on reset 0 32 read-only 2 0x4 PIORESCAP[%s] Reset captured value of port n 0xD0 32 read-only 0 0xFFFFFFFF PIORESCAP State of PIOn_31 through PIOn_0 for resets other than POR. 0 32 read-only PRESETCTRL0 Peripheral reset control n 0x100 32 read-write 0 0x87FEF80 FLASH_RST Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 7 1 read-write FMC_RST Flash accelerator reset control. Note that the FMC must not be reset while executing from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function. 8 1 read-write EEPROM_RST EEPROM reset control. 9 1 read-write SPIFI_RST SPIFI reset control. 10 1 read-write MUX_RST Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 11 1 read-write IOCON_RST IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 13 1 read-write GPIO0_RST GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 14 1 read-write GPIO1_RST GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 15 1 read-write GPIO2_RST GPIO2 reset control. 16 1 read-write GPIO3_RST GPIO3 reset control. 17 1 read-write PINT_RST Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 18 1 read-write GINT_RST Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 19 1 read-write DMA0_RST DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 20 1 read-write CRC_RST CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 21 1 read-write WWDT_RST Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 22 1 read-write ADC0_RST ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 27 1 read-write PRESETCTRL1 Peripheral reset control n 0x104 32 read-write 0 0xE4FFD85 MRT_RST Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 1 read-write SCT0_RST State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 2 1 read-write MCAN0_RST 0 = Clear reset to this function. 7 1 read-write MCAN1_RST 0 = Clear reset to this function. 8 1 read-write UTICK_RST Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 10 1 read-write FC0_RST Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 11 1 read-write FC1_RST Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 12 1 read-write FC2_RST Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 13 1 read-write FC3_RST Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 14 1 read-write FC4_RST Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 15 1 read-write FC5_RST Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 16 1 read-write FC6_RST Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 17 1 read-write FC7_RST Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 18 1 read-write DMIC_RST Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 19 1 read-write CTIMER2_RST CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function 22 1 read-write USB0D_RST USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 25 1 read-write CTIMER0_RST CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 26 1 read-write CTIMER1_RST CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 27 1 read-write PRESETCTRL2 Peripheral reset control n 0x108 32 read-write 0 0xE4FFD85 LCD_RST LCD reset control. 2 1 read-write SDIO_RST SDIO reset control. 3 1 read-write USB1H_RST USB1 Host reset control. 4 1 read-write USB1D_RST USB1 Device reset control. 5 1 read-write USB1RAM_RST USB1 RAM reset control. 6 1 read-write EMC_RESET EMC reset control. 7 1 read-write ETH_RST Ethernet reset control. 8 1 read-write GPIO4_RST GPIO4 reset control. 9 1 read-write GPIO5_RST GPIO5 reset control. 10 1 read-write AES_RST AES reset control. 11 1 read-write OTP_RST OTP reset control. 12 1 read-write RNG_RST RNG reset control. 13 1 read-write FC8_RST Flexcomm 8 reset control. 14 1 read-write FC9_RST Flexcomm 9 reset control. 15 1 read-write USB0HMR_RST USB0 HOST master reset control. 16 1 read-write USB0HSL_RST USB0 HOST slave reset control. 17 1 read-write SHA_RST SHA reset control. 18 1 read-write SC0_RST Smart card 0 reset control. 19 1 read-write SC1_RST Smart card 1 reset control. 20 1 read-write 3 0x4 PRESETCTRLSET[%s] Set bits in PRESETCTRLn 0x120 32 write-only 0 0xFFFFFFFF RST_SET Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them. 0 32 write-only 3 0x4 PRESETCTRLCLR[%s] Clear bits in PRESETCTRLn 0x140 32 write-only 0 0xFFFFFFFF RST_CLR Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them. 0 32 write-only SYSRSTSTAT System reset status register 0x1F0 32 read-write 0 0x1F POR POR reset status 0 1 read-write NO_POR_DETECTED No POR detected 0 POR_DETECTED POR detected. Writing a one clears this reset. 0x1 EXTRST Status of the external RESET pin. External reset status 1 1 read-write NO_RESET_DETECTED No reset event detected. 0 RESET_DETECTED Reset detected. Writing a one clears this reset. 0x1 WDT Status of the Watchdog reset 2 1 read-write NO_WDT_RESET_DETECTED No WDT reset detected 0 WDT_RESET_DETECTED WDT reset detected. Writing a one clears this reset. 0x1 BOD Status of the Brown-out detect reset 3 1 read-write NO_BOD_RESET_DETECTED No BOD reset detected 0 BOD_RESET_DETECTED BOD reset detected. Writing a one clears this reset. 0x1 SYSRST Status of the software system reset 4 1 read-write NO_SYSTEM_RESET_DETECTED No System reset detected 0 SYSTEM_RESET_DETECTED System reset detected. Writing a one clears this reset. 0x1 AHBCLKCTRL0 AHB Clock control n 0x200 32 read-write 0x183 0xFFFFFFFF ROM Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. 1 1 read-write SRAM1 Enables the clock for SRAM1. 0 = Disable; 1 = Enable. 3 1 read-write SRAM2 Enables the clock for SRAM2. 0 = Disable; 1 = Enable. 4 1 read-write SRAM3 Enables the clock for SRAM3. 5 1 read-write FLASH Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming, not for flash read. 7 1 read-write FMC Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read. 8 1 read-write EEPROM Enables the clock for EEPROM. 9 1 read-write SPIFI Enables the clock for the SPIFI. 0 = Disable; 1 = Enable. 10 1 read-write INPUTMUX Enables the clock for the input muxes. 0 = Disable; 1 = Enable. 11 1 read-write IOCON Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. 13 1 read-write GPIO0 Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. 14 1 read-write GPIO1 Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. 15 1 read-write GPIO2 Enables the clock for the GPIO2 port registers. 16 1 read-write GPIO3 Enables the clock for the GPIO3 port registers. 17 1 read-write PINT Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. 18 1 read-write GINT Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. 19 1 read-write DMA Enables the clock for the DMA controller. 0 = Disable; 1 = Enable. 20 1 read-write CRC Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. 21 1 read-write WWDT Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. 22 1 read-write RTC Enables the bus clock for the RTC. 0 = Disable; 1 = Enable. 23 1 read-write ADC0 Enables the clock for the ADC0 register interface. 27 1 read-write AHBCLKCTRL1 AHB Clock control n 0x204 32 read-write 0 0xE4FFD87 MRT Enables the clock for the Multi-Rate Timer. 0 1 read-write RIT Enables the clock for the Repetitive Interrupt Timer. 1 1 read-write SCT0 Enables the clock for SCT0. 2 1 read-write MCAN0 Enables the clock for MCAN0. 7 1 read-write MCAN1 Enables the clock for MCAN1. 8 1 read-write UTICK Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. 10 1 read-write FLEXCOMM0 Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable. 11 1 read-write FLEXCOMM1 Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable. 12 1 read-write FLEXCOMM2 Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable. 13 1 read-write FLEXCOMM3 Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable. 14 1 read-write FLEXCOMM4 Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable. 15 1 read-write FLEXCOMM5 Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable. 16 1 read-write FLEXCOMM6 Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable. 17 1 read-write FLEXCOMM7 Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable. 18 1 read-write DMIC Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable. 19 1 read-write CTIMER2 Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable. 22 1 read-write USB0D Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable. 25 1 read-write CTIMER0 Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable. 26 1 read-write CTIMER1 Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. 27 1 read-write AHBCLKCTRL2 AHB Clock control n 0x208 32 read-write 0 0xE4FFD87 LCD Enables the clock for the LCD interface. 2 1 read-write SDIO Enables the clock for the SDIO interface. 3 1 read-write USB1H Enables the clock for the USB1 host interface. 4 1 read-write USB1D Enables the clock for the USB1 device interface. 5 1 read-write USB1RAM Enables the clock for the USB1 RAM interface. 6 1 read-write EMC Enables the clock for the EMC interface. 7 1 read-write ETH Enables the clock for the ethernet interface. 8 1 read-write GPIO4 Enables the clock for the GPIO4 interface. 9 1 read-write GPIO5 Enables the clock for the GPIO5 interface. 10 1 read-write AES Enables the clock for the AES interface. 11 1 read-write OTP Enables the clock for the OTP interface. 12 1 read-write RNG Enables the clock for the RNG interface. 13 1 read-write FLEXCOMM8 Enables the clock for the Flexcomm8 interface. 14 1 read-write FLEXCOMM9 Enables the clock for the Flexcomm9 interface. 15 1 read-write USB0HMR Enables the clock for the USB host master interface. 16 1 read-write USB0HSL Enables the clock for the USB host slave interface. 17 1 read-write SHA0 Enables the clock for the SHA interface. 18 1 read-write SC0 Enables the clock for the Smart card0 interface. 19 1 read-write SC1 Enables the clock for the Smart card1 interface. 20 1 read-write 3 0x4 AHBCLKCTRLSET[%s] Set bits in AHBCLKCTRLn 0x220 32 write-only 0 0xFFFFFFFF CLK_SET Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them. 0 32 write-only 3 0x4 AHBCLKCTRLCLR[%s] Clear bits in AHBCLKCTRLn 0x240 32 write-only 0 0xFFFFFFFF CLK_CLR Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them. 0 32 write-only MAINCLKSELA Main clock source select A 0x280 32 read-write 0 0x3 SEL Clock source for main clock source selector A 0 2 read-write FRO_12_MHZ FRO 12 MHz (fro_12m) 0 CLKIN CLKIN (clk_in) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator (wdt_clk) 0x2 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x3 MAINCLKSELB Main clock source select B 0x284 32 read-write 0 0x3 SEL Clock source for main clock source selector B. Selects the clock source for the main clock. 0 2 read-write MAINCLKSELA MAINCLKSELA. Use the clock source selected in MAINCLKSELA register. 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x2 RTC_OSC_OUTPUT RTC oscillator 32 kHz output (32k_clk) 0x3 CLKOUTSELA CLKOUT clock source select A 0x288 32 read-write 0x7 0x7 SEL CLKOUT clock source selection 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 CLKIN CLKIN (clk_in) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator (wdt_clk) 0x2 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x3 SYSTEM_PLL_OUTPUT PLL output (pll_clk) 0x4 USB_PLL_CLOCK USB PLL clock (usb_pll_clk) 0x5 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x6 RTC_OSC_OUTPUT RTC oscillator 32 kHz output (32k_clk) 0x7 SYSPLLCLKSEL PLL clock source select 0x290 32 read-write 0 0x7 SEL System PLL clock source selection. 0 3 read-write FRO_12_MHZ FRO 12 MHz (fro_12m) 0 CLKIN CLKIN (clk_in) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator (wdt_clk) 0x2 RTC_OSC_OUTPUT RTC oscillator 32 kHz output (32k_clk) 0x3 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 AUDPLLCLKSEL Audio PLL clock source select 0x298 32 read-write 0 0x7 SEL Audio PLL clock source selection. 0 3 read-write FRO_12_MHZ FRO 12 MHz (fro_12m) 0 CLKIN CLKIN (clk_in) 0x1 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 SPIFICLKSEL SPIFI clock source select 0x2A0 32 read-write 0x7 0x7 SEL System PLL clock source selection 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 USB_PLL_OUTPUT USB PLL clock (usb_pll_clk) 0x2 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x3 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x4 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 ADCCLKSEL ADC clock source select 0x2A4 32 read-write 0x7 0x7 SEL ADC clock source selection 0 3 read-write FRO_HF FRO 96 or 48 MHz (fro_hf) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 USB_PLL_CLOCK USB PLL clock (usb_pll_clk) 0x2 AUDIO_PLL_CLOCK Audio PLL clock (audio_pll_clk) 0x3 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 USB0CLKSEL USB0 clock source select 0x2A8 32 read-write 0x7 0x7 SEL USB0 device clock source selection. 0 3 read-write FRO_HF FRO 96 or 48 MHz (fro_hf) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 USB_PLL_CLOCK USB PLL clock (usb_pll_clk) 0x2 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 USB1CLKSEL USB1 clock source select 0x2AC 32 read-write 0x7 0x7 SEL USB1 PHY clock source selection. 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 USB_PLL_CLOCK USB PLL clock (usb_pll_clk) 0x2 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 10 0x4 FCLKSEL[%s] Flexcomm 0 clock source select 0x2B0 32 read-write 0x7 0x7 SEL Flexcomm clock source selection. One per Flexcomm. 0 3 read-write FRO_12_MHZ FRO 12 MHz (fro_12m) 0 FRO_HF_DIV FRO HF DIV (fro_hf_div) 0x1 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x2 MCLK_INPUT MCLK pin input, when selected in IOCON (mclk_in) 0x3 FRG_CLOCK_OUTPUT FRG clock, the output of the fractional rate generator (frg_clk) 0x4 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 MCLKCLKSEL MCLK clock source select 0x2E0 32 read-write 0x7 0x7 SEL MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem. 0 3 read-write FRO_HF_DIV FRO HF DIV (fro_hf_div) 0 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x1 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 FRGCLKSEL Fractional Rate Generator clock source select 0x2E8 32 read-write 0x7 0x7 SEL Fractional Rate Generator clock source select. 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 FRO_12_MHZ FRO 12 MHz (fro_12m) 0x2 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x3 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 DMICCLKSEL Digital microphone (DMIC) subsystem clock select 0x2EC 32 read-write 0x7 0x7 SEL DMIC (audio subsystem) clock source select. 0 3 read-write FRO_12_MHZ FRO 12 MHz (fro_12m) 0 FRO_HF_DIV FRO HF DIV (fro_hf_div) 0x1 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x2 MCLK_INPUT MCLK pin input, when selected in IOCON (mclk_in) 0x3 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 SCTCLKSEL SCTimer/PWM clock source select 0x2F0 32 read-write 0x7 0x7 SEL SCT clock source select. 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x2 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x3 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 LCDCLKSEL LCD clock source select 0x2F4 32 read-write 0x3 0x3 SEL LCD clock source select. 0 2 read-write MAIN_CLOCK Main clock (main_clk) 0 LCDCLKIN LCDCLKIN (LCDCLK_EXT) 0x1 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x2 NONE None, this may be selected in order to reduce power when no output is needed. 0x3 SDIOCLKSEL SDIO clock source select 0x2F8 32 read-write 0x7 0x7 SEL SDIO clock source select. 0 3 read-write MAIN_CLOCK Main clock (main_clk) 0 SYSTEM_PLL_OUTPUT System PLL output (pll_clk) 0x1 USB_PLL_CLOCK USB PLL clock (usb_pll_clk) 0x2 FRO_HF FRO 96 or 48 MHz (fro_hf) 0x3 AUDIO_PLL_OUTPUT Audio PLL clock (audio_pll_clk) 0x4 NONE None, this may be selected in order to reduce power when no output is needed. 0x7 SYSTICKCLKDIV SYSTICK clock divider 0x300 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write ARMTRACECLKDIV ARM Trace clock divider 0x304 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write CAN0CLKDIV MCAN0 clock divider 0x308 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write CAN1CLKDIV MCAN1 clock divider 0x30C 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write SC0CLKDIV Smartcard0 clock divider 0x310 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write SC1CLKDIV Smartcard1 clock divider 0x314 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write AHBCLKDIV AHB clock divider 0x380 32 read-write 0 0x600000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write REQFLAG Divider status flag. 31 1 read-write CLKOUTDIV CLKOUT clock divider 0x384 32 read-write 0x40000000 0x600000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write FROHFCLKDIV FROHF clock divider 0x388 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write SPIFICLKDIV SPIFI clock divider 0x390 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write ADCCLKDIV ADC clock divider 0x394 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write USB0CLKDIV USB0 clock divider 0x398 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write USB1CLKDIV USB1 clock divider 0x39C 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write FRGCTRL Fractional rate divider 0x3A0 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0 8 read-write MULT Numerator of the fractional divider. MULT is equal to the programmed value. 8 8 read-write DMICCLKDIV DMIC clock divider 0x3A8 32 read-write 0x40000000 0x600000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write MCLKDIV I2S MCLK clock divider 0x3AC 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write LCDCLKDIV LCD clock divider 0x3B0 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write SCTCLKDIV SCT/PWM clock divider 0x3B4 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write EMCCLKDIV EMC clock divider 0x3B8 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write SDIOCLKDIV SDIO clock divider 0x3BC 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 read-write HALT Halts the divider counter. 30 1 read-write REQFLAG Divider status flag. 31 1 read-write FLASHCFG Flash wait states configuration 0x400 32 read-write 0xD1A 0xFFFFFFFF FETCHCFG Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches. 0 2 read-write NO_BUFFER Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled. 0 ONE_BUFFER One buffer is used for all instruction fetches. 0x1 ALL_BUFFERS All buffers may be used for instruction fetches. 0x2 DATACFG Data read configuration. This field determines how flash accelerator buffers are used for data accesses. 2 2 read-write NOT_BUFFERED Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory. 0 ONE_BUFFER One buffer is used for all data accesses. 0x1 ALL_BUFFERS All buffers may be used for data accesses. 0x2 ACCEL Acceleration enable. 4 1 read-write DISABLED Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance. 0 ENABLED Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings. 0x1 PREFEN Prefetch enable. 5 1 read-write NO_PREFETCH No instruction prefetch is performed. 0 PREFETCH If the FETCHCFG field is not 0, the next flash line following the current execution address is automatically prefetched if it is not already buffered. 0x1 PREFOVR Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched. 6 1 read-write PREFETCH_COMPLETED Any previously initiated prefetch will be completed. 0 PREFETCH_ABORT Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. 0x1 FLASHTIM Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. 12 4 read-write N_1_CLOCK_CYCLE 1 system clock flash access time (for system clock rates up to 12 MHz). 0 N_2_CLOCK_CYCLES 2 system clocks flash access time (for system clock rates up to 30 MHz). 0x1 N_3_CLOCK_CYCLES 3 system clocks flash access time (for system clock rates up to 60 MHz). 0x2 N_4_CLOCK_CYCLES 4 system clocks flash access time (for system clock rates up to 85 MHz). 0x3 N_5_CLOCK_CYCLES 5 system clocks flash access time (for system clock rates up to 100 MHz). 0x4 USB0CLKCTRL USB0 clock control 0x40C 32 read-write 0 0x1F AP_FS_DEV_CLK USB0 Device USB0_NEEDCLK signal control. 0 1 read-write POL_FS_DEV_CLK USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt. 1 1 read-write AP_FS_HOST_CLK USB0 Host USB0_NEEDCLK signal control. 2 1 read-write POL_FS_HOST_CLK USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt. 3 1 read-write PU_DISABLE Internal pull-up disable control. 4 1 read-write USB0CLKSTAT USB0 clock status 0x410 32 read-write 0 0x3 DEV_NEED_CLKST USB0 Device USB0_NEEDCLK signal status. 0 1 read-write HOST_NEED_CLKST USB0 Host USB0_NEEDCLK signal status. 1 1 read-write FREQMECTRL Frequency measure register 0x418 32 read-write 0 0x80003FFF CAPVAL Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only. 0 14 read-write PROG Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0). 31 1 read-write MCLKIO MCLK input/output control 0x420 32 read-write 0 0x1 DIR MCLK direction control. 0 1 read-write USB1CLKCTRL USB1 clock control 0x424 32 read-write 0x10 0x1F AP_FS_DEV_CLK USB1 Device need_clock signal control. 0 1 read-write POL_FS_DEV_CLK USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt. 1 1 read-write AP_FS_HOST_CLK USB1 Host need_clock signal control. 2 1 read-write POL_FS_HOST_CLK USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt. 3 1 read-write HS_DEV_WAKEUP_N External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic. 4 1 read-write USB1CLKSTAT USB1 clock status 0x428 32 read-write 0 0x3 DEV_NEED_CLKST USB1 Device USB1_NEEDCLK signal status. 0 1 read-write HOST_NEED_CLKST USB1 Device host USB1_NEEDCLK signal status. 1 1 read-write EMCSYSCTRL EMC system control 0x444 32 read-write 0x1 0xF EMCSC EMC Shift Control. 0 1 read-write EMCRD EMC Reset Disable. 1 1 read-write EMCBC External Memory Controller burst control. 2 1 read-write EMCFBCLKINSEL External Memory Controller clock select. 3 1 read-write EMCDLYCTRL EMC clock delay control 0x448 32 read-write 0x210 0x1F1F CMD_DELAY Programmable delay value for EMC outputs in command delayed mode. 0 5 read-write FBCLK_DELAY Programmable delay value for the feedback clock that controls input data sampling. 8 5 read-write EMCDLYCAL EMC delay chain calibration control 0x44C 32 read-write 0 0xC0FF CALVALUE Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz. 0 8 read-write START Start control bit for the EMC calibration counter. 14 1 read-write DONE Measurement completion flag. 15 1 read-write ETHPHYSEL Ethernet PHY Selection 0x450 32 read-write 0 0x4 PHY_SEL PHY interface select. 2 1 read-write ETHSBDCTRL Ethernet SBD flow control 0x454 32 read-write 0 0x3 SBD_CTRL Sideband Flow Control. 0 2 read-write SDIOCLKCTRL SDIO CCLKIN phase and delay control 0x460 32 read-write 0 0x9F9F008F CCLK_DRV_PHASE Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. 0 2 read-write CCLK_SAMPLE_PHASE Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. 2 2 read-write PHASE_ACTIVE sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv. 7 1 read-write CCLK_DRV_DELAY Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. 16 5 read-write CCLK_DRV_DELAY_ACTIVE Enables drive delay, as controlled by the CCLK_DRV_DELAY field. 23 1 read-write CCLK_SAMPLE_DELAY Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. 24 5 read-write CCLK_SAMPLE_DELAY_ACTIVE Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. 31 1 read-write FROCTRL FRO oscillator control 0x500 32 read-write 0x4000 0xC3FF7FFF TRIM This value is factory trimmed to account for bias and temperature compensation. 0 14 read-write SEL Select the FRO HF output frequency. 14 1 read-write FREQTRIM Frequency trim. 16 8 read-write USBCLKADJ USB clock adjust mode. 24 1 read-write USBMODCHG USB Mode value Change flag. 25 1 read-write HSPDCLK High speed clock enable. 30 1 read-write WRTRIM Write Trim value. 31 1 read-write SYSOSCCTRL System oscillator control 0x504 32 read-write 0 0x3 BYPASS Bypass system oscillator. 0 1 read-write FREQRANGE Determines frequency range for system oscillator. 1 1 read-write WDTOSCCTRL Watchdog oscillator control 0x508 32 read-write 0xA0 0x3FF DIVSEL Divider select. 0 5 read-write FREQSEL Frequency select. 5 5 read-write RTCOSCCTRL RTC oscillator 32 kHz output control 0x50C 32 read-write 0x1 0x1 EN RTC 32 kHz clock enable. 0 1 read-write USBPLLCTRL USB PLL control 0x51C 32 read-write 0 0 MSEL PLL feedback Divider value. 0 8 read-write PSEL PLL Divider value. 8 2 read-write NSEL PLL feedback Divider value. 10 2 read-write DIRECT Direct CCO clock output control. 12 1 read-write DISABLED CCO Clock signal goes through post divider. 0 ENABLED CCO Clock signal goes directly to output(s).. 0x1 BYPASS Input clock bypass control. 13 1 read-write DISABLED CCO clock is sent to post dividers.. 0 ENABLED PLL input clock is sent to post dividers.. 0x1 FBSEL Feedback divider input clock control. 14 1 read-write USBPLLSTAT USB PLL status 0x520 32 read-write 0 0 LOCK USBPLL lock indicator. 0 1 read-write SYSPLLCTRL System PLL control 0x580 32 read-write 0 0xFFFFFFFF SELR Bandwidth select R value. 0 4 read-write SELI Bandwidth select I value. 4 6 read-write SELP Bandwidth select P value. 10 5 read-write BYPASS PLL bypass control. 15 1 read-write DISABLED Bypass disabled. PLL CCO is sent to the PLL post-dividers. 0 ENABLED Bypass enabled. PLL input clock is sent directly to the PLL output (default). 0x1 UPLIMOFF Disable upper frequency limiter. 17 1 read-write DIRECTI PLL0 direct input enable. 19 1 read-write DIRECTO PLL0 direct output enable. 20 1 read-write DISABLED Disabled. The PLL output divider (P divider) is used to create the PLL output. 0 ENABLED Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. 0x1 SYSPLLSTAT PLL status 0x584 32 read-write 0 0 LOCK PLL lock indicator. 0 1 read-write SYSPLLNDEC PLL N divider 0x588 32 read-write 0 0 NDEC Decoded N-divider coefficient value. 0 10 read-write NREQ NDEC reload request. 10 1 read-write SYSPLLPDEC PLL P divider 0x58C 32 read-write 0 0 PDEC Decoded P-divider coefficient value. 0 7 read-write PREQ . 7 1 read-write SYSPLLMDEC System PLL M divider 0x590 32 read-write 0 0 MDEC Decoded M-divider coefficient value. 0 17 read-write MREQ MDEC reload request. 17 1 read-write AUDPLLCTRL Audio PLL control 0x5A0 32 read-write 0 0 SELR Bandwidth select R value. 0 4 read-write SELI Bandwidth select I value. 4 6 read-write SELP . 10 5 read-write BYPASS PLL bypass control. 15 1 read-write DISABLED Bypass disabled. PLL CCO is sent to the PLL post-dividers. 0 ENABLED Bypass enabled. PLL input clock is sent directly to the PLL output (default). 0x1 UPLIMOFF Disable upper frequency limiter. 17 1 read-write DIRECTI PLL direct input enable. 19 1 read-write DIRECTO PLL direct output enable 20 1 read-write DISABLED Disabled. The PLL output divider (P divider) is used to create the PLL output. 0 ENABLED Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. 0x1 AUDPLLSTAT Audio PLL status 0x5A4 32 read-write 0 0 LOCK PLL lock indicator. 0 1 read-write AUDPLLNDEC Audio PLL N divider 0x5A8 32 read-write 0 0 NDEC Decoded N-divider coefficient value. 0 10 read-write NREQ NDEC reload request. 10 1 read-write AUDPLLPDEC Audio PLL P divider 0x5AC 32 read-write 0 0 PDEC Decoded P-divider coefficient value. 0 7 read-write PREQ PDEC reload request. 7 1 read-write AUDPLLMDEC Audio PLL M divider 0x5B0 32 read-write 0 0 MDEC Decoded M-divider coefficient value. 0 17 read-write MREQ MDEC reload request. 17 1 read-write AUDPLLFRAC Audio PLL fractional divider control 0x5B4 32 read-write 0 0 CTRL PLL fractional divider control word 0 22 read-write REQ Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator. 22 1 read-write SEL_EXT Select fractional divider. 23 1 read-write PDSLEEPCFG0 Sleep configuration register 0x600 32 read-write 0xF81F40 0xFBFFD0 PDEN_FRO FRO oscillator. 4 1 read-write PDEN_TS Temp sensor. 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 8 1 read-write PDEN_VD2_ANA Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23). 9 1 read-write PDEN_ADC0 ADC power. 10 1 read-write PDEN_SRAMX PDEN_SRAMX controls SRAMX (also enable/disable bit 27). 13 1 read-write PDEN_SRAM0 PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27). 14 1 read-write PDEN_SRAM1_2_3 PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27). 15 1 read-write PDEN_USB_RAM PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27). 16 1 read-write PDEN_ROM ROM (also enable/disable bit 27). 17 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23). 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 20 1 read-write PDEN_USB0_PHY USB0 PHY power (also enable/disable bit 28). 21 1 read-write PDEN_SYS_PLL System PLL (PLL0) power (also enable/disable bit 26). 22 1 read-write PDEN_VREFP VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19). 23 1 read-write PDEN_VD3 Power control for all PLLs. 26 1 read-write PDEN_VD4 Power control for all SRAMs and ROM. 27 1 read-write PDEN_VD5 Power control both USB0 PHY and USB1 PHY. 28 1 read-write PDEN_VD6 Power control for EEPROM. 29 1 read-write PDSLEEPCFG1 Sleep configuration register 0x604 32 read-write 0xF81F40 0xFBFFD0 PDEN_USB1_PHY USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register). 0 1 read-write PDEN_USB1_PLL USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register). 1 1 read-write PDEN_AUD_PLL Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register). 2 1 read-write PDEN_SYSOSC System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register). 3 1 read-write PDEN_EEPROM EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register). 5 1 read-write PDEN_RNG Random Number Generator Power. 7 1 read-write PDRUNCFG0 Power configuration register 0x610 32 read-write 0x14F81F40 0x3CFBFFD0 PDEN_FRO FRO oscillator. 4 1 read-write PDEN_TS Temp sensor. 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 8 1 read-write PDEN_VD2_ANA Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23). 9 1 read-write PDEN_ADC0 ADC power. 10 1 read-write PDEN_SRAMX PDEN_SRAMX controls SRAMX (also enable/disable bit 27). 13 1 read-write PDEN_SRAM0 PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27). 14 1 read-write PDEN_SRAM1_2_3 PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27). 15 1 read-write PDEN_USB_RAM PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27). 16 1 read-write PDEN_ROM ROM (also enable/disable bit 27). 17 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23). 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 20 1 read-write PDEN_USB0_PHY USB0 PHY power (also enable/disable bit 28). 21 1 read-write PDEN_SYS_PLL System PLL (PLL0) power (also enable/disable bit 26). 22 1 read-write PDEN_VREFP VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19). 23 1 read-write PDEN_VD3 Power control for all PLLs. 26 1 read-write PDEN_VD4 Power control for all SRAMs and ROM. 27 1 read-write PDEN_VD5 Power control both USB0 PHY and USB1 PHY. 28 1 read-write PDEN_VD6 Power control for EEPROM. 29 1 read-write PDRUNCFG1 Power configuration register 0x614 32 read-write 0x14F81F40 0x3CFBFFD0 PDEN_USB1_PHY USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register). 0 1 read-write PDEN_USB1_PLL USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register). 1 1 read-write PDEN_AUD_PLL Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register). 2 1 read-write PDEN_SYSOSC System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register). 3 1 read-write PDEN_EEPROM EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register). 5 1 read-write PDEN_RNG Random Number Generator Power. 7 1 read-write PDRUNCFGSET0 Power configuration set register 0x620 32 read-write 0 0xFFFFFFFF PDEN_FRO FRO oscillator. 4 1 read-write PDEN_TS Temp sensor. 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 8 1 read-write PDEN_VD2_ANA Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23). 9 1 read-write PDEN_ADC0 ADC power. 10 1 read-write PDEN_SRAMX PDEN_SRAMX controls SRAMX (also enable/disable bit 27). 13 1 read-write PDEN_SRAM0 PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27). 14 1 read-write PDEN_SRAM1_2_3 PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27). 15 1 read-write PDEN_USB_RAM PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27). 16 1 read-write PDEN_ROM ROM (also enable/disable bit 27). 17 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23). 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 20 1 read-write PDEN_USB0_PHY USB0 PHY power (also enable/disable bit 28). 21 1 read-write PDEN_SYS_PLL System PLL (PLL0) power (also enable/disable bit 26). 22 1 read-write PDEN_VREFP VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19). 23 1 read-write PDEN_VD3 Power control for all PLLs. 26 1 read-write PDEN_VD4 Power control for all SRAMs and ROM. 27 1 read-write PDEN_VD5 Power control both USB0 PHY and USB1 PHY. 28 1 read-write PDEN_VD6 Power control for EEPROM. 29 1 read-write PDRUNCFGSET1 Power configuration set register 0x624 32 read-write 0 0xFFFFFFFF PDEN_USB1_PHY USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register). 0 1 read-write PDEN_USB1_PLL USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register). 1 1 read-write PDEN_AUD_PLL Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register). 2 1 read-write PDEN_SYSOSC System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register). 3 1 read-write PDEN_EEPROM EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register). 5 1 read-write PDEN_RNG Random Number Generator Power. 7 1 read-write PDRUNCFGCLR0 Power configuration clear register 0x630 32 read-write 0 0xFFFFFFFF PDEN_FRO FRO oscillator. 4 1 read-write PDEN_TS Temp sensor. 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 8 1 read-write PDEN_VD2_ANA Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23). 9 1 read-write PDEN_ADC0 ADC power. 10 1 read-write PDEN_SRAMX PDEN_SRAMX controls SRAMX (also enable/disable bit 27). 13 1 read-write PDEN_SRAM0 PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27). 14 1 read-write PDEN_SRAM1_2_3 PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27). 15 1 read-write PDEN_USB_RAM PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27). 16 1 read-write PDEN_ROM ROM (also enable/disable bit 27). 17 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23). 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 20 1 read-write PDEN_USB0_PHY USB0 PHY power (also enable/disable bit 28). 21 1 read-write PDEN_SYS_PLL System PLL (PLL0) power (also enable/disable bit 26). 22 1 read-write PDEN_VREFP VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19). 23 1 read-write PDEN_VD3 Power control for all PLLs. 26 1 read-write PDEN_VD4 Power control for all SRAMs and ROM. 27 1 read-write PDEN_VD5 Power control both USB0 PHY and USB1 PHY. 28 1 read-write PDEN_VD6 Power control for EEPROM. 29 1 read-write PDRUNCFGCLR1 Power configuration clear register 0x634 32 read-write 0 0xFFFFFFFF PDEN_USB1_PHY USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register). 0 1 read-write PDEN_USB1_PLL USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register). 1 1 read-write PDEN_AUD_PLL Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register). 2 1 read-write PDEN_SYSOSC System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register). 3 1 read-write PDEN_EEPROM EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register). 5 1 read-write PDEN_RNG Random Number Generator Power. 7 1 read-write STARTER0 Start logic 0 wake-up enable register 0x680 32 read-write 0 0x3FFFFFFF WDT_BOD WWDT and BOD interrupt wake-up. 0 1 read-write DMA DMA wake-up. 1 1 read-write GINT0 Group interrupt 0 wake-up. 2 1 read-write GINT1 Group interrupt 1 wake-up. 3 1 read-write PIN_INT0 GPIO pin interrupt 0 wake-up. 4 1 read-write PIN_INT1 GPIO pin interrupt 1 wake-up. 5 1 read-write PIN_INT2 GPIO pin interrupt 2 wake-up. 6 1 read-write PIN_INT3 GPIO pin interrupt 3 wake-up. 7 1 read-write UTICK Micro-tick Timer wake-up. 8 1 read-write MRT Multi-Rate Timer wake-up. 9 1 read-write CTIMER0 Standard counter/timer CTIMER0 wake-up. 10 1 read-write CTIMER1 Standard counter/timer CTIMER1 wake-up. 11 1 read-write SCT0 SCT0 wake-up. 12 1 read-write CTIMER3 Standard counter/timer CTIMER3 wake-up. 13 1 read-write FLEXCOMM0 Flexcomm0 peripheral interrupt wake-up. 14 1 read-write FLEXCOMM1 Flexcomm1 peripheral interrupt wake-up. 15 1 read-write FLEXCOMM2 Flexcomm2 peripheral interrupt wake-up. 16 1 read-write FLEXCOMM3 Flexcomm3 peripheral interrupt wake-up. 17 1 read-write FLEXCOMM4 Flexcomm4 peripheral interrupt wake-up. 18 1 read-write FLEXCOMM5 Flexcomm5 peripheral interrupt wake-up. 19 1 read-write FLEXCOMM6 Flexcomm6 peripheral interrupt wake-up. 20 1 read-write FLEXCOMM7 Flexcomm7 peripheral interrupt wake-up. 21 1 read-write ADC0_SEQA ADC0 sequence A interrupt wake-up. 22 1 read-write ADC0_SEQB ADC0 sequence B interrupt wake-up. 23 1 read-write ADC0_THCMP ADC0 threshold and error interrupt wake-up. 24 1 read-write DMIC Digital microphone interrupt wake-up. 25 1 read-write HWVAD Hardware voice activity detect interrupt wake-up. 26 1 read-write USB0_NEEDCLK USB activity interrupt wake-up. 27 1 read-write USB0 USB function interrupt wake-up. 28 1 read-write RTC RTC interrupt alarm and wake-up timer. 29 1 read-write STARTER1 Start logic 0 wake-up enable register 0x684 32 read-write 0 0x3FFFFFFF PINT4 GPIO pin interrupt 4 wake-up. 0 1 read-write PINT5 GPIO pin interrupt 5 wake-up. 1 1 read-write PINT6 GPIO pin interrupt 6 wake-up. 2 1 read-write PINT7 GPIO pin interrupt 7 wake-up. 3 1 read-write CTIMER2 Standard counter/timer CTIMER2 wake-up. 4 1 read-write CTIMER4 Standard counter/timer CTIMER4 wake-up. 5 1 read-write SPIFI SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 7 1 read-write FLEXCOMM8 Flexcomm Interface 8 wake-up. 8 1 read-write FLEXCOMM9 Flexcomm Interface 9 wake-up. 9 1 read-write USB1 USB 1 wake-up. 15 1 read-write USB1_ACT USB 1 activity wake-up. 16 1 read-write ENET_INT1 Ethernet. 17 1 read-write ENET_INT2 Ethernet. 18 1 read-write ENET_INT0 Ethernet. 19 1 read-write SMARTCARD0 Smart card 0 wake-up. 23 1 read-write SMARTCARD1 Smart card 1 wake-up. 24 1 read-write 2 0x4 STARTERSET[%s] Set bits in STARTER 0x6A0 32 write-only 0 0xFFFFFFFF START_SET Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented. 0 32 write-only 2 0x4 STARTERCLR[%s] Clear bits in STARTER0 0x6C0 32 write-only 0 0xFFFFFFFF START_CLR Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented. 0 32 write-only HWWAKE Configures special cases of hardware wake-up 0x780 32 read-write 0 0xF FORCEWAKE Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to continue operating while the main CPU(s) are shut down. 0 1 read-write FCWAKE Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted. 1 1 read-write WAKEDMIC Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted. 2 1 read-write WAKEDMA Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity. 3 1 read-write AUTOCGOR Auto Clock-Gate Override Register 0xE04 32 read-write 0 0xE RAM0X When 1, automatic clock gating for RAMX and RAM0 are turned off. 1 1 read-write RAM1 When 1, automatic clock gating for RAM1 are turned off. 2 1 read-write RAM2 When 1, automatic clock gating for RAM1 are turned off. 3 1 read-write RAM3 When 1, automatic clock gating for RAM1 are turned off. 4 1 read-write JTAGIDCODE JTAG ID code register 0xFF4 32 read-only 0 0xFFFFFFFF JTAGID JTAG ID code. 0 32 read-only DEVICE_ID0 Part ID register 0xFF8 32 read-only 0 0xFFFFFFFF PARTID Part ID 0 32 read-only DEVICE_ID1 Boot ROM and die revision register 0xFFC 32 read-only 0 0xFFFFFFFF REVID Revision. 0 32 read-only BODCTRL Brown-Out Detect control 0x20044 32 read-write 0 0xFF BODRSTLEV BOD reset level 0 2 read-write LEVEL0 Level 0: 1.5 V 0 LEVEL1 Level 1: 1.85 V 0x1 LEVEL2 Level 2: 2.0 V 0x2 LEVEL3 Level 3: 2.3 V 0x3 BODRSTENA BOD reset enable 2 1 read-write DISABLE Disable reset function. 0 ENABLE Enable reset function. 0x1 BODINTLEV BOD interrupt level 3 2 read-write LEVEL0 Level 0: 2.05 V 0 LEVEL1 Level 1: 2.45 V 0x1 LEVEL2 Level 2: 2.75 V 0x2 LEVEL3 Level 3: 3.05 V 0x3 BODINTENA BOD interrupt enable 5 1 read-write DISABLE Disable interrupt function. 0 ENABLE Enable interrupt function. 0x1 BODRSTSTAT BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit. 6 1 read-write BODINTSTAT BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. 7 1 read-write IOCON LPC5411x I/O pin configuration (IOCON) IOCON 0x40001000 0 0x300 registers PIO00 Digital I/O control for port 0 pins PIO0_0 0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO01 Digital I/O control for port 0 pins PIO0_1 0x4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO02 Digital I/O control for port 0 pins PIO0_2 0x8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO03 Digital I/O control for port 0 pins PIO0_3 0xC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO04 Digital I/O control for port 0 pins PIO0_4 0x10 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO05 Digital I/O control for port 0 pins PIO0_5 0x14 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO06 Digital I/O control for port 0 pins PIO0_6 0x18 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO07 Digital I/O control for port 0 pins PIO0_7 0x1C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO08 Digital I/O control for port 0 pins PIO0_8 0x20 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO09 Digital I/O control for port 0 pins PIO0_9 0x24 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO010 Digital I/O control for port 0 pins PIO0_10 0x28 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO011 Digital I/O control for port 0 pins PIO0_11 0x2C 32 read-write 0x326 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO012 Digital I/O control for port 0 pins PIO0_12 0x30 32 read-write 0x326 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO013 Digital I/O control for port 0 pins PIO0_13 0x34 32 read-write 0x340 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 I2CSLEW Controls slew rate of I2C pad. 6 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 I2CDRIVE Controls the current sink capability of the pin. 10 1 read-write LOW Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGH High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 11 1 read-write ENABLED Enabled. I2C 50 ns glitch filter enabled. 0 DISABLED Disabled. I2C 50 ns glitch filter disabled. 0x1 PIO014 Digital I/O control for port 0 pins PIO0_14 0x38 32 read-write 0x340 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 I2CSLEW Controls slew rate of I2C pad. 6 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 I2CDRIVE Controls the current sink capability of the pin. 10 1 read-write LOW Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGH High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 11 1 read-write ENABLED Enabled. I2C 50 ns glitch filter enabled. 0 DISABLED Disabled. I2C 50 ns glitch filter disabled. 0x1 PIO015 Digital I/O control for port 0 pins PIO0_15 0x3C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO016 Digital I/O control for port 0 pins PIO0_16 0x40 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO017 Digital I/O control for port 0 pins PIO0_17 0x44 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO018 Digital I/O control for port 0 pins PIO0_18 0x48 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO019 Digital I/O control for port 0 pins PIO0_19 0x4C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO020 Digital I/O control for port 0 pins PIO0_20 0x50 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO021 Digital I/O control for port 0 pins PIO0_21 0x54 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO022 Digital I/O control for port 0 pins PIO0_22 0x58 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO023 Digital I/O control for port 0 pins PIO0_23 0x5C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO024 Digital I/O control for port 0 pins PIO0_24 0x60 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO025 Digital I/O control for port 0 pins PIO0_25 0x64 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO026 Digital I/O control for port 0 pins PIO0_26 0x68 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO027 Digital I/O control for port 0 pins PIO0_27 0x6C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO028 Digital I/O control for port 0 pins PIO0_28 0x70 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO029 Digital I/O control for port 0 pins PIO0_29 0x74 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO030 Digital I/O control for port 0 pins PIO0_30 0x78 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO031 Digital I/O control for port 0 pins PIO0_31 0x7C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO10 Digital I/O control for port 1 pins PIO1_0 0x80 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO11 Digital I/O control for port 1 pins PIO1_1 0x84 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO12 Digital I/O control for port 1 pins PIO1_2 0x88 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO13 Digital I/O control for port 1 pins PIO1_3 0x8C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO14 Digital I/O control for port 1 pins PIO1_4 0x90 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO15 Digital I/O control for port 1 pins PIO1_5 0x94 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO16 Digital I/O control for port 1 pins PIO1_6 0x98 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO17 Digital I/O control for port 1 pins PIO1_7 0x9C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO18 Digital I/O control for port 1 pins PIO1_8 0xA0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO19 Digital I/O control for port 1 pins PIO1_9 0xA4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO110 Digital I/O control for port 1 pins PIO1_10 0xA8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO111 Digital I/O control for port 1 pins PIO1_11 0xAC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO112 Digital I/O control for port 1 pins PIO1_12 0xB0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO113 Digital I/O control for port 1 pins PIO1_13 0xB4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO114 Digital I/O control for port 1 pins PIO1_14 0xB8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO115 Digital I/O control for port 1 pins PIO1_15 0xBC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO116 Digital I/O control for port 1 pins PIO1_16 0xC0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO117 Digital I/O control for port 1 pins PIO1_17 0xC4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO118 Digital I/O control for port 1 pins PIO1_18 0xC8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO119 Digital I/O control for port 1 pins PIO1_19 0xCC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO120 Digital I/O control for port 1 pins PIO1_20 0xD0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO121 Digital I/O control for port 1 pins PIO1_21 0xD4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO122 Digital I/O control for port 1 pins PIO1_22 0xD8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO123 Digital I/O control for port 1 pins PIO1_23 0xDC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO124 Digital I/O control for port 1 pins PIO1_24 0xE0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO125 Digital I/O control for port 1 pins PIO1_25 0xE4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO126 Digital I/O control for port 1 pins PIO1_26 0xE8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO127 Digital I/O control for port 1 pins PIO1_27 0xEC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO128 Digital I/O control for port 1 pins PIO1_28 0xF0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO129 Digital I/O control for port 1 pins PIO1_29 0xF4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO130 Digital I/O control for port 1 pins PIO1_30 0xF8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO131 Digital I/O control for port 1 pins PIO1_31 0xFC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO20 Digital I/O control for port 2 pins PIO2_0 0x100 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO21 Digital I/O control for port 2 pins PIO2_1 0x104 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO22 Digital I/O control for port 2 pins PIO2_2 0x108 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO23 Digital I/O control for port 2 pins PIO2_3 0x10C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO24 Digital I/O control for port 2 pins PIO2_4 0x110 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO25 Digital I/O control for port 2 pins PIO2_5 0x114 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO26 Digital I/O control for port 2 pins PIO2_6 0x118 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO27 Digital I/O control for port 2 pins PIO2_7 0x11C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO28 Digital I/O control for port 2 pins PIO2_8 0x120 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO29 Digital I/O control for port 2 pins PIO2_9 0x124 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO210 Digital I/O control for port 2 pins PIO2_10 0x128 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO211 Digital I/O control for port 2 pins PIO2_11 0x12C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO212 Digital I/O control for port 2 pins PIO2_12 0x130 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO213 Digital I/O control for port 2 pins PIO2_13 0x134 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO214 Digital I/O control for port 2 pins PIO2_14 0x138 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO215 Digital I/O control for port 2 pins PIO2_15 0x13C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO216 Digital I/O control for port 2 pins PIO2_16 0x140 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO217 Digital I/O control for port 2 pins PIO2_17 0x144 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO218 Digital I/O control for port 2 pins PIO2_18 0x148 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO219 Digital I/O control for port 2 pins PIO2_19 0x14C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO220 Digital I/O control for port 2 pins PIO2_20 0x150 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO221 Digital I/O control for port 2 pins PIO2_21 0x154 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO222 Digital I/O control for port 2 pins PIO2_22 0x158 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO223 Digital I/O control for port 2 pins PIO2_23 0x15C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO224 Digital I/O control for port 2 pins PIO2_24 0x160 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO225 Digital I/O control for port 2 pins PIO2_25 0x164 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO226 Digital I/O control for port 2 pins PIO2_26 0x168 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO227 Digital I/O control for port 2 pins PIO2_27 0x16C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO228 Digital I/O control for port 2 pins PIO2_28 0x170 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO229 Digital I/O control for port 2 pins PIO2_29 0x174 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO230 Digital I/O control for port 2 pins PIO2_30 0x178 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO231 Digital I/O control for port 2 pins PIO2_31 0x17C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO30 Digital I/O control for port 3 pins PIO3_0 0x180 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO31 Digital I/O control for port 3 pins PIO3_1 0x184 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO32 Digital I/O control for port 3 pins PIO3_2 0x188 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO33 Digital I/O control for port 3 pins PIO3_3 0x18C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO34 Digital I/O control for port 3 pins PIO3_4 0x190 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO35 Digital I/O control for port 3 pins PIO3_5 0x194 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO36 Digital I/O control for port 3 pins PIO3_6 0x198 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO37 Digital I/O control for port 3 pins PIO3_7 0x19C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO38 Digital I/O control for port 3 pins PIO3_8 0x1A0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO39 Digital I/O control for port 3 pins PIO3_9 0x1A4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO310 Digital I/O control for port 3 pins PIO3_10 0x1A8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO311 Digital I/O control for port 3 pins PIO3_11 0x1AC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO312 Digital I/O control for port 3 pins PIO3_12 0x1B0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO313 Digital I/O control for port 3 pins PIO3_13 0x1B4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO314 Digital I/O control for port 3 pins PIO3_14 0x1B8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO315 Digital I/O control for port 3 pins PIO3_15 0x1BC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO316 Digital I/O control for port 3 pins PIO3_16 0x1C0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO317 Digital I/O control for port 3 pins PIO3_17 0x1C4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO318 Digital I/O control for port 3 pins PIO3_18 0x1C8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO319 Digital I/O control for port 3 pins PIO3_19 0x1CC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO320 Digital I/O control for port 3 pins PIO3_20 0x1D0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO321 Digital I/O control for port 3 pins PIO3_21 0x1D4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO322 Digital I/O control for port 3 pins PIO3_22 0x1D8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO323 Digital I/O control for port 3 pins PIO3_23 0x1DC 32 read-write 0x340 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 I2CSLEW Controls slew rate of I2C pad. 6 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 I2CDRIVE Controls the current sink capability of the pin. 10 1 read-write LOW Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGH High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 11 1 read-write ENABLED Enabled. I2C 50 ns glitch filter enabled. 0 DISABLED Disabled. I2C 50 ns glitch filter disabled. 0x1 PIO324 Digital I/O control for port 3 pins PIO3_24 0x1E0 32 read-write 0x340 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 I2CSLEW Controls slew rate of I2C pad. 6 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 I2CDRIVE Controls the current sink capability of the pin. 10 1 read-write LOW Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGH High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 11 1 read-write ENABLED Enabled. I2C 50 ns glitch filter enabled. 0 DISABLED Disabled. I2C 50 ns glitch filter disabled. 0x1 PIO325 Digital I/O control for port 3 pins PIO3_25 0x1E4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO326 Digital I/O control for port 3 pins PIO3_26 0x1E8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO327 Digital I/O control for port 3 pins PIO3_27 0x1EC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO328 Digital I/O control for port 3 pins PIO3_28 0x1F0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO329 Digital I/O control for port 3 pins PIO3_29 0x1F4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO330 Digital I/O control for port 3 pins PIO3_30 0x1F8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO331 Digital I/O control for port 3 pins PIO3_31 0x1FC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO40 Digital I/O control for port 4 pins PIO4_0 0x200 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO41 Digital I/O control for port 4 pins PIO4_1 0x204 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO42 Digital I/O control for port 4 pins PIO4_2 0x208 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO43 Digital I/O control for port 4 pins PIO4_3 0x20C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO44 Digital I/O control for port 4 pins PIO4_4 0x210 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO45 Digital I/O control for port 4 pins PIO4_5 0x214 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO46 Digital I/O control for port 4 pins PIO4_6 0x218 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO47 Digital I/O control for port 4 pins PIO4_7 0x21C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO48 Digital I/O control for port 4 pins PIO4_8 0x220 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO49 Digital I/O control for port 4 pins PIO4_9 0x224 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO410 Digital I/O control for port 4 pins PIO4_10 0x228 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO411 Digital I/O control for port 4 pins PIO4_11 0x22C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO412 Digital I/O control for port 4 pins PIO4_12 0x230 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO413 Digital I/O control for port 4 pins PIO4_13 0x234 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO414 Digital I/O control for port 4 pins PIO4_14 0x238 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO415 Digital I/O control for port 4 pins PIO4_15 0x23C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO416 Digital I/O control for port 4 pins PIO4_16 0x240 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO417 Digital I/O control for port 4 pins PIO4_17 0x244 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO418 Digital I/O control for port 4 pins PIO4_18 0x248 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO419 Digital I/O control for port 4 pins PIO4_19 0x24C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO420 Digital I/O control for port 4 pins PIO4_20 0x250 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO421 Digital I/O control for port 4 pins PIO4_21 0x254 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO422 Digital I/O control for port 4 pins PIO4_22 0x258 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO423 Digital I/O control for port 4 pins PIO4_23 0x25C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO424 Digital I/O control for port 4 pins PIO4_24 0x260 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO425 Digital I/O control for port 4 pins PIO4_25 0x264 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO426 Digital I/O control for port 4 pins PIO4_26 0x268 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO427 Digital I/O control for port 4 pins PIO4_27 0x26C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO428 Digital I/O control for port 4 pins PIO4_28 0x270 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO429 Digital I/O control for port 4 pins PIO4_29 0x274 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO430 Digital I/O control for port 4 pins PIO4_30 0x278 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO431 Digital I/O control for port 4 pins PIO4_31 0x27C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO50 Digital I/O control for port 5 pins PIO5_0 0x280 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO51 Digital I/O control for port 5 pins PIO5_1 0x284 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO52 Digital I/O control for port 5 pins PIO5_2 0x288 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO53 Digital I/O control for port 5 pins PIO5_3 0x28C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO54 Digital I/O control for port 5 pins PIO5_4 0x290 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO55 Digital I/O control for port 5 pins PIO5_5 0x294 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO56 Digital I/O control for port 5 pins PIO5_6 0x298 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO57 Digital I/O control for port 5 pins PIO5_7 0x29C 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO58 Digital I/O control for port 5 pins PIO5_8 0x2A0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO59 Digital I/O control for port 5 pins PIO5_9 0x2A4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO510 Digital I/O control for port 5 pins PIO5_10 0x2A8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO511 Digital I/O control for port 5 pins PIO5_11 0x2AC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO512 Digital I/O control for port 5 pins PIO5_12 0x2B0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO513 Digital I/O control for port 5 pins PIO5_13 0x2B4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO514 Digital I/O control for port 5 pins PIO5_14 0x2B8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO515 Digital I/O control for port 5 pins PIO5_15 0x2BC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO516 Digital I/O control for port 5 pins PIO5_16 0x2C0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO517 Digital I/O control for port 5 pins PIO5_17 0x2C4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO518 Digital I/O control for port 5 pins PIO5_18 0x2C8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO519 Digital I/O control for port 5 pins PIO5_19 0x2CC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO520 Digital I/O control for port 5 pins PIO5_20 0x2D0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO521 Digital I/O control for port 5 pins PIO5_21 0x2D4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO522 Digital I/O control for port 5 pins PIO5_22 0x2D8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO523 Digital I/O control for port 5 pins PIO5_23 0x2DC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO524 Digital I/O control for port 5 pins PIO5_24 0x2E0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO525 Digital I/O control for port 5 pins PIO5_25 0x2E4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO526 Digital I/O control for port 5 pins PIO5_26 0x2E8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO527 Digital I/O control for port 5 pins PIO5_27 0x2EC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO528 Digital I/O control for port 5 pins PIO5_28 0x2F0 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO529 Digital I/O control for port 5 pins PIO5_29 0x2F4 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO530 Digital I/O control for port 5 pins PIO5_30 0x2F8 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO531 Digital I/O control for port 5 pins PIO5_31 0x2FC 32 read-write 0x320 0xFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Analog/Digital mode. 8 1 read-write ANALOG Analog mode. 0 DIGITAL Digital mode. 0x1 FILTEROFF Controls input glitch filter. 9 1 read-write ENABLED Filter enabled. Noise pulses below approximately 10 ns are filtered out. 0 DISABLED Filter disabled. No input filtering is done. 0x1 SLEW Driver slew rate. 10 1 read-write STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 0x1 OD Controls open-drain mode. 11 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 GINT0 LPC5411x Group GPIO input interrupt (GINT0/1) GINT GINT 0x40002000 0 0x48 registers GINT0 2 CTRL GPIO grouped interrupt control register 0 32 read-write 0 0x7 INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. 0 1 read-write NO_REQUEST No request. No interrupt request is pending. 0 REQUEST_ACTIVE Request active. Interrupt request is active. 0x1 COMB Combine enabled inputs for group interrupt 1 1 read-write OR Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 0x1 TRIG Group interrupt trigger 2 1 read-write EDGE_TRIGGERED Edge-triggered. 0 LEVEL_TRIGGERED Level-triggered. 0x1 2 0x4 PORT_POL[%s] GPIO grouped interrupt port 0 polarity register 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF POL Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. 0 32 read-write 2 0x4 PORT_ENA[%s] GPIO grouped interrupt port 0 enable register 0x40 32 read-write 0 0xFFFFFFFF ENA Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. 0 32 read-write GINT1 LPC5411x Group GPIO input interrupt (GINT0/1) GINT 0x40003000 0 0x48 registers GINT1 3 PINT LPC5411x Pin interrupt and pattern match (PINT) PINT 0x40004000 0 0x34 registers PIN_INT0 4 PIN_INT1 5 PIN_INT2 6 PIN_INT3 7 PIN_INT4 32 PIN_INT5 33 PIN_INT6 34 PIN_INT7 35 ISEL Pin Interrupt Mode register 0 32 read-write 0 0xFF PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 0 8 read-write IENR Pin interrupt level or rising edge interrupt enable register 0x4 32 read-write 0 0xFF ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 8 read-write SIENR Pin interrupt level or rising edge interrupt set register 0x8 32 write-only 0 0 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 0 8 write-only CIENR Pin interrupt level (rising edge interrupt) clear register 0xC 32 write-only 0 0 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. 0 8 write-only IENF Pin interrupt active level or falling edge interrupt enable register 0x10 32 read-write 0 0xFF ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 8 read-write SIENF Pin interrupt active level or falling edge interrupt set register 0x14 32 write-only 0 0 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. 0 8 write-only CIENF Pin interrupt active level or falling edge interrupt clear register 0x18 32 write-only 0 0 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. 0 8 write-only RISE Pin interrupt rising edge register 0x1C 32 read-write 0 0xFF RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 0 8 read-write FALL Pin interrupt falling edge register 0x20 32 read-write 0 0xFF FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. 0 8 read-write IST Pin interrupt status register 0x24 32 read-write 0 0xFF PSTAT Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 0 8 read-write PMCTRL Pattern match interrupt control register 0x28 32 read-write 0 0xFF000003 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 0 1 read-write PIN_INTERRUPT Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 0 PATTERN_MATCH Pattern match. Interrupts are driven in response to pattern matches. 0x1 ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 1 1 read-write DISABLED Disabled. RXEV output to the CPU is disabled. 0 ENABLED Enabled. RXEV output to the CPU is enabled. 0x1 PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. 24 8 read-write PMSRC Pattern match interrupt bit-slice source register 0x2C 32 read-write 0 0xFFFFFF00 SRC0 Selects the input source for bit slice 0 8 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 11 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 14 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 17 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 20 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 23 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 26 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 29 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 0x7 PMCFG Pattern match interrupt bit slice configuration register 0x30 32 read-write 0 0xFFFFFF7F PROD_ENDPTS0 Determines whether slice 0 is an endpoint. 0 1 read-write NO_EFFECT No effect. Slice 0 is not an endpoint. 0 ENDPOINT endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS1 Determines whether slice 1 is an endpoint. 1 1 read-write NO_EFFECT No effect. Slice 1 is not an endpoint. 0 ENDPOINT endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS2 Determines whether slice 2 is an endpoint. 2 1 read-write NO_EFFECT No effect. Slice 2 is not an endpoint. 0 ENDPOINT endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS3 Determines whether slice 3 is an endpoint. 3 1 read-write NO_EFFECT No effect. Slice 3 is not an endpoint. 0 ENDPOINT endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS4 Determines whether slice 4 is an endpoint. 4 1 read-write NO_EFFECT No effect. Slice 4 is not an endpoint. 0 ENDPOINT endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS5 Determines whether slice 5 is an endpoint. 5 1 read-write NO_EFFECT No effect. Slice 5 is not an endpoint. 0 ENDPOINT endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS6 Determines whether slice 6 is an endpoint. 6 1 read-write NO_EFFECT No effect. Slice 6 is not an endpoint. 0 ENDPOINT endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 0x1 CFG0 Specifies the match contribution condition for bit slice 0. 8 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG1 Specifies the match contribution condition for bit slice 1. 11 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG2 Specifies the match contribution condition for bit slice 2. 14 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG3 Specifies the match contribution condition for bit slice 3. 17 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG4 Specifies the match contribution condition for bit slice 4. 20 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG5 Specifies the match contribution condition for bit slice 5. 23 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG6 Specifies the match contribution condition for bit slice 6. 26 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG7 Specifies the match contribution condition for bit slice 7. 29 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 INPUTMUX LPC5411x Input multiplexing (INPUT MUX) INPUTMUX 0x40005000 0 0x188 registers 7 0x4 SCT0_INMUX[%s] Trigger select register for DMA channel 0 32 read-write 0x1F 0x1F INP_N Input number to SCT0 inputs 0 to 6.. 0 5 read-write 8 0x4 PINTSEL[%s] Pin interrupt select register 0xC0 32 read-write 0 0xFF INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63). 0 8 read-write 30 0x4 DMA_ITRIG_INMUX[%s] Trigger select register for DMA channel 0xE0 32 read-write 0x1F 0x1F INP Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3 0 5 read-write 4 0x4 DMA_OTRIG_INMUX[%s] DMA output trigger selection to become DMA trigger 0x160 32 read-write 0x1F 0x1F INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19). 0 5 read-write FREQMEAS_REF Selection for frequency measurement reference clock 0x180 32 read-write 0x1F 0x1F CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 0 5 read-write FREQMEAS_TARGET Selection for frequency measurement target clock 0x184 32 read-write 0x1F 0x1F CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 0 5 read-write CTIMER0 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER CTIMER 0x40008000 0 0x88 registers CTIMER0 10 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0 32 read-write 0 0xFF MR0INT Interrupt flag for match channel 0. 0 1 read-write MR1INT Interrupt flag for match channel 1. 1 1 read-write MR2INT Interrupt flag for match channel 2. 2 1 read-write MR3INT Interrupt flag for match channel 3. 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. 6 1 read-write CR3INT Interrupt flag for capture channel 3 event. 7 1 read-write TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 32 read-write 0 0x3 CEN Counter enable. 0 1 read-write DISABLED Disabled.The counters are disabled. 0 ENABLED Enabled. The Timer Counter and Prescale Counter are enabled. 0x1 CRST Counter reset. 1 1 read-write DISABLED Disabled. Do nothing. 0 ENABLED Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 0x1 TC Timer Counter 0x8 32 read-write 0 0xFFFFFFFF TCVAL Timer counter value. 0 32 read-write PR Prescale Register 0xC 32 read-write 0 0xFFFFFFFF PRVAL Prescale counter value. 0 32 read-write PC Prescale Counter 0x10 32 read-write 0 0xFFFFFFFF PCVAL Prescale counter value. 0 32 read-write MCR Match Control Register 0x14 32 read-write 0 0xF000FFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 read-write MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 1 read-write MR0RL Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 24 1 read-write MR1RL Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 25 1 read-write MR2RL Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 26 1 read-write MR3RL Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 27 1 read-write 4 0x4 MR[%s] Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 32 read-write 0 0xFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 0 1 read-write CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 8 1 read-write CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 9 1 read-write CAP3FE Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 10 1 read-write CAP3I Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 11 1 read-write 4 0x4 CR[%s] Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x2C 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only EMR External Match Register. The EMR controls the match function and the external match pins. 0x3C 32 read-write 0 0xFFF EM0 External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 0 1 read-write EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 32 read-write 0 0xFF CTMODE Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 2 read-write TIMER Timer Mode. Incremented every rising APB bus clock edge. 0 COUNTER_RISING_EDGE Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 COUNTER_FALLING_EDGE Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 COUNTER_DUAL_EDGE Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 2 2 read-write CHANNEL_0 Channel 0. CAPn.0 for CTIMERn 0 CHANNEL_1 Channel 1. CAPn.1 for CTIMERn 0x1 CHANNEL_2 Channel 2. CAPn.2 for CTIMERn 0x2 CHANNEL_3 Channel 3. CAPn.3 for CTIMERn 0x3 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 5 3 read-write CHANNEL_0_RISING Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0 CHANNEL_0_FALLING Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0x1 CHANNEL_1_RISING Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x2 CHANNEL_1_FALLING Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x3 CHANNEL_2_RISING Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x4 CHANNEL_2_FALLING Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x5 PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins. 0x74 32 read-write 0 0xF PWMEN0 PWM mode enable for channel0. 0 1 read-write MATCH Match. CTIMERn_MAT0 is controlled by EM0. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT0. 0x1 PWMEN1 PWM mode enable for channel1. 1 1 read-write MATCH Match. CTIMERn_MAT01 is controlled by EM1. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT1. 0x1 PWMEN2 PWM mode enable for channel2. 2 1 read-write MATCH Match. CTIMERn_MAT2 is controlled by EM2. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT2. 0x1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 3 1 read-write MATCH Match. CTIMERn_MAT3 is controlled by EM3. 0 PWM PWM. PWM mode is enabled for CT132Bn_MAT3. 0x1 4 0x4 MSR[%s] Match Shadow Register 0x78 32 read-write 0 0xFFFFFFFF SHADOWW Timer counter match shadow value. 0 32 read-write CTIMER1 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER 0x40009000 0 0x88 registers CTIMER1 11 CTIMER2 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER 0x40028000 0 0x88 registers CTIMER2 36 CTIMER3 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER 0x40048000 0 0x88 registers CTIMER3 13 CTIMER4 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER 0x40049000 0 0x88 registers CTIMER4 37 WWDT LPC5411x Windowed Watchdog Timer (WWDT) WWDT 0x4000C000 0 0x1C registers WDT_BOD 0 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0 32 read-write 0 0x3F WDEN Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. 0 1 read-write STOP Stop. The watchdog timer is stopped. 0 RUN Run. The watchdog timer is running. 0x1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 1 1 read-write INTERRUPT Interrupt. A watchdog time-out will not cause a chip reset. 0 RESET Reset. A watchdog time-out will cause a chip reset. 0x1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. 2 1 read-write WDINT Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 3 1 read-write WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 4 1 read-write FLEXIBLE Flexible. The watchdog time-out value (TC) can be changed at any time. 0 THRESHOLD Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 0x1 LOCK Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset. 5 1 read-write TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x4 32 read-write 0xFF 0xFFFFFF COUNT Watchdog time-out value. 0 24 read-write FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. 0x8 32 write-only 0 0 FEED Feed value should be 0xAA followed by 0x55. 0 8 write-only TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0xC 32 read-only 0xFF 0xFFFFFF COUNT Counter timer value. 0 24 read-only WARNINT Watchdog Warning Interrupt compare value. 0x14 32 read-write 0 0x3FF WARNINT Watchdog warning interrupt compare value. 0 10 read-write WINDOW Watchdog Window compare value. 0x18 32 read-write 0xFFFFFF 0xFFFFFF WINDOW Watchdog window value. 0 24 read-write MRT0 LPC5411x Multi-Rate Timer (MRT) MRT 0x4000D000 0 0xFC registers MRT0 9 4 0x10 CHANNEL[%s] no description available 0 INTVAL MRT Time interval value register. This value is loaded into the TIMER register. 0 32 read-write 0 0x80FFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 24 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write NO_FORCE_LOAD No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. 0 FORCE_LOAD Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 0x1 TIMER MRT Timer register. This register reads the value of the down-counter. 0x4 32 read-only 0xFFFFFF 0xFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 24 read-only CTRL MRT Control register. This register controls the MRT modes. 0x8 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write DISABLED Disabled. TIMERn interrupt is disabled. 0 ENABLED Enabled. TIMERn interrupt is enabled. 0x1 MODE Selects timer mode. 1 2 read-write REPEAT_INTERRUPT_MODE Repeat interrupt mode. 0 ONE_SHOT_INTERRUPT_MODE One-shot interrupt mode. 0x1 ONE_SHOT_STALL_MODE One-shot stall mode. 0x2 STAT MRT Status register. 0xC 32 read-write 0 0x7 INTFLAG Monitors the interrupt flag. 0 1 read-write NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 0x1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write IDLE_STATE Idle state. TIMERn is stopped. 0 RUNNING Running. TIMERn is running. 0x1 INUSE Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. 2 1 read-write NO This channel is not in use. 0 YES This channel is in use. 0x1 MODCFG Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. 0xF0 32 read-write 0x173 0x800001FF NOC Identifies the number of channels in this MRT.(4 channels on this device.) 0 4 read-write NOB Identifies the number of timer bits in this MRT. (24 bits wide on this device.) 4 5 read-write MULTITASK Selects the operating mode for the INUSE flags and the IDLE_CH register. 31 1 read-write HARDWARE_STATUS_MODE Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. 0 MULTI_TASK_MODE Multi-task mode. 0x1 IDLE_CH Idle channel register. This register returns the number of the first idle channel. 0xF4 32 read-only 0 0xF0 CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. 4 4 read-only IRQ_FLAG Global interrupt flag register 0xF8 32 read-write 0 0xF GFLAG0 Monitors the interrupt flag of TIMER0. 0 1 read-write NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 0x1 GFLAG1 Monitors the interrupt flag of TIMER1. See description of channel 0. 1 1 read-write GFLAG2 Monitors the interrupt flag of TIMER2. See description of channel 0. 2 1 read-write GFLAG3 Monitors the interrupt flag of TIMER3. See description of channel 0. 3 1 read-write UTICK0 LPC5411x Micro-tick Timer (UTICK) UTICK 0x4000E000 0 0x20 registers UTICK0 8 CTRL Control register. 0 32 read-write 0 0xFFFFFFFF DELAYVAL Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. 0 31 read-write REPEAT Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. 31 1 read-write STAT Status register. 0x4 32 read-write 0 0x3 INTR Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. 0 1 read-write ACTIVE Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. 1 1 read-write CFG Capture configuration register. 0x8 32 read-write 0 0xF0F CAPEN0 Enable Capture 0. 1 = Enabled, 0 = Disabled. 0 1 read-write CAPEN1 Enable Capture 1. 1 = Enabled, 0 = Disabled. 1 1 read-write CAPEN2 Enable Capture 2. 1 = Enabled, 0 = Disabled. 2 1 read-write CAPEN3 Enable Capture 3. 1 = Enabled, 0 = Disabled. 3 1 read-write CAPPOL0 Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. 8 1 read-write CAPPOL1 Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. 9 1 read-write CAPPOL2 Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. 10 1 read-write CAPPOL3 Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. 11 1 read-write CAPCLR Capture clear register. 0xC 32 write-only 0 0 CAPCLR0 Clear capture 0. Writing 1 to this bit clears the CAP0 register value. 0 1 write-only CAPCLR1 Clear capture 1. Writing 1 to this bit clears the CAP1 register value. 1 1 write-only CAPCLR2 Clear capture 2. Writing 1 to this bit clears the CAP2 register value. 2 1 write-only CAPCLR3 Clear capture 3. Writing 1 to this bit clears the CAP3 register value. 3 1 write-only 4 0x4 CAP[%s] Capture register . 0x10 32 read-only 0 0xFFFFFFFF CAP_VALUE Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. 0 31 read-only VALID Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. 31 1 read-only EEPROM LPC5460x EEPROM controller EEPROM 0x40014000 0 0xFF0 registers EEPROM 52 CMD EEPROM command register 0 32 read-write 0 0x7 CMD Command. 0 3 read-write RWSTATE EEPROM read wait state register 0x8 32 read-write 0xE07 0xFFFF RPHASE2 Wait states 2 (minus 1 encoded). 0 8 read-write RPHASE1 Wait states 1 (minus 1 encoded). 8 8 read-write AUTOPROG EEPROM auto programming register 0xC 32 read-write 0 0x3 AUTOPROG Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with . 0 2 read-write WSTATE EEPROM wait state register 0x10 32 read-write 0x40802 0x80FFFFFF PHASE3 Wait states for phase 3 (minus 1 encoded). 0 8 read-write PHASE2 Wait states for phase 2 (minus 1 encoded). 8 8 read-write PHASE1 Wait states for phase 1 (minus 1 encoded). 16 8 read-write LCK_PARWEP Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access. 31 1 read-write CLKDIV EEPROM clock divider register 0x14 32 read-write 0x63 0xFFFF CLKDIV Division factor (minus 1 encoded). 0 16 read-write PWRDWN EEPROM power-down register 0x18 32 read-write 0 0x1 PWRDWN Power down mode bit. 0 1 read-write INTENCLR EEPROM interrupt enable clear 0xFD8 32 write-only 0 0x4 PROG_CLR_EN Clear program operation finished interrupt enable bit for EEPROM. 2 1 write-only INTENSET EEPROM interrupt enable set 0xFDC 32 write-only 0 0x4 PROG_SET_EN Set program operation finished interrupt enable bit for EEPROM device 1. 2 1 write-only INTSTAT EEPROM interrupt status 0xFE0 32 read-only 0 0x4 END_OF_PROG EEPROM program operation finished interrupt status bit. 2 1 read-only INTEN EEPROM interrupt enable 0xFE4 32 read-only 0 0x4 EE_PROG_DONE EEPROM program operation finished interrupt enable bit. 2 1 read-only INTSTATCLR EEPROM interrupt status clear 0xFE8 32 write-only 0 0x4 PROG_CLR_ST Clear program operation finished interrupt status bit for EEPROM device. 2 1 write-only INTSTATSET EEPROM interrupt status set 0xFEC 32 write-only 0 0x4 PROG_SET_ST Set program operation finished interrupt status bit for EEPROM device. 2 1 write-only OTPC This is the description of component otpc It is an eFUSE OTP (One Time Programmable memory) controller with APB bus interface. More details will follow. OTPC 0x40015000 0 0x40 registers 8 0x4 AESKEY[%s] Register for reading the AES key. 0x10 32 read-only 0 0 KEY AES key. 0 32 read-only ECRP ECRP options. 0x30 32 read-only 0 0 CRP_MASS_ERASE_DISABLE Disable or enable CRP mass erase. 4 1 read-only IAP_PROTECTION_ENABLE This bit controls the ability to enable checking for ECRP in IAP functions. 5 1 read-only CRP_ISP_DISABLE_PIN This bit controls the ability to enter ISP mode using the ISP pin. 6 1 read-only CRP_ISP_DISABLE_IAP This bit controls the ability to re-invoke ISP using IAP routines. 7 1 read-only CRP_ALLOW_ZERO This bit controls how 0 is treated when read as a ECRP value.. 9 1 read-only JTAG_DISABLE 0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG.. 31 1 read-only USER0 User application specific options. 0x38 32 read-only 0 0 USER0 User application specific option. 0 32 read-only USER1 User application specific options. 0x3C 32 read-only 0 0 USER1 User application specific option. 0 32 read-only RTC LPC5411x Real-Time Clock (RTC) RTC 0x4002C000 0 0x60 registers RTC 29 CTRL RTC control register 0 32 read-write 0x1 0x3FD SWRESET Software reset control 0 1 read-write NOT_IN_RESET Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 0 IN_RESET In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. 0x1 ALARM1HZ RTC 1 Hz timer alarm flag status. 2 1 read-write NO_MATCH No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 0 MATCH Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 0x1 WAKE1KHZ RTC 1 kHz timer wake-up flag status. 3 1 read-write RUN Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 0 TIMEOUT Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 0x1 ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. 4 1 read-write DISABLE Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 0x1 WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. 5 1 read-write DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 0x1 RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). 6 1 read-write DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. The 1 kHz RTC timer is enabled. 0x1 RTC_EN RTC enable. 7 1 read-write DISABLE Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. 0 ENABLE Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. 0x1 RTC_OSC_PD RTC oscillator power-down control. 8 1 read-write POWER_UP See RTC_OSC_BYPASS 0 POWERED_DOWN RTC oscillator is powered-down. 0x1 MATCH RTC match register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF MATVAL Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. 0 32 read-write COUNT RTC counter register 0x8 32 read-write 0 0xFFFFFFFF VAL A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. 0 32 read-write WAKE High-resolution/wake-up timer control register 0xC 32 read-write 0 0xFFFF VAL A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. 0 16 read-write 8 0x4 GPREG[%s] General Purpose register 0x40 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. 0 32 read-write RIT LPC5460x Repetitive Interrupt Timer(RIT) RIT 0x4002D000 0 0x20 registers RIT 38 COMPVAL Compare value LSB register 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF RICOMP . 0 32 read-write MASK Mask LSB register 0x4 32 read-write 0 0xFFFFFFFF RIMASK Mask register. 0 32 read-write CTRL Control register 0x8 32 read-write 0xC 0xF RITINT Interrupt flag. 0 1 read-write RITENCLR Timer enable clear. 1 1 read-write RITENBR Timer enable for debug. 2 1 read-write RITEN Timer enable. 3 1 read-write COUNTER Counter LSB register 0xC 32 read-write 0 0xFFFFFFFF RICOUNTER 32 LSBs of the up counter. 0 32 read-write COMPVAL_H Compare value MSB register 0x10 32 read-write 0xFFFF 0xFFFF RICOMP Compare value MSB register. 0 16 read-write MASK_H Mask MSB register 0x14 32 read-write 0 0xFFFF RIMASK Mask register. 0 16 read-write COUNTER_H Counter MSB register 0x1C 32 read-write 0 0xFFFF RICOUNTER 16 LSBs of the up counter. 0 16 read-write FMC LPC5460x Flash signature generator FMC 0x40034000 0 0xFEC registers FCTR Control register 0 32 read-write 0x200005 0xFFFFFF FS_RD0 Value must be 0 for signature generation. 3 1 read-write FS_RD1 Value must be 1 for signature generation. 4 1 read-write FBWST Wait state register 0x10 32 read-write 0xC005 0xFFFFFF WAITSTATES Wait states for signature generation. 0 8 read-write FMSSTART Signature start address register 0x20 32 read-write 0 0x1FFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). 0 17 read-write FMSSTOP Signature stop-address register 0x24 32 read-write 0 0x3FFFF STOP Stop address for signature generation (the word specified by STOP is included in the address range). 0 17 read-write SIG_START When this bit is written to 1, signature generation starts. 17 1 read-write 4 0x4 FMSW[%s] Words of 128-bit signature word 0x2C 32 read-only 0 0xFFFFFFFF SW Words of 128-bit signature (bits). 0 32 read-only FMSTAT Signature generation status register 0xFE0 32 read-only 0 0x4 SIG_DONE When 1, a previously started signature generation has completed. 2 1 read-only FMSTATCLR Signature generation status clear register 0xFE8 32 write-only 0 0x4 SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. 2 1 write-only SMARTCARD0 LPC5460x Smart Card Interface SMARTCARD SMARTCARD 0x40036000 0 0x4C registers SMARTCARD0 55 DLL Divisor Latch LSB RBR_THR_DLL 0 32 read-write 0x1 0xFF DLLSB The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn. 0 8 read-write RBR Receiver Buffer Register RBR_THR_DLL 0 32 read-only 0 0xFF RBR The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO. 0 8 read-only THR Transmit Holding Register RBR_THR_DLL 0 32 write-only 0 0xFF THR Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO. 0 8 write-only DLM Divisor Latch MSB DLM_IER 0x4 32 read-write 0 0xFF DLMSB The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn. 0 8 read-write IER Interrupt Enable Register DLM_IER 0x4 32 read-write 0 0x7 RBRIE RBR Interrupt Enable. 0 1 read-write THREIE THRE Interrupt Enable. 1 1 read-write RXIE RX Line Status Interrupt Enable. 2 1 read-write FCR FIFO Control Register IIR_FCR 0x8 32 write-only 0 0xCF FIFOEN FIFO Enable. 0 1 write-only RXFIFORES RX FIFO Reset. 1 1 write-only TXFIFORES TX FIFO Reset. 2 1 write-only DMAMODE DMA Mode Select. 3 1 write-only RXTRIGLVL RX Trigger Level. 6 2 write-only IIR Interrupt ID Register IIR_FCR 0x8 32 read-only 0x1 0xCF INTSTATUS Interrupt status. 0 1 read-only INTID Interrupt identification. 1 3 read-only FIFOENABLE Copies of SCInFCR[0]. 6 2 read-only LCR Line Control Register 0xC 32 read-write 0 0xBF WLS Word Length Select. 0 2 read-write SBS Stop Bit Select. 2 1 read-write PE Parity Enable. 3 1 read-write PS Parity Select. 4 2 read-write DLAB Divisor Latch Access Bit. 7 1 read-write LSR Line Status Register 0x14 32 read-only 0x60 0xEF RDR Receiver Data Ready. 0 1 read-only OE Overrun Error. 1 1 read-only PE Parity Error. 2 1 read-only FE Framing Error. 3 1 read-only THRE Transmitter Holding Register Empty. 5 1 read-only TEMT Transmitter Empty. 6 1 read-only RXFE Error in RX FIFO. 7 1 read-only SCR Scratch Pad Register 0x1C 32 read-write 0 0xFF PAD A readable, writable byte. 0 8 read-write OSR Oversampling register 0x2C 32 read-write 0xF0 0x7FFE OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. 1 3 read-write OSINT Integer part of the oversampling ratio, minus 1. 4 4 read-write FDINT These bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. 8 7 read-write SCICTRL Smart Card Interface control register 0x48 32 read-write 0 0xFFE7 SCIEN Smart Card Interface Enable. 0 1 read-write NACKDIS NACK response disable. 1 1 read-write PROTSEL Protocol selection as defined in the ISO7816-3 standard. 2 1 read-write TXRETRY Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). 5 3 read-write GUARDTIME Extra guard time. 8 8 read-write SMARTCARD1 LPC5460x Smart Card Interface SMARTCARD 0x40037000 0 0x4C registers SMARTCARD1 56 ASYNC_SYSCON LPC5411x Asynchronous system configuration (ASYNC_SYSCON) ASYNC_SYSCON 0x40040000 0 0x24 registers ASYNCPRESETCTRL Async peripheral reset control 0 32 read-write 0 0x6000 CTIMER3 Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 13 1 read-write CTIMER4 Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 14 1 read-write ASYNCPRESETCTRLSET Set bits in ASYNCPRESETCTRL 0x4 32 write-only 0 0 ARST_SET Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 0 32 write-only ASYNCPRESETCTRLCLR Clear bits in ASYNCPRESETCTRL 0x8 32 write-only 0 0 ARST_CLR Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 0 32 write-only ASYNCAPBCLKCTRL Async peripheral clock control 0x10 32 read-write 0 0x6000 CTIMER3 Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. 13 1 read-write CTIMER4 Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. 14 1 read-write ASYNCAPBCLKCTRLSET Set bits in ASYNCAPBCLKCTRL 0x14 32 write-only 0 0 ACLK_SET Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 0 32 write-only ASYNCAPBCLKCTRLCLR Clear bits in ASYNCAPBCLKCTRL 0x18 32 write-only 0 0 ACLK_CLR Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them. 0 32 write-only ASYNCAPBCLKSELA Async APB clock source select A 0x20 32 read-write 0 0x3 SEL Clock source for asynchronous clock source selector A 0 2 read-write MAIN_CLOCK Main clock (main_clk) 0 FRO_12_MHZ FRO 12 MHz (fro_12m) 0x1 AUDIO_PLL_CLOCK Audio PLL clock.(AUDPLL_BYPASS) 0x2 FC6_FCLK fc6 fclk (fc6_fclk) 0x3 SPIFI0 LPC5411x SPI Flash Interface (SPIFI) SPIFI 0x40080000 0 0x20 registers SPIFI0 39 CTRL SPIFI control register 0 32 read-write 0x400FFFFF 0xF8EFFFFF TIMEOUT This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again. 0 16 read-write CSHIGH This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. 16 4 read-write D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. 21 1 read-write INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. 22 1 read-write MODE3 SPI Mode 3 select. 23 1 read-write SCK_LOW SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH. 0 SCK_HIGH SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 27 1 read-write ENABLE Enable. Cache prefetching enabled. 0 DISABLE Disable. Disables prefetching of cache lines. 0x1 DUAL Select dual protocol. 28 1 read-write QUAD Quad protocol. This protocol uses IO3:0. 0 DUAL Dual protocol. This protocol uses IO1:0. 0x1 RFCLK Select active clock edge for input data. 29 1 read-write RISING_EDGE Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 0 FALLING_EDGE Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 FBCLK Feedback clock select. 30 1 read-write INTERNAL_CLOCK Internal clock. The SPIFI samples read data using an internal clock. 0 FEEDBACK_CLOCK Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 DMAEN A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode. 31 1 read-write CMD SPIFI command register 0x4 32 read-write 0 0xFFFFFFFF DATALEN Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field. 0 14 read-write POLL This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs 14 1 read-write DOUT If the DATALEN field is not zero, this bit controls the direction of the data: 15 1 read-write INPUT Input from serial flash. 0 OUTPUT Output to serial flash. 0x1 INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. 19 2 read-write ALL_SERIAL All serial. All fields of the command are serial. 0 QUAD_DUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUAD_DUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. 21 3 read-write OPCODE Opcode. Opcode only, no address. 0x1 OPCODE_1_BYTE Opcode one byte. Opcode, least significant byte of address. 0x2 OPCODE_2_BYTES Opcode two bytes. Opcode, two least significant bytes of address. 0x3 OPCODE_3_BYTES Opcode three bytes. Opcode, three least significant bytes of address. 0x4 OPCODE_4_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_3_BYTES No opcode three bytes. No opcode, 3 least significant bytes of address. 0x6 NO_OPCODE_4_BYTES No opcode four bytes. No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). 24 8 read-write ADDR SPIFI address register 0x8 32 read-write 0 0xFFFFFFFF ADDRESS Address. 0 32 read-write IDATA SPIFI intermediate data register 0xC 32 read-write 0 0xFFFFFFFF IDATA Value of intermediate bytes. 0 32 read-write CLIMIT SPIFI limit register 0x10 32 read-write 0x8000000 0xFFFFFFFF CLIMIT Zero-based upper limit of cacheable memory 0 32 read-write DATA SPIFI data register 0x14 32 read-write 0 0xFFFFFFFF DATA Input or output data 0 32 read-write MCMD SPIFI memory command register 0x18 32 read-write 0 0xFFFFC000 POLL This bit should be written as 0. 14 1 read-write DOUT This bit should be written as 0. 15 1 read-write INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. 19 2 read-write ALL_SERIAL All serial. All fields of the command are serial. 0 QUAD_DUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUAD_DUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. 21 3 read-write OPCODE Opcode. Opcode only, no address. 0x1 OPCODE_1_BYTE Opcode one byte. Opcode, least-significant byte of address. 0x2 OPCODE_2_BYTES Opcode two bytes. Opcode, 2 least-significant bytes of address. 0x3 OPCODE_3_BYTES Opcode three bytes. Opcode, 3 least-significant bytes of address. 0x4 OPCODE_4_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_3_BYTES No opcode three bytes. No opcode, 3 least-significant bytes of address. 0x6 NO_OPCODE_4_BYTES No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). 24 8 read-write STAT SPIFI status register 0x1C 32 read-write 0x2000000 0xFF000033 MCINIT This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register. 0 1 read-write CMD This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash. 1 1 read-write RESET Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register. 4 1 read-write INTRQ This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. 5 1 read-write EMC LPC5460x External Memory Controller (EMC) EMC 0x40081000 0 0x27C registers 4 0x20 DYNAMIC[%s] no description available 0x100 DYNAMICCONFIG Configuration information for EMC_DYCSx 0 32 read-write 0 0x185F98 MD Memory device. 3 2 read-write AM0 See Table 933. 7 6 read-write AM1 See Table 933. 14 1 read-write B Buffer enable. 19 1 read-write P Write protect. 20 1 read-write DYNAMICRASCAS RAS and CAS latencies for EMC_DYCSx 0x4 32 read-write 0x303 0x303 RAS RAS latency (active to read/write delay). 0 2 read-write CAS CAS latency. 8 2 read-write 4 0x20 STATIC[%s] no description available 0x200 STATICCONFIG Configuration for EMC_CSx 0 32 read-write 0 0x1801CB MW Memory width. 0 2 read-write PM Page mode. 3 1 read-write PC Chip select polarity. 6 1 read-write PB Byte lane state. 7 1 read-write EW Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. 8 1 read-write B Buffer enable [2]. 19 1 read-write P Write protect. 20 1 read-write STATICWAITWEN Delay from EMC_CSx to write enable 0x4 32 read-write 0 0xF WAITWEN Wait write enable. 0 4 read-write STATICWAITOEN Delay from EMC_CSx or address change, whichever is later, to output enable 0x8 32 read-write 0 0xF WAITOEN Wait output enable. 0 4 read-write STATICWAITRD Delay from EMC_CSx to a read access 0xC 32 read-write 0x1F 0x1F WAITRD . 0 5 read-write STATICWAITPAGE Delay for asynchronous page mode sequential accesses for EMC_CSx 0x10 32 read-write 0x1F 0x1F WAITPAGE Asynchronous page mode read after the first read wait states. 0 5 read-write STATICWAITWR Delay from EMC_CSx to a write access 0x14 32 read-write 0x1F 0x1F WAITWR Write wait states. 0 5 read-write STATICWAITTURN Number of bus turnaround cycles EMC_CSx 0x18 32 read-write 0xF 0xF WAITTURN Bus turn-around cycles. 0 4 read-write CONTROL Controls operation of the memory controller 0 32 read-write 0x3 0x7 E EMC Enable. 0 1 read-write M Address mirror. 1 1 read-write L Low-power mode. 2 1 read-write STATUS Provides EMC status information 0x4 32 read-only 0x5 0x7 B Busy. 0 1 read-only S Write buffer status. 1 1 read-only SA Self-refresh acknowledge. 2 1 read-only CONFIG Configures operation of the memory controller 0x8 32 read-write 0 0x101 EM Endian mode. 0 1 read-write CLKR This bit must contain 0 for proper operation of the EMC. 8 1 read-write DYNAMICCONTROL Controls dynamic memory operation 0x20 32 read-write 0x6 0x1A7 CE Dynamic memory clock enable. 0 1 read-write CS Dynamic memory clock control. 1 1 read-write SR Self-refresh request, EMCSREFREQ. 2 1 read-write MMC Memory clock control. 5 1 read-write I SDRAM initialization. 7 2 read-write DYNAMICREFRESH Configures dynamic memory refresh 0x24 32 read-write 0 0x7FF REFRESH Refresh timer. 0 11 read-write DYNAMICREADCONFIG Configures dynamic memory read strategy 0x28 32 read-write 0 0x3 RD Read data strategy. 0 2 read-write DYNAMICRP Precharge command period 0x30 32 read-write 0xF 0xF TRP Precharge command period. 0 4 read-write DYNAMICRAS Active to precharge command period 0x34 32 read-write 0xF 0xF TRAS Active to precharge command period. 0 4 read-write DYNAMICSREX Self-refresh exit time 0x38 32 read-write 0xF 0xF TSREX Self-refresh exit time. 0 4 read-write DYNAMICAPR Last-data-out to active command time 0x3C 32 read-write 0xF 0xF TAPR Last-data-out to active command time. 0 4 read-write DYNAMICDAL Data-in to active command time 0x40 32 read-write 0xF 0xF TDAL Data-in to active command. 0 4 read-write DYNAMICWR Write recovery time 0x44 32 read-write 0xF 0xF TWR Write recovery time. 0 4 read-write DYNAMICRC Selects the active to active command period 0x48 32 read-write 0x1F 0x1F TRC Active to active command period. 0 5 read-write DYNAMICRFC Selects the auto-refresh period 0x4C 32 read-write 0x1F 0x1F TRFC Auto-refresh period and auto-refresh to active command period. 0 5 read-write DYNAMICXSR Time for exit self-refresh to active command 0x50 32 read-write 0x1F 0x1F TXSR Exit self-refresh to active command time. 0 5 read-write DYNAMICRRD Latency for active bank A to active bank B 0x54 32 read-write 0xF 0xF TRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. 0 4 read-write DYNAMICMRD Time for load mode register to active command 0x58 32 read-write 0xF 0xF TMRD Load mode register to active command time. 0 4 read-write STATICEXTENDEDWAIT Time for long static memory read and write transfers 0x80 32 read-write 0 0x3FF EXTENDEDWAIT Extended wait time out. 0 10 read-write DMA0 LPC5411x DMA controller DMA 0x40082000 0 0x5DC registers DMA0 1 30 0x10 CHANNEL[%s] no description available 0x400 CFG Configuration register for DMA channel . 0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write DISABLED Disabled. Peripheral DMA requests are disabled. 0 ENABLED Enabled. Peripheral DMA requests are enabled. 0x1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write DISABLED Disabled. Hardware triggering is not used. 0 ENABLED Enabled. Use hardware triggering. 0x1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write ACTIVE_LOW_FALLING Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 0 ACTIVE_HIGH_RISING Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 0x1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write EDGE Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 0 LEVEL Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. 0x1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write SINGLE Single transfer. Hardware trigger causes a single transfer. 0 BURST Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. 0x1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write DISABLED Disabled. Source burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Source burst wrapping is enabled for this DMA channel. 0x1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write DISABLED Disabled. Destination burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Destination burst wrapping is enabled for this DMA channel. 0x1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT Control and status register for DMA channel . 0x4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only NO_EFFECT No effect. No effect on DMA operation. 0 VALID_PENDING Valid pending. 0x1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only NOT_TRIGGERED Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 0 TRIGGERED Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 0x1 XFERCFG Transfer configuration register for DMA channel . 0x8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write NOT_VALID Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 0 VALID Valid. The current channel descriptor is considered valid. 0x1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write DISABLED Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 0 ENABLED Enabled. Reload the channels' control structure when the current descriptor is exhausted. 0x1 SWTRIG Software Trigger. 2 1 read-write NOT_SET Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 0 SET Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. 0x1 CLRTRIG Clear Trigger. 3 1 read-write NOT_CLEARED Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 0 CLEARED Cleared. The trigger is cleared when this descriptor is exhausted 0x1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write NO_EFFECT No effect. 0 SET Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 0x1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write NO_EFFECT No effect. 0 SET Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 0x1 WIDTH Transfer width used for this DMA channel. 8 2 read-write BIT_8 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 0 BIT_16 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 0x1 BIT_32 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 0x2 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write NO_INCREMENT No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0 WIDTH_X_1 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 0x1 WIDTH_X_2 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 0x3 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write NO_INCREMENT No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0 WIDTH_X_1 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 0x1 WIDTH_X_2 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 0x3 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CTRL DMA control. 0 32 read-write 0 0x1 ENABLE DMA controller master enable. 0 1 read-write DISABLED Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 0 ENABLED Enabled. The DMA controller is enabled. 0x1 INTSTAT Interrupt status. 0x4 32 read-only 0 0x6 ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1 1 read-only NOT_PENDING Not pending. No enabled interrupts are pending. 0 PENDING Pending. At least one enabled interrupt is pending. 0x1 ACTIVEERRINT Summarizes whether any error interrupts are pending. 2 1 read-only NOT_PENDING Not pending. No error interrupts are pending. 0 PENDING Pending. At least one error interrupt is pending. 0x1 SRAMBASE SRAM address of the channel configuration table. 0x8 32 read-write 0 0xFFFFFE00 OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. 9 23 read-write ENABLESET0 Channel Enable read and Set for all DMA channels. 0x20 32 read-write 0 0xFFFFFFFF ENA Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 0 32 read-write ENABLECLR0 Channel Enable Clear for all DMA channels. 0x28 32 write-only 0 0 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only ACTIVE0 Channel Active status for all DMA channels. 0x30 32 read-only 0 0xFFFFFFFF ACT Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 0 32 read-only BUSY0 Channel Busy status for all DMA channels. 0x38 32 read-only 0 0xFFFFFFFF BSY Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 0 32 read-only ERRINT0 Error Interrupt status for all DMA channels. 0x40 32 read-write 0 0xFFFFFFFF ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. 0 32 read-write INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x48 32 read-write 0 0xFFFFFFFF INTEN Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 0 32 read-write INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x50 32 write-only 0 0 CLR Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only INTA0 Interrupt A status for all DMA channels. 0x58 32 read-write 0 0xFFFFFFFF IA Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. 0 32 read-write INTB0 Interrupt B status for all DMA channels. 0x60 32 read-write 0 0xFFFFFFFF IB Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. 0 32 read-write SETVALID0 Set ValidPending control bits for all DMA channels. 0x68 32 write-only 0 0 SV SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n 0 32 write-only SETTRIG0 Set Trigger control bits for all DMA channels. 0x70 32 write-only 0 0 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. 0 32 write-only ABORT0 Channel Abort control for all DMA channels. 0x78 32 write-only 0 0 ABORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. 0 32 write-only LCD LPC5460x LCD controller LCD 0x40083000 0 0xC30 registers LCD 53 TIMH Horizontal Timing Control register 0 32 read-write 0 0xFFFFFFFC PPL Pixels-per-line. 2 6 read-write HSW Horizontal synchronization pulse width. 8 8 read-write HFP Horizontal front porch. 16 8 read-write HBP Horizontal back porch. 24 8 read-write TIMV Vertical Timing Control register 0x4 32 read-write 0 0xFFFFFFFF LPP Lines per panel. 0 10 read-write VSW Vertical synchronization pulse width. 10 6 read-write VFP Vertical front porch. 16 8 read-write VBP Vertical back porch. 24 8 read-write POL Clock and Signal Polarity Control register 0x8 32 read-write 0 0xFFFF7FDF PCD_LO Lower five bits of panel clock divisor. 0 5 read-write ACB AC bias pin frequency. 6 5 read-write IVS Invert vertical synchronization. 11 1 read-write IHS Invert horizontal synchronization. 12 1 read-write IPC Invert panel clock. 13 1 read-write IOE Invert output enable. 14 1 read-write CPL Clocks per line. 16 10 read-write BCD Bypass panel clock divider. 26 1 read-write PCD_HI Upper five bits of panel clock divisor. 27 5 read-write LE Line End Control register 0xC 32 read-write 0 0x1007F LED Line-end delay. 0 7 read-write LEE LCD Line end enable. 16 1 read-write UPBASE Upper Panel Frame Base Address register 0x10 32 read-write 0 0xFFFFFFF8 LCDUPBASE LCD upper panel base address. 3 29 read-write LPBASE Lower Panel Frame Base Address register 0x14 32 read-write 0 0xFFFFFFF8 LCDLPBASE LCD lower panel base address. 3 29 read-write CTRL LCD Control register 0x18 32 read-write 0 0x13FFF LCDEN LCD enable control bit. 0 1 read-write LCDBPP LCD bits per pixel. 1 3 read-write LCDBW STN LCD monochrome/color selection. 4 1 read-write LCDTFT LCD panel TFT type selection. 5 1 read-write LCDMONO8 Monochrome LCD interface width. 6 1 read-write LCDDUAL Single or Dual LCD panel selection. 7 1 read-write BGR Color format selection. 8 1 read-write BEBO Big-endian Byte Order. 9 1 read-write BEPO Big-Endian Pixel Ordering. 10 1 read-write LCDPWR LCD power enable. 11 1 read-write LCDVCOMP LCD Vertical Compare Interrupt. 12 2 read-write WATERMARK LCD DMA FIFO watermark level. 16 1 read-write INTMSK Interrupt Mask register 0x1C 32 read-write 0 0x1E FUFIM FIFO underflow interrupt enable. 1 1 read-write LNBUIM LCD next base address update interrupt enable. 2 1 read-write VCOMPIM Vertical compare interrupt enable. 3 1 read-write BERIM AHB master error interrupt enable. 4 1 read-write INTRAW Raw Interrupt Status register 0x20 32 read-only 0 0x1E FUFRIS FIFO underflow raw interrupt status. 1 1 read-only LNBURIS LCD next address base update raw interrupt status. 2 1 read-only VCOMPRIS Vertical compare raw interrupt status. 3 1 read-only BERRAW AHB master bus error raw interrupt status. 4 1 read-only INTSTAT Masked Interrupt Status register 0x24 32 read-only 0 0x1E FUFMIS FIFO underflow masked interrupt status. 1 1 read-only LNBUMIS LCD next address base update masked interrupt status. 2 1 read-only VCOMPMIS Vertical compare masked interrupt status. 3 1 read-only BERMIS AHB master bus error masked interrupt status. 4 1 read-only INTCLR Interrupt Clear register 0x28 32 read-write 0 0x1E FUFIC FIFO underflow interrupt clear. 1 1 write-only LNBUIC LCD next address base update interrupt clear. 2 1 write-only VCOMPIC Vertical compare interrupt clear. 3 1 write-only BERIC AHB master error interrupt clear. 4 1 read-write UPCURR Upper Panel Current Address Value register 0x2C 32 read-only 0 0xFFFFFFFF LCDUPCURR LCD Upper Panel Current Address. 0 32 read-only LPCURR Lower Panel Current Address Value register 0x30 32 read-only 0 0xFFFFFFFF LCDLPCURR LCD Lower Panel Current Address. 0 32 read-only 128 0x4 PAL[%s] 256x16-bit Color Palette registers 0x200 32 read-write 0 0xFFFFFFFF R04_0 Red palette data. 0 5 read-write G04_0 Green palette data. 5 5 read-write B04_0 Blue palette data. 10 5 read-write I0 Intensity / unused bit. 15 1 read-write R14_0 Red palette data. 16 5 read-write G14_0 Green palette data. 21 5 read-write B14_0 Blue palette data. 26 5 read-write I1 Intensity / unused bit. 31 1 read-write 256 0x4 CRSR_IMG[%s] Cursor Image registers 0x800 32 read-write 0 0xFFFFFFFF CRSR_IMG Cursor Image data. 0 32 read-write CRSR_CTRL Cursor Control register 0xC00 32 read-write 0 0x31 CRSRON Cursor enable. 0 1 read-write CRSRNUM1_0 Cursor image number. 4 2 read-write CRSR_CFG Cursor Configuration register 0xC04 32 read-write 0 0x3 CRSRSIZE Cursor size selection. 0 1 read-write FRAMESYNC Cursor frame synchronization type. 1 1 read-write CRSR_PAL0 Cursor Palette register 0 0xC08 32 read-write 0 0xFFFFFF RED Red color component. 0 8 read-write GREEN Green color component. 8 8 read-write BLUE Blue color component. 16 8 read-write CRSR_PAL1 Cursor Palette register 1 0xC0C 32 read-write 0 0xFFFFFF RED Red color component. 0 8 read-write GREEN Green color component. 8 8 read-write BLUE Blue color component. 16 8 read-write CRSR_XY Cursor XY Position register 0xC10 32 read-write 0 0x3FF03FF CRSRX X ordinate of the cursor origin measured in pixels. 0 10 read-write CRSRY Y ordinate of the cursor origin measured in pixels. 16 10 read-write CRSR_CLIP Cursor Clip Position register 0xC14 32 read-write 0 0x3F3F CRSRCLIPX Cursor clip position for X direction. 0 6 read-write CRSRCLIPY Cursor clip position for Y direction. 8 6 read-write CRSR_INTMSK Cursor Interrupt Mask register 0xC20 32 read-write 0 0x1 CRSRIM Cursor interrupt mask. 0 1 read-write CRSR_INTCLR Cursor Interrupt Clear register 0xC24 32 write-only 0 0x1 CRSRIC Cursor interrupt clear. 0 1 write-only CRSR_INTRAW Cursor Raw Interrupt Status register 0xC28 32 read-only 0 0x1 CRSRRIS Cursor raw interrupt status. 0 1 read-only CRSR_INTSTAT Cursor Masked Interrupt Status register 0xC2C 32 read-only 0 0x1 CRSRMIS Cursor masked interrupt status. 0 1 read-only USB0 LPC5411x USB 2.0 Device Controller USB 0x40084000 0 0x38 registers USB0_NEEDCLK 27 USB0 28 DEVCMDSTAT USB Device Command/Status register 0 32 read-write 0x800 0x171BFBFF DEV_ADDR USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. 0 7 read-write DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. 7 1 read-write SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on: 9 1 read-write NORMAL USB_NEEDCLK has normal function. 0 ALWAYS_ON USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. 0x1 LPM_SUP LPM Supported: 11 1 read-write NO LPM not supported. 0 YES LPM supported. 0x1 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP 12 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP 13 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CO Interrupt on NAK for control OUT EP 14 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CI Interrupt on NAK for control IN EP 15 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. 16 1 read-write DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. 17 1 read-write LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. 20 1 read-only DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. 24 1 read-write DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. 25 1 read-write DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. 26 1 read-write VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. 28 1 read-only INFO USB Info register 0x4 32 read-write 0 0x7FFF FRAME_NR Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 0 11 read-only ERR_CODE The error code which last occurred: 11 4 read-write NO_ERROR No error 0 PID_ENCODING_ERROR PID encoding error 0x1 PID_UNKNOWN PID unknown 0x2 PACKET_UNEXPECTED Packet unexpected 0x3 TOKEN_CRC_ERROR Token CRC error 0x4 DATA_CRC_ERROR Data CRC error 0x5 TIMEOUT Time out 0x6 BABBLE Babble 0x7 TRUNCATED_EOP Truncated EOP 0x8 SENT_RECEIVED_NAK Sent/Received NAK 0x9 SENT_STALL Sent Stall 0xA OVERRUN Overrun 0xB SENT_EMPTY_PACKET Sent empty packet 0xC BITSTUFF_ERROR Bitstuff error 0xD SYNC_ERROR Sync error 0xE WRONG_DATA_TOGGLE Wrong data toggle 0xF MINREV Minor Revision. 16 8 read-only MAJREV Major Revision. 24 8 read-only EPLISTSTART USB EP Command/Status List start address 0x8 32 read-write 0 0xFFFFFF00 EP_LIST Start address of the USB EP Command/Status List. 8 24 read-write DATABUFSTART USB Data buffer start address 0xC 32 read-write 0 0xFFC00000 DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. 22 10 read-write LPM USB Link Power Management register 0x10 32 read-write 0 0x1FF HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token 0 4 read-only HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. 8 1 read-write EPSKIP USB Endpoint skip 0x14 32 read-write 0 0x3FFFFFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. 0 10 read-write EPINUSE USB Endpoint Buffer in use 0x18 32 read-write 0 0x3FC BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. 2 8 read-write EPBUFCFG USB Endpoint Buffer Configuration register 0x1C 32 read-write 0 0x3FC BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. 2 8 read-write INTSTAT USB interrupt status register 0x20 32 read-write 0 0xC00003FF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. 0 1 read-write EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. 9 1 read-write FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. 30 1 read-write DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. 31 1 read-write INTEN USB interrupt enable register 0x24 32 read-write 0 0xC00003FF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 0 10 read-write FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 31 1 read-write INTSETSTAT USB set interrupt status register 0x28 32 read-write 0 0xC00003FF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 0 10 read-write FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 31 1 read-write EPTOGGLE USB Endpoint toggle register 0x34 32 read-write 0 0x3FF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 0 10 read-write SCT0 SCTimer/PWM (SCT) SCT 0x40085000 0 0x550 registers SCT0 12 10 0x8 EV[%s] no description available 0x300 EV_STATE SCT event state register 0 0 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 16 read-write EV_CTRL SCT event control register 0 0x4 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write L_COUNTER Selects the L state and the L match register selected by MATCHSEL. 0 H_COUNTER Selects the H state and the H match register selected by MATCHSEL. 0x1 OUTSEL Input/output select 5 1 read-write INPUT Selects the inputs selected by IOSEL. 0 OUTPUT Selects the outputs selected by IOSEL. 0x1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write LOW LOW 0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write OR OR. The event occurs when either the specified match or I/O condition occurs. 0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write ADD STATEV value is added into STATE (the carry-out is ignored). 0 LOAD STATEV value is loaded into STATE. 0x1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write DIRECTION_INDEPENDENT Direction independent. This event is triggered regardless of the count direction. 0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 10 0x8 OUT[%s] no description available 0x500 OUT_SET SCT output 0 set register 0 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write OUT_CLR SCT output 0 clear register 0x4 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write CONFIG SCT configuration register 0 32 read-write 0x1E00 0x61FFF UNIFY SCT operation 0 1 read-write DUAL_COUNTER The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 0 UNIFIED_COUNTER The SCT operates as a unified 32-bit counter. 0x1 CLKMODE SCT clock mode 1 2 read-write SYSTEM_CLOCK_MODE System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 0 SAMPLED_SYSTEM_CLOCK_MODE Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. 0x1 SCT_INPUT_CLOCK_MODE SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 0x2 ASYNCHRONOUS_MODE Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. 0x3 CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. 3 4 read-write INPUT_0_RISING_EDGES Rising edges on input 0. 0 INPUT_0_FALLING_EDGE Falling edges on input 0. 0x1 INPUT_1_RISING_EDGES Rising edges on input 1. 0x2 INPUT_1_FALLING_EDGE Falling edges on input 1. 0x3 INPUT_2_RISING_EDGES Rising edges on input 2. 0x4 INPUT_2_FALLING_EDGE Falling edges on input 2. 0x5 INPUT_3_RISING_EDGES Rising edges on input 3. 0x6 INPUT_3_FALLING_EDGE Falling edges on input 3. 0x7 INPUT_4_RISING_EDGES Rising edges on input 4. 0x8 INPUT_4_FALLING_EDGE Falling edges on input 4. 0x9 INPUT_5_RISING_EDGES Rising edges on input 5. 0xA INPUT_5_FALLING_EDGE Falling edges on input 5. 0xB INPUT_6_RISING_EDGES Rising edges on input 6. 0xC INPUT_6_FALLING_EDGE Falling edges on input 6. 0xD INPUT_7_RISING_EDGES Rising edges on input 7. 0xE INPUT_7_FALLING_EDGE Falling edges on input 7. 0xF NORELOAD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 18 1 read-write CTRL SCT control register 0x4 32 read-write 0x40004 0x1FFF1FFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0 1 read-write STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 3 1 read-write BIDIR_L L or unified counter direction select 4 1 read-write UP Up. The counter counts up to a limit condition, then is cleared to zero. 0 UP_DOWN Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 0x1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. 19 1 read-write BIDIR_H Direction select 20 1 read-write UP The H counter counts up to its limit condition, then is cleared to zero. 0 UP_DOWN The H counter counts up to its limit, then counts down to a limit condition or to 0. 0x1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 21 8 read-write LIMIT SCT limit event select register 0x8 32 read-write 0 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write HALT SCT halt event select register 0xC 32 read-write 0 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write STOP SCT stop event select register 0x10 32 read-write 0 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write START SCT start event select register 0x14 32 read-write 0 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write COUNT SCT counter register 0x40 32 read-write 0 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. 0 16 read-write CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 16 16 read-write STATE SCT state register 0x44 32 read-write 0 0x1F001F STATE_L State variable. 0 5 read-write STATE_H State variable. 16 5 read-write INPUT SCT input register 0x48 32 read-only 0 0xFFFFFFFF AIN0 Input 0 state. Input 0 state on the last SCT clock edge. 0 1 read-only AIN1 Input 1 state. Input 1 state on the last SCT clock edge. 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. 4 1 read-only AIN5 Input 5 state. Input 5 state on the last SCT clock edge. 5 1 read-only AIN6 Input 6 state. Input 6 state on the last SCT clock edge. 6 1 read-only AIN7 Input 7 state. Input 7 state on the last SCT clock edge. 7 1 read-only AIN8 Input 8 state. Input 8 state on the last SCT clock edge. 8 1 read-only AIN9 Input 9 state. Input 9 state on the last SCT clock edge. 9 1 read-only AIN10 Input 10 state. Input 10 state on the last SCT clock edge. 10 1 read-only AIN11 Input 11 state. Input 11 state on the last SCT clock edge. 11 1 read-only AIN12 Input 12 state. Input 12 state on the last SCT clock edge. 12 1 read-only AIN13 Input 13 state. Input 13 state on the last SCT clock edge. 13 1 read-only AIN14 Input 14 state. Input 14 state on the last SCT clock edge. 14 1 read-only AIN15 Input 15 state. Input 15 state on the last SCT clock edge. 15 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. 20 1 read-only SIN5 Input 5 state. Input 5 state following the synchronization specified by INSYNC. 21 1 read-only SIN6 Input 6 state. Input 6 state following the synchronization specified by INSYNC. 22 1 read-only SIN7 Input 7 state. Input 7 state following the synchronization specified by INSYNC. 23 1 read-only SIN8 Input 8 state. Input 8 state following the synchronization specified by INSYNC. 24 1 read-only SIN9 Input 9 state. Input 9 state following the synchronization specified by INSYNC. 25 1 read-only SIN10 Input 10 state. Input 10 state following the synchronization specified by INSYNC. 26 1 read-only SIN11 Input 11 state. Input 11 state following the synchronization specified by INSYNC. 27 1 read-only SIN12 Input 12 state. Input 12 state following the synchronization specified by INSYNC. 28 1 read-only SIN13 Input 13 state. Input 13 state following the synchronization specified by INSYNC. 29 1 read-only SIN14 Input 14 state. Input 14 state following the synchronization specified by INSYNC. 30 1 read-only SIN15 Input 15 state. Input 15 state following the synchronization specified by INSYNC. 31 1 read-only REGMODE SCT match/capture mode register 0x4C 32 read-write 0 0xFFFFFFFF REGMOD_L Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. 0 16 read-write REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. 16 16 read-write OUTPUT SCT output register 0x50 32 read-write 0 0xFFFF OUT Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write OUTPUTDIRCTRL SCT output counter direction control register 0x54 32 read-write 0 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 2 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 4 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 8 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 10 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 12 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 14 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 16 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 18 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR10 Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. 20 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 22 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 24 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 26 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 28 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 30 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RES SCT conflict resolution register 0x58 32 read-write 0 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. 0 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. 2 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. 4 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. 6 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. 8 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. 10 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O6RES Effect of simultaneous set and clear on output 6. 12 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR6 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O7RES Effect of simultaneous set and clear on output 7. 14 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR7 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O8RES Effect of simultaneous set and clear on output 8. 16 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR8 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O9RES Effect of simultaneous set and clear on output 9. 18 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR9 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O10RES Effect of simultaneous set and clear on output 10. 20 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR10 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O11RES Effect of simultaneous set and clear on output 11. 22 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR11 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O12RES Effect of simultaneous set and clear on output 12. 24 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR12 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O13RES Effect of simultaneous set and clear on output 13. 26 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR13 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O14RES Effect of simultaneous set and clear on output 14. 28 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR14 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O15RES Effect of simultaneous set and clear on output 15. 30 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR15 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 DMAREQ0 SCT DMA request 0 register 0x5C 32 read-write 0 0xC000FFFF DEV_0 If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write DMAREQ1 SCT DMA request 1 register 0x60 32 read-write 0 0xC000FFFF DEV_1 If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write EVEN SCT event interrupt enable register 0xF0 32 read-write 0 0xFFFF IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write EVFLAG SCT event flag register 0xF4 32 read-write 0 0xFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write CONEN SCT conflict interrupt enable register 0xF8 32 read-write 0 0xFFFF NCEN The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write CONFLAG SCT conflict flag register 0xFC 32 read-write 0 0xC000FFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 31 1 read-write CAP0 SCT capture register of capture channel CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH0 SCT match value register of match channels CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP1 SCT capture register of capture channel CAP_MATCH 0x104 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH1 SCT match value register of match channels CAP_MATCH 0x104 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP2 SCT capture register of capture channel CAP_MATCH 0x108 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH2 SCT match value register of match channels CAP_MATCH 0x108 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP3 SCT capture register of capture channel CAP_MATCH 0x10C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH3 SCT match value register of match channels CAP_MATCH 0x10C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP4 SCT capture register of capture channel CAP_MATCH 0x110 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH4 SCT match value register of match channels CAP_MATCH 0x110 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP5 SCT capture register of capture channel CAP_MATCH 0x114 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH5 SCT match value register of match channels CAP_MATCH 0x114 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP6 SCT capture register of capture channel CAP_MATCH 0x118 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH6 SCT match value register of match channels CAP_MATCH 0x118 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP7 SCT capture register of capture channel CAP_MATCH 0x11C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH7 SCT match value register of match channels CAP_MATCH 0x11C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP8 SCT capture register of capture channel CAP_MATCH 0x120 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH8 SCT match value register of match channels CAP_MATCH 0x120 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP9 SCT capture register of capture channel CAP_MATCH 0x124 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH9 SCT match value register of match channels CAP_MATCH 0x124 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAPCTRL0 SCT capture control register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL0 SCT match reload value register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL1 SCT capture control register CAPCTRL_MATCHREL 0x204 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL1 SCT match reload value register CAPCTRL_MATCHREL 0x204 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL2 SCT capture control register CAPCTRL_MATCHREL 0x208 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL2 SCT match reload value register CAPCTRL_MATCHREL 0x208 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL3 SCT capture control register CAPCTRL_MATCHREL 0x20C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL3 SCT match reload value register CAPCTRL_MATCHREL 0x20C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL4 SCT capture control register CAPCTRL_MATCHREL 0x210 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL4 SCT match reload value register CAPCTRL_MATCHREL 0x210 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL5 SCT capture control register CAPCTRL_MATCHREL 0x214 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL5 SCT match reload value register CAPCTRL_MATCHREL 0x214 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL6 SCT capture control register CAPCTRL_MATCHREL 0x218 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL6 SCT match reload value register CAPCTRL_MATCHREL 0x218 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL7 SCT capture control register CAPCTRL_MATCHREL 0x21C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL7 SCT match reload value register CAPCTRL_MATCHREL 0x21C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL8 SCT capture control register CAPCTRL_MATCHREL 0x220 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL8 SCT match reload value register CAPCTRL_MATCHREL 0x220 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL9 SCT capture control register CAPCTRL_MATCHREL 0x224 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL9 SCT match reload value register CAPCTRL_MATCHREL 0x224 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write FLEXCOMM0 LPC5411x Flexcomm serial communication FLEXCOMM FLEXCOMM 0x40086000 0 0x1000 registers FLEXCOMM0 14 PSELID Peripheral Select and Flexcomm ID register. 0xFF8 32 read-write 0x101000 0xFFFFF0FF PERSEL Peripheral Select. This field is writable by software. 0 3 read-write NO_PERIPH_SELECTED No peripheral selected. 0 USART USART function selected. 0x1 SPI SPI function selected. 0x2 I2C I2C function selected. 0x3 I2S_TRANSMIT I2S transmit function selected. 0x4 I2S_RECEIVE I2S receive function selected. 0x5 LOCK Lock the peripheral select. This field is writable by software. 3 1 read-write UNLOCKED Peripheral select can be changed by software. 0 LOCKED Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. 0x1 USARTPRESENT USART present indicator. This field is Read-only. 4 1 read-only NOT_PRESENT This Flexcomm does not include the USART function. 0 PRESENT This Flexcomm includes the USART function. 0x1 SPIPRESENT SPI present indicator. This field is Read-only. 5 1 read-only NOT_PRESENT This Flexcomm does not include the SPI function. 0 PRESENT This Flexcomm includes the SPI function. 0x1 I2CPRESENT I2C present indicator. This field is Read-only. 6 1 read-only NOT_PRESENT This Flexcomm does not include the I2C function. 0 PRESENT This Flexcomm includes the I2C function. 0x1 I2SPRESENT I 2S present indicator. This field is Read-only. 7 1 read-only NOT_PRESENT This Flexcomm does not include the I2S function. 0 PRESENT This Flexcomm includes the I2S function. 0x1 ID Flexcomm ID. 12 20 read-only PID Peripheral identification register. 0xFFC 32 read-write 0 0xFFFFFFFF Minor_Rev Minor revision of module implementation. 8 4 read-only Major_Rev Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-write FLEXCOMM1 LPC5411x Flexcomm serial communication FLEXCOMM 0x40087000 0 0x1000 registers FLEXCOMM1 15 FLEXCOMM2 LPC5411x Flexcomm serial communication FLEXCOMM 0x40088000 0 0x1000 registers FLEXCOMM2 16 FLEXCOMM3 LPC5411x Flexcomm serial communication FLEXCOMM 0x40089000 0 0x1000 registers FLEXCOMM3 17 FLEXCOMM4 LPC5411x Flexcomm serial communication FLEXCOMM 0x4008A000 0 0x1000 registers FLEXCOMM4 18 FLEXCOMM5 LPC5411x Flexcomm serial communication FLEXCOMM 0x40096000 0 0x1000 registers FLEXCOMM5 19 FLEXCOMM6 LPC5411x Flexcomm serial communication FLEXCOMM 0x40097000 0 0x1000 registers FLEXCOMM6 20 FLEXCOMM7 LPC5411x Flexcomm serial communication FLEXCOMM 0x40098000 0 0x1000 registers FLEXCOMM7 21 FLEXCOMM8 LPC5411x Flexcomm serial communication FLEXCOMM 0x40099000 0 0x1000 registers FLEXCOMM8 40 FLEXCOMM9 LPC5411x Flexcomm serial communication FLEXCOMM 0x4009A000 0 0x1000 registers FLEXCOMM9 41 I2C0 LPC5411x I2C-bus interfaces FLEXCOMM0 I2C I2C 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG Configuration for shared functions. 0x800 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write DISABLED Disabled. The I2C Master function is disabled. 0 ENABLED Enabled. The I2C Master function is enabled. 0x1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write DISABLED Disabled. The I2C slave function is disabled. 0 ENABLED Enabled. The I2C slave function is enabled. 0x1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write DISABLED Disabled. The I2C Monitor function is disabled. 0 ENABLED Enabled. The I2C Monitor function is enabled. 0x1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write DISABLED Disabled. Time-out function is disabled. 0 ENABLED Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. 0x1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write DISABLED Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 0 ENABLED Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. 0x1 HSCAPABLE High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. 5 1 read-write FAST_MODE_PLUS Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, 0 HIGH_SPEED High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. 0x1 STAT Status register for Master, Slave, and Monitor functions. 0x804 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only IN_PROGRESS In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 0 PENDING Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. 0x1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only IDLE Idle. The Master function is available to be used for a new transaction. 0 RECEIVE_READY Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x1 TRANSMIT_READY Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x2 NACK_ADDRESS NACK Address. Slave NACKed address. 0x3 NACK_DATA NACK Data. Slave NACKed transmitted data. 0x4 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write NO_LOSS No Arbitration Loss has occurred. 0 ARBITRATION_LOSS Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 0x1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write NO_ERROR No Start/Stop Error has occurred. 0 ERROR The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. 0x1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only IN_PROGRESS In progress. The Slave function does not currently need service. 0 PENDING Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 0x1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only SLAVE_ADDRESS Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 0 SLAVE_RECEIVE Slave receive. Received data is available (Slave Receiver mode). 0x1 SLAVE_TRANSMIT Slave transmit. Data can be transmitted (Slave Transmitter mode). 0x2 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only STRETCHING Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 0 NOT_STRETCHING Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 0x1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only ADDRESS0 Address 0. Slave address 0 was matched. 0 ADDRESS1 Address 1. Slave address 1 was matched. 0x1 ADDRESS2 Address 2. Slave address 2 was matched. 0x2 ADDRESS3 Address 3. Slave address 3 was matched. 0x3 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only NOT_SELECTED Not selected. The Slave function is not currently selected. 0 SELECTED Selected. The Slave function is currently selected. 0x1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write NOT_DESELECTED Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. 0 DESELECTED Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 0x1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only NO_DATA No data. The Monitor function does not currently have data available. 0 DATA_WAITING Data waiting. The Monitor function has data waiting to be read. 0x1 MONOV Monitor Overflow flag. 17 1 read-write NO_OVERRUN No overrun. Monitor data has not overrun. 0 OVERRUN Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 0x1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only INACTIVE Inactive. The Monitor function considers the I2C bus to be inactive. 0 ACTIVE Active. The Monitor function considers the I2C bus to be active. 0x1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write NOT_IDLE Not idle. The I2C bus is not idle, or this flag has been cleared by software. 0 IDLE Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 0x1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write NO_TIMEOUT No time-out. I2C bus events have not caused a time-out. 0 EVEN_TIMEOUT Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 0x1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write NO_TIMEOUT No time-out. SCL low time has not caused a time-out. 0 TIMEOUT Time-out. SCL low time has caused a time-out. 0x1 INTENSET Interrupt Enable Set and read register. 0x808 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write DISABLED Disabled. The MstPending interrupt is disabled. 0 ENABLED Enabled. The MstPending interrupt is enabled. 0x1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write DISABLED Disabled. The MstArbLoss interrupt is disabled. 0 ENABLED Enabled. The MstArbLoss interrupt is enabled. 0x1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write DISABLED Disabled. The MstStStpErr interrupt is disabled. 0 ENABLED Enabled. The MstStStpErr interrupt is enabled. 0x1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write DISABLED Disabled. The SlvPending interrupt is disabled. 0 ENABLED Enabled. The SlvPending interrupt is enabled. 0x1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write DISABLED Disabled. The SlvNotStr interrupt is disabled. 0 ENABLED Enabled. The SlvNotStr interrupt is enabled. 0x1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write DISABLED Disabled. The SlvDeSel interrupt is disabled. 0 ENABLED Enabled. The SlvDeSel interrupt is enabled. 0x1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write DISABLED Disabled. The MonRdy interrupt is disabled. 0 ENABLED Enabled. The MonRdy interrupt is enabled. 0x1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write DISABLED Disabled. The MonOv interrupt is disabled. 0 ENABLED Enabled. The MonOv interrupt is enabled. 0x1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write DISABLED Disabled. The MonIdle interrupt is disabled. 0 ENABLED Enabled. The MonIdle interrupt is enabled. 0x1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write DISABLED Disabled. The Event time-out interrupt is disabled. 0 ENABLED Enabled. The Event time-out interrupt is enabled. 0x1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write DISABLED Disabled. The SCL time-out interrupt is disabled. 0 ENABLED Enabled. The SCL time-out interrupt is enabled. 0x1 INTENCLR Interrupt Enable Clear register. 0x80C 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x810 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x814 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x818 32 read-only 0x801 0x30B8951 MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x820 32 read-write 0 0xE MSTCONTINUE Master Continue. This bit is write-only. 0 1 write-only NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 0x1 MSTSTART Master Start control. This bit is write-only. 1 1 read-write NO_EFFECT No effect. 0 START Start. A Start will be generated on the I2C bus at the next allowed time. 0x1 MSTSTOP Master Stop control. This bit is write-only. 2 1 read-write NO_EFFECT No effect. 0 STOP Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). 0x1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write DISABLED Disable. No DMA requests are generated for master operation. 0 ENABLED Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 0x1 MSTTIME Master timing configuration. 0x824 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write CLOCKS_2 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0 CLOCKS_3 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x1 CLOCKS_4 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x2 CLOCKS_5 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x3 CLOCKS_6 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x4 CLOCKS_7 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x5 CLOCKS_8 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x6 CLOCKS_9 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 0x7 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write CLOCKS_2 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 0 CLOCKS_3 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 0x1 CLOCKS_4 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 0x2 CLOCKS_5 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 0x3 CLOCKS_6 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x4 CLOCKS_7 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x5 CLOCKS_8 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x6 CLOCKS_9 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 0x7 MSTDAT Combined Master receiver and transmitter data register. 0x828 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x840 32 read-write 0 0x30B SLVCONTINUE Slave Continue. 0 1 read-write NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. 0x1 SLVNACK Slave NACK. 1 1 read-write NO_EFFECT No effect. 0 NACK NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 0x1 SLVDMA Slave DMA enable. 3 1 read-write DISABLED Disabled. No DMA requests are issued for Slave mode operation. 0 ENABLED Enabled. DMA requests are issued for I2C slave data transmission and reception. 0x1 AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. 8 1 read-write NORMAL Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 0 AUTOMATIC_ACK A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. 0x1 AUTOMATCHREAD When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. 9 1 read-write I2C_WRITE The expected next operation in Automatic Mode is an I2C write. 0 I2C_READ The expected next operation in Automatic Mode is an I2C read. 0x1 SLVDAT Combined Slave receiver and transmitter data register. 0x844 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write 4 0x4 SLVADR[%s] Slave address register. 0x848 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write AUTONACK Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. 15 1 read-write NORMAL Normal operation, matching I2C addresses are not ignored. 0 AUTOMATIC Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. 0x1 SLVQUAL0 Slave Qualification for address 0. 0x858 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write MASK Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 0 EXTEND Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 0x1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x880 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only NO_START_DETECTED No start detected. The Monitor function has not detected a Start event on the I2C bus. 0 START_DETECTED Start detected. The Monitor function has detected a Start event on the I2C bus. 0x1 MONRESTART Monitor Received Repeated Start. 9 1 read-only NOT_DETECTED No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 0 DETECTED Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 0x1 MONNACK Monitor Received NACK. 10 1 read-only ACKNOWLEDGED Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 0 NOT_ACKNOWLEDGED Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 0x1 ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only I2C1 LPC5411x I2C-bus interfaces FLEXCOMM1 I2C 0x40087000 0 0x1000 registers FLEXCOMM1 15 I2C2 LPC5411x I2C-bus interfaces FLEXCOMM2 I2C 0x40088000 0 0x1000 registers FLEXCOMM2 16 I2C3 LPC5411x I2C-bus interfaces FLEXCOMM3 I2C 0x40089000 0 0x1000 registers FLEXCOMM3 17 I2C4 LPC5411x I2C-bus interfaces FLEXCOMM4 I2C 0x4008A000 0 0x1000 registers FLEXCOMM4 18 I2C5 LPC5411x I2C-bus interfaces FLEXCOMM5 I2C 0x40096000 0 0x1000 registers FLEXCOMM5 19 I2C6 LPC5411x I2C-bus interfaces FLEXCOMM6 I2C 0x40097000 0 0x1000 registers FLEXCOMM6 20 I2C7 LPC5411x I2C-bus interfaces FLEXCOMM7 I2C 0x40098000 0 0x1000 registers FLEXCOMM7 21 I2C8 LPC5411x I2C-bus interfaces FLEXCOMM8 I2C 0x40099000 0 0x1000 registers FLEXCOMM8 40 I2C9 LPC5411x I2C-bus interfaces FLEXCOMM9 I2C 0x4009A000 0 0x1000 registers FLEXCOMM9 41 SPI0 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM0 SPI SPI 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG SPI Configuration register 0x400 32 read-write 0 0xFBD ENABLE SPI enable. 0 1 read-write DISABLED Disabled. The SPI is disabled and the internal state machine and counters are reset. 0 ENABLED Enabled. The SPI is enabled for operation. 0x1 MASTER Master mode select. 2 1 read-write SLAVE_MODE Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 0 MASTER_MODE Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 0x1 LSBF LSB First mode enable. 3 1 read-write STANDARD Standard. Data is transmitted and received in standard MSB first order. 0 REVERSE Reverse. Data is transmitted and received in reverse order (LSB first). 0x1 CPHA Clock Phase select. 4 1 read-write CHANGE Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. 0 CAPTURE Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. 0x1 CPOL Clock Polarity select. 5 1 read-write LOW Low. The rest state of the clock (between transfers) is low. 0 HIGH High. The rest state of the clock (between transfers) is high. 0x1 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 7 1 read-write DISABLED Disabled. 0 ENABLED Enabled. 0x1 SPOL0 SSEL0 Polarity select. 8 1 read-write LOW Low. The SSEL0 pin is active low. 0 HIGH High. The SSEL0 pin is active high. 0x1 SPOL1 SSEL1 Polarity select. 9 1 read-write LOW Low. The SSEL1 pin is active low. 0 HIGH High. The SSEL1 pin is active high. 0x1 SPOL2 SSEL2 Polarity select. 10 1 read-write LOW Low. The SSEL2 pin is active low. 0 HIGH High. The SSEL2 pin is active high. 0x1 SPOL3 SSEL3 Polarity select. 11 1 read-write LOW Low. The SSEL3 pin is active low. 0 HIGH High. The SSEL3 pin is active high. 0x1 DLY SPI Delay register 0x404 32 read-write 0 0xFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 0 4 read-write POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 12 4 read-write STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position. 0x408 32 read-write 0x100 0x1C0 SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. 8 1 read-only INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x40C 32 read-write 0 0x130 SSAEN Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 4 1 read-write DISABLED Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0 ENABLED Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0x1 SSDEN Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 5 1 read-write DISABLED Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 0 ENABLED Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. 0x1 MSTIDLEEN Master idle interrupt enable. 8 1 read-write DISABLED No interrupt will be generated when the SPI master function is idle. 0 ENABLED An interrupt will be generated when the SPI master function is fully idle. 0x1 INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x410 32 write-only 0 0 SSAEN Writing 1 clears the corresponding bit in the INTENSET register. 4 1 write-only SSDEN Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only MSTIDLE Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DIV SPI clock Divider 0x424 32 read-write 0 0xFFFF DIVVAL Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. 0 16 read-write INTSTAT SPI Interrupt Status 0x428 32 read-only 0 0x130 SSA Slave Select Assert. 4 1 read-only SSD Slave Select Deassert. 5 1 read-only MSTIDLE Master Idle status flag. 8 1 read-only FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write POPDBG Pop FIFO for debug reads. 18 1 read-write DO_NOT_POP Debug reads of the FIFO do not pop the FIFO. 0 POP A debug read will cause the FIFO to pop. 0x1 FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 16 read-write TXSSEL0_N Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. 16 1 write-only ASSERTED SSEL0 asserted. 0 NOT_ASSERTED SSEL0 not asserted. 0x1 TXSSEL1_N Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. 17 1 write-only ASSERTED SSEL1 asserted. 0 NOT_ASSERTED SSEL1 not asserted. 0x1 TXSSEL2_N Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. 18 1 write-only ASSERTED SSEL2 asserted. 0 NOT_ASSERTED SSEL2 not asserted. 0x1 TXSSEL3_N Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. 19 1 write-only ASSERTED SSEL3 asserted. 0 NOT_ASSERTED SSEL3 not asserted. 0x1 EOT End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. 20 1 write-only NOT_DEASSERTED SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 0 DEASSERTED SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 0x1 EOF End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 21 1 write-only NOT_EOF Data not EOF. This piece of data transmitted is not treated as the end of a frame. 0 EOF Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. 0x1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. 22 1 write-only READ Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. 0 IGNORE Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 0x1 LEN Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. 24 4 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. 20 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. 16 1 read-only RXSSEL1_N Slave Select for receive. 17 1 read-only RXSSEL2_N Slave Select for receive. 18 1 read-only RXSSEL3_N Slave Select for receive. 19 1 read-only SOT Start of transfer flag. 20 1 read-only ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only SPI1 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM1 SPI 0x40087000 0 0x1000 registers FLEXCOMM1 15 SPI2 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM2 SPI 0x40088000 0 0x1000 registers FLEXCOMM2 16 SPI3 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM3 SPI 0x40089000 0 0x1000 registers FLEXCOMM3 17 SPI4 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM4 SPI 0x4008A000 0 0x1000 registers FLEXCOMM4 18 SPI5 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM5 SPI 0x40096000 0 0x1000 registers FLEXCOMM5 19 SPI6 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM6 SPI 0x40097000 0 0x1000 registers FLEXCOMM6 20 SPI7 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM7 SPI 0x40098000 0 0x1000 registers FLEXCOMM7 21 SPI8 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM8 SPI 0x40099000 0 0x1000 registers FLEXCOMM8 40 SPI9 LPC5411x Serial Peripheral Interfaces (SPI) FLEXCOMM9 SPI 0x4009A000 0 0x1000 registers FLEXCOMM9 41 USART0 LPC5411x USARTs FLEXCOMM0 USART USART 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write DISABLED Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. 0 ENABLED Enabled. The USART is enabled for operation. 0x1 DATALEN Selects the data size for the USART. 2 2 read-write BIT_7 7 bit Data length. 0 BIT_8 8 bit Data length. 0x1 BIT_9 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 0x2 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write NO_PARITY No parity. 0 EVEN_PARITY Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write BIT_1 1 stop bit. 0 BITS_2 2 stop bits. This setting should only be used for asynchronous communication. 0x1 MODE32K Selects standard or 32 kHz clocking mode. 7 1 read-write DISABLED Disabled. USART uses standard clocking. 0 ENABLED Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 0x1 LINMODE LIN break mode enable. 8 1 read-write DISABLED Disabled. Break detect and generate is configured for normal operation. 0 ENABLED Enabled. Break detect and generate is configured for LIN bus operation. 0x1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write DISABLED No flow control. The transmitter does not receive any automatic flow control signal. 0 ENABLED Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 0x1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write ASYNCHRONOUS_MODE Asynchronous mode. 0 SYNCHRONOUS_MODE Synchronous mode. 0x1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write FALLING_EDGE Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE Rising edge. Un_RXD is sampled on the rising edge of SCLK. 0x1 SYNCMST Synchronous mode Master select. 14 1 read-write SLAVE Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER Master. When synchronous mode is enabled, the USART is a master. 0x1 LOOP Selects data loopback mode. 15 1 read-write NORMAL Normal operation. 0 LOOPBACK Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 0x1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write DISABLED Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 0 ENABLED Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. 0x1 AUTOADDR Automatic Address matching enable. 19 1 read-write DISABLED Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 0 ENABLED Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. 0x1 OESEL Output Enable Select. 20 1 read-write STANDARD Standard. The RTS signal is used as the standard flow control function. 0 RS_485 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 0x1 OEPOL Output Enable Polarity. 21 1 read-write LOW Low. If selected by OESEL, the output enable is active low. 0 HIGH High. If selected by OESEL, the output enable is active high. 0x1 RXPOL Receive data polarity. 22 1 read-write STANDARD Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 TXPOL Transmit data polarity. 23 1 read-write STANDARD Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write NORMAL Normal operation. 0 CONTINOUS Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 0x1 ADDRDET Enable address detect mode. 2 1 read-write DISABLED Disabled. The USART presents all incoming data. 0 ENABLED Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 0x1 TXDIS Transmit Disable. 6 1 read-write ENABLED Not disabled. USART transmitter is not disabled. 0 DISABLED Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 0x1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write CLOCK_ON_CHARACTER Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINOUS_CLOCK Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 0x1 CLRCCONRX Clear Continuous Clock. 9 1 read-write NO_EFFECT No effect. No effect on the CC bit. 0 AUTO_CLEAR Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 0x1 AUTOBAUD Autobaud enable. 16 1 read-write DISABLED Disabled. USART is in normal operating mode. 0 ENABLED Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. 0x1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xA 0x45A RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). 6 1 read-only RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F868 TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. 15 1 read-write ABERREN When 1, enables an interrupt when an auto baud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-only 0 0x1F968 TXIDLE Transmitter Idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERRINT Auto baud Error Interrupt flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write POPDBG Pop FIFO for debug reads. 18 1 read-write DO_NOT_POP Debug reads of the FIFO do not pop the FIFO. 0 POP A debug read will cause the FIFO to pop. 0x1 FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 9 read-write FIFORD FIFO read data. 0xE30 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only USART1 LPC5411x USARTs FLEXCOMM1 USART 0x40087000 0 0x1000 registers FLEXCOMM1 15 USART2 LPC5411x USARTs FLEXCOMM2 USART 0x40088000 0 0x1000 registers FLEXCOMM2 16 USART3 LPC5411x USARTs FLEXCOMM3 USART 0x40089000 0 0x1000 registers FLEXCOMM3 17 USART4 LPC5411x USARTs FLEXCOMM4 USART 0x4008A000 0 0x1000 registers FLEXCOMM4 18 USART5 LPC5411x USARTs FLEXCOMM5 USART 0x40096000 0 0x1000 registers FLEXCOMM5 19 USART6 LPC5411x USARTs FLEXCOMM6 USART 0x40097000 0 0x1000 registers FLEXCOMM6 20 USART7 LPC5411x USARTs FLEXCOMM7 USART 0x40098000 0 0x1000 registers FLEXCOMM7 21 USART8 LPC5411x USARTs FLEXCOMM8 USART 0x40099000 0 0x1000 registers FLEXCOMM8 40 USART9 LPC5411x USARTs FLEXCOMM9 USART 0x4009A000 0 0x1000 registers FLEXCOMM9 41 GPIO LPC5411x General Purpose I/O (GPIO) GPIO 0x4008C000 0 0x2498 registers 6 0x20 B[%s] no description available 0 32 0x1 B_[%s] Byte pin registers for all port 0 and 1 GPIO pins 0 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write 6 0x80 W[%s] no description available 0x1000 32 0x4 W_[%s] Word pin registers for all port 0 and 1 GPIO pins 0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write 6 0x4 DIR[%s] Direction registers 0x2000 32 read-write 0 0xFFFFFFFF DIRP Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. 0 32 read-write 6 0x4 MASK[%s] Mask register 0x2080 32 read-write 0 0xFFFFFFFF MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. 0 32 read-write 6 0x4 PIN[%s] Port pin register 0x2100 32 read-write 0 0xFFFFFFFF PORT Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. 0 32 read-write 6 0x4 MPIN[%s] Masked port register 0x2180 32 read-write 0 0xFFFFFFFF MPORTP Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 0 32 read-write 6 0x4 SET[%s] Write: Set register for port Read: output bits for port 0x2200 32 read-write 0 0xFFFFFFFF SETP Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 32 read-write 6 0x4 CLR[%s] Clear port 0x2280 32 write-only 0 0 CLRP Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. 0 32 write-only 6 0x4 NOT[%s] Toggle port 0x2300 32 write-only 0 0 NOTP Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. 0 32 write-only 6 0x4 DIRSET[%s] Set pin direction bits for port 0x2380 32 write-only 0 0 DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 29 write-only 6 0x4 DIRCLR[%s] Clear pin direction bits for port 0x2400 32 write-only 0 0 DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 29 write-only 6 0x4 DIRNOT[%s] Toggle pin direction bits for port 0x2480 32 write-only 0 0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 29 write-only DMIC0 LPC5411x DMIC Subsystem (DMIC)) DMIC 0x40090000 0 0x1000 registers DMIC0 25 HWVAD0 26 2 0x100 CHANNEL[%s] no description available 0 OSR Oversample Rate register 0 0 32 read-write 0 0xFF OSR Selects the oversample rate for the related input channel. 0 8 read-write DIVHFCLK DMIC Clock Register 0 0x4 32 read-write 0 0xF PDMDIV PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others = reserved. 0 4 read-write PREAC2FSCOEF Pre-Emphasis Filter Coefficient for 2 FS register 0x8 32 read-write 0 0x3 COMP Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation = 13 0 2 read-write PREAC4FSCOEF Pre-Emphasis Filter Coefficient for 4 FS register 0xC 32 read-write 0 0x3 COMP Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation = 13 0 2 read-write GAINSHIFT Decimator Gain Shift register 0x10 32 read-write 0 0x3F GAIN Gain control, as a positive or negative (two's complement) number of bits to shift. 0 6 read-write FIFO_CTRL FIFO Control register 0 0x80 32 read-write 0 0x1F000F ENABLE FIFO enable. 0 1 read-write DISABLED FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed. 0 ENABLED FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. 0x1 RESETN FIFO reset. 1 1 read-write RESET Reset the FIFO. 0 NORMAL Normal operation 0x1 INTEN Interrupt enable. 2 1 read-write DISABLED FIFO level interrupts are not enabled. 0 ENABLED FIFO level interrupts are enabled. 0x1 DMAEN DMA enable 3 1 read-write DISABLED DMA requests are not enabled. 0 ENABLED DMA requests based on FIFO level are enabled. 0x1 TRIGLVL FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). 16 5 read-write FIFO_STATUS FIFO Status register 0 0x84 32 read-write 0 0x7 INT Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC subsystem must be running in order for an interrupt to occur. 0 1 read-write OVERRUN Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one to this bit clears the flag. This flag does not cause an interrupt. 1 1 read-write UNDERRUN Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. 2 1 read-write FIFO_DATA FIFO Data Register 0 0x88 32 read-write 0 0xFFFFFF DATA Data from the top of the input filter FIFO. 0 24 read-write PHY_CTRL PDM Source Configuration register 0 0x8C 32 read-write 0 0x3 PHY_FALL Capture PDM_DATA 0 1 read-write RISING_EDGE Capture PDM_DATA on the rising edge of PDM_CLK. 0 FALLING_EDGE Capture PDM_DATA on the falling edge of PDM_CLK. 0x1 PHY_HALF Half rate sampling 1 1 read-write STANDARD Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. 0 HALF_RATE Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing. 0x1 DC_CTRL DC Control register 0 0x90 32 read-write 0 0x1F3 DCPOLE DC block filter 0 2 read-write FLAT_RESPONSE Flat response, no filter. 0 HZ_155 155 Hz. 0x1 HZ_78 78 Hz. 0x2 HZ_39 39 Hz 0x3 DCGAIN Fine gain adjustment in the form of a number of bits to downshift. 4 4 read-write SATURATEAT16BIT Selects 16-bit saturation. 8 1 read-write DO_NOT_SATURATE Results roll over if out range and do not saturate. 0 SATURATE If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. 0x1 CHANEN Channel Enable register 0xF00 32 read-write 0 0x3 EN_CH0 Enable channel 0. When 1, PDM channel 0 is enabled. 0 1 read-write EN_CH1 Enable channel 1. When 1, PDM channel 1 is enabled. 1 1 read-write IOCFG I/O Configuration register 0xF0C 32 read-write 0 0x7 CLK_BYPASS0 Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides for the possibility of an external codec taking over the PDM bus. 0 1 read-write CLK_BYPASS1 Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides for the possibility of an external codec taking over the PDM bus. 1 1 read-write STEREO_DATA0 Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a configuration that supports a single stereo digital microphone. 2 1 read-write USE2FS Use 2FS register 0xF10 32 read-write 0 0x1 USE2FS Use 2FS register 0 1 read-write USE_1FS Use 1FS output for PCM data. 0 USE_2FS Use 2FS output for PCM data. 0x1 HWVADGAIN HWVAD input gain register 0xF80 32 read-write 0x5 0xF INPUTGAIN Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04 -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved. 0 4 read-write HWVADHPFS HWVAD filter control register 0xF84 32 read-write 0x1 0x3 HPFS High pass filter 0 2 read-write BYPASS First filter by-pass. 0 HIGH_PASS_1750HZ High pass filter with -3dB cut-off at 1750Hz. 0x1 HIGH_PASS_215HZ High pass filter with -3dB cut-off at 215Hz. 0x2 HWVADST10 HWVAD control register 0xF88 32 read-write 0 0x1 ST10 Stage 0 0 1 read-write NORMAL Normal operation, waiting for HWVAD trigger event (stage 0). 0 RESET Reset internal interrupt flag by writing a '1' pulse. 0x1 HWVADRSTT HWVAD filter reset register 0xF8C 32 read-write 0 0x1 RSTT Writing a 1 resets all filter values 0 1 read-write HWVADTHGN HWVAD noise estimator gain register 0xF90 32 read-write 0 0xF THGN Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1. 0 4 read-write HWVADTHGS HWVAD signal estimator gain register 0xF94 32 read-write 0x4 0xF THGS Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1. 0 4 read-write HWVADLOWZ HWVAD noise envelope estimator register 0xF98 32 read-only 0 0xFFFF LOWZ Noise envelope estimator value. 0 16 read-only ID Module Identification register 0xFFC 32 read-only 0x2 0xFFFFFFFF ID Indicates module ID and the number of channels in this DMIC interface. 0 32 read-only ENET LPC5460x Ethernet controller ENET 0x40092000 0 0x11E4 registers ETHERNET 49 ETHERNET_PMT 50 ETHERNET_MACLP 51 2 0x40 MTL_QUEUE[%s] no description available 0xD00 MTL_TXQx_OP_MODE MTL TxQx Operation Mode register 0 32 read-write 0 0x7007F FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. 0 1 read-write TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. 1 1 read-write TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue 0. 2 2 read-write TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. 4 3 read-write TQS Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. 16 3 read-write MTL_TXQx_UNDRFLW MTL TxQx Underflow register 0x4 32 read-only 0 0xFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. 0 11 read-only UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. 11 1 read-only MTL_TXQx_DBG MTL TxQx Debug register 0x8 32 read-only 0 0x77003F TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled - Reception of 802. 0 1 read-only TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the Packet Abort request from the MAC. 1 2 read-only TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue. 3 1 read-only TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 4 1 read-only TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. 5 1 read-only PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. 16 3 read-only STSXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. 20 3 read-only MTL_TXQx_ETS_CTRL MTL TxQx ETS control register, only TxQ1 support 0x10 32 read-write 0 0x7C AVALG AV Algorithm. 2 1 read-write CC Credit Control. 3 1 read-write SLC Credit Control. 4 3 read-only MTL_TXQx_ETS_STAT MTL TxQx ETS Status register 0x14 32 read-write 0 0xFFFFFF ABS Average Bits per Slot. 0 24 read-write MTL_TXQx_QNTM_WGHT no description available 0x18 32 read-write 0 0x1FFFFF ISCQW Average Bits per Slot. 0 21 read-write MTL_TXQx_SNDSLP_CRDT MTL TxQx SendSlopCredit register, only TxQ1 support 0x1C 32 read-write 0 0xFFFFFF SSC sendSlopeCredit. 0 14 read-write MTL_TXQx_HI_CRDT MTL TxQx hiCredit register, only TxQ1 support 0x20 32 read-write 0 0x1FFFFFFF HC hiCredit. 0 29 read-write MTL_TXQx_LO_CRDT MTL TxQx loCredit register, only TxQ1 support 0x24 32 read-write 0 0x1FFFFFFF LC loCredit. 0 29 read-write MTL_TXQx_INTCTRL_STAT no description available 0x2C 32 read-write 0 0x1010303 TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. 0 1 read-write ABPSIS Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. 1 1 read-write TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. 8 1 read-write ABPSIE Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the interrupt when the average bits per slot status is updated. 9 1 read-write RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. 16 1 read-write RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. 24 1 read-write MTL_RXQx_OP_MODE MTL RxQx Operation Mode register 0x30 32 read-write 0 0x70007B RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. 0 2 read-write FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. 3 1 read-write FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, Mll_ER, watchdog timeout, or overflow). 4 1 read-write RSF Receive Queue Store and Forward When this bit is set, the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. 5 1 read-write DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. 6 1 read-write RQS This field indicates the size of the allocated Receive queues in blocks of 256 bytes. 20 3 read-write MTL_RXQx_MISSPKT_OVRFLW_CNT MTL RxQx Missed Packet Overflow Counter register 0x34 32 read-write 0 0xFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow. 0 11 read-write OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-only MTL_RXQx_DBG MTL RxQx Debug register 0x38 32 read-write 0 0x3FFF0037 RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. 0 1 read-write RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status. 1 2 read-only RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full. 4 2 read-only PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. 16 14 read-only MTL_RXQx_CTRL MTL RxQx Control register 0x3C 32 read-write 0 0xF RXQ_WEGT Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration When this bit is set, the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. 3 1 read-write 2 0x80 DMA_CH[%s] no description available 0x1100 DMA_CHx_CTRL DMA Channelx Control 0 32 read-write 0 0x1D0000 PBLx8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times. 16 1 read-write DSL Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit, 64-bit, or 128-bit bus) to skip between two unchained s. 18 3 read-write DMA_CHx_TX_CTRL DMA Channelx Transmit Control 0x4 32 read-write 0 0x3F001F ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. 0 1 read-write TCW Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel. 1 3 read-write OSF Operate on Second Frame When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write TxPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. 16 6 read-write DMA_CHx_RX_CTRL DMA Channelx Receive Control 0x8 32 read-write 0 0x803F7FF9 SR Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive list and processes the incoming packets. 0 1 read-write RBSZ Receive Buffer size This field indicates the size of the Rx buffers specified in bytes. 3 12 read-write RxPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. 16 6 read-write RPF DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred. 31 1 read-write DMA_CHx_TXDESC_LIST_ADDR no description available 0x14 32 read-write 0 0xFFFFFFFC STL Start of transmit list This field contains the base address of the first in the Transmit list. 2 30 read-write DMA_CHx_RXDESC_LIST_ADDR no description available 0x1C 32 read-write 0 0xFFFFFFFC SRL Start of receive list This field contains the base address of the First in the Receive list. 2 30 read-write DMA_CHx_TXDESC_TAIL_PTR no description available 0x20 32 read-write 0 0xFFFFFFFC TDTP Transmit Tail Pointer This field contains the tail pointer for the Tx ring. 2 30 read-write DMA_CHx_RXDESC_TAIL_PTR no description available 0x28 32 read-write 0 0xFFFFFFFC RDTP Receive Tail Pointer This field contains the tail pointer for the Rx ring. 2 30 read-write DMA_CHx_TXDESC_RING_LENGTH no description available 0x2C 32 read-write 0 0x3FF TDRL Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring. 0 10 read-write DMA_CHx_RXDESC_RING_LENGTH Channelx Rx descriptor Ring Length 0x30 32 read-write 0 0x3FF RDRL Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring. 0 10 read-write DMA_CHx_INT_EN Channelx Interrupt Enable 0x34 32 read-write 0 0xDFC7 TIE Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. 0 1 read-write TSE Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. 1 1 read-write TBUE Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. 2 1 read-write RIE Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. 6 1 read-write RBUE Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. 7 1 read-write RSE Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. 8 1 read-write RWTE Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. 9 1 read-write ETIE Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. 10 1 read-write ERIE Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. 11 1 read-write FBEE Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. 12 1 read-write AIE Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled. 14 1 read-write NIE Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. 15 1 read-write DMA_CHx_RX_INT_WDTIMER Receive Interrupt Watchdog Timer 0x38 32 read-write 0 0xFF RIWT Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. 0 8 read-write DMA_CHx_SLOT_FUNC_CTRL_STAT Slot Function Control and Status 0x3C 32 read-write 0 0xF0003 ESC Enable Slot Comparison When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. 0 1 read-write ASC Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or, ahead of the reference slot number by up to two slots This bit is applicable only when the ESC bit is set. 1 1 read-write RSN Reference Slot Number This field gives the current value of the reference slot number in the DMA. 16 4 read-only DMA_CHx_CUR_HST_TXDESC Channelx Current Host Transmit descriptor 0x44 32 read-only 0 0xFFFFFFFF HTD Host Transmit descriptor Address Pointer Cleared on Reset. 0 32 read-only DMA_CHx_CUR_HST_RXDESC no description available 0x4C 32 read-only 0 0xFFFFFFFF HRD Host Receive descriptor Address Pointer Cleared on Reset. 0 32 read-only DMA_CHx_CUR_HST_TXBUF no description available 0x54 32 read-only 0 0xFFFFFFFF HTB Host Transmit Buffer Address Pointer Cleared on Reset. 0 32 read-only DMA_CHx_CUR_HST_RXBUF Channelx Current Application Receive Buffer Address 0x5C 32 read-only 0 0xFFFFFFFF HRB Host Receive Buffer Address Pointer Cleared on Reset. 0 32 read-only DMA_CHx_STAT Channelx DMA status register 0x60 32 read-write 0 0x7DFC7 TI Transmit Interrupt This bit indicates that the packet transmission is complete. 0 1 read-write TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list, and the DMA cannot acquire it. 2 1 read-write RI Receive Interrupt This bit indicates that the packet reception is complete. 6 1 read-write RBU Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list, and the DMA cannot acquire it. 7 1 read-write RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write RWT Receive Watchdog time out This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write ETI Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. 10 1 read-write ERI Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet. 11 1 read-write FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). 12 1 read-write AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. 14 1 read-write NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal Interrupt Summary bit. 15 1 read-write EB DMA Error Bits This field indicates the type of error that caused a Bus Error. 16 3 read-write MAC_CONFIG MAC configuration register 0 32 read-write 0x8000 0xFFFFF7F RE Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. 0 1 read-write TE Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. 1 1 read-write PRELEN Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. 2 2 read-write DC Deferral Check When this bit is set, the deferral check function is enabled in the MAC. 4 1 read-write BL Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. 5 2 read-write DR Disable Retry When this bit is set, the MAC will attempt only one transmission. 8 1 read-write DCRS Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter ignores the MII CRS signal during packet transmission in the half-duplex mode. 9 1 read-write DO Disable Receive Own When this bit is set, the MAC disables the reception of frames when the gmii_txen_o is asserted in Half-Duplex mode. 10 1 read-write ECRSFD Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. 11 1 read-write LM Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. 12 1 read-write DM Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously. 13 1 read-write FES Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by default and is enabled only when RMII/SMII is enabled during configuration. 14 1 read-write PS Portselect. 15 1 read-only JE Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for tagged frames) without reporting a giant frame error in the receive frame status. 16 1 read-write JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. 17 1 read-write BE Packet Burst Enable When this bit is set, the MAC allows packet bursting during transmission in the MII half-duplex mode. 18 1 read-write WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. 19 1 read-write ACS Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. 20 1 read-write CST CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. 21 1 read-write S2KP IEEE 802. 22 1 read-write GPSLCE Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet. 23 1 read-write IPG Inter-Packet Gap These bits control the minimum IPG between packets during transmission. 24 3 read-write IPC Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. 27 1 read-write MAC_EXT_CONFIG no description available 0x4 32 read-write 0 0x73FFF GPSL Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. 0 14 read-write DCRCC Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does not check the CRC field in the received packets. 16 1 read-write SPEN Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. 17 1 read-write USP Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and MAC Address Low Table 748 registers. 18 1 read-write MAC_FRAME_FILTER MAC frame filter register 0x8 32 read-write 0 0x800003F9 PR Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. 0 1 read-write DAIF DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. 3 1 read-write PM Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. 4 1 read-write DBF Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. 5 1 read-write PCF Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). 6 2 read-write SAIF SA Inverse Filtering When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. 8 1 read-only SAF Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. 9 1 read-only RA Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. 31 1 read-write MAC_WD_TIMEROUT MAC watchdog Timeout register 0xC 32 read-write 0 0x10F WTO Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register Table 722 is reset, this field is used as watchdog timeout for a received packet. 0 4 read-write PWE Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet. 8 1 read-write MAC_VLAN_TAG MAC vlan tag register 0x50 32 read-write 0 0xFFFF VL VLAN Tag Identifier for Receive Packets. 0 16 read-write ETV Enable 12-Bit VLAN Tag Comparison. 16 1 read-write VTIM VLAN Tag Inverse Match Enable. 17 1 read-write ESVL Enable S-VLAN. 18 1 read-write ERSVLM Enable Receive S-VLAN Match. 19 1 read-write DOVLTC Disable VLAN Type Check. 20 1 read-write EVLS Enable VLAN Tag Stripping on Receive. 21 2 read-write EVLRXS Enable VLAN Tag in Rx status. 24 1 read-write VTHM Disable VLAN Type Check. 25 1 read-write EDVLP Enable Double VLAN Processing. 26 1 read-write ERIVLT Enable Inner VLAN Tag. 27 1 read-write EIVLS Enable Inner VLAN Tag Stripping on Receive. 28 2 read-write EIVLRXS Enable Inner VLAN Tag in Rx Status. 31 1 read-write 2 0x4 MAC_TX_FLOW_CTRL_Q[%s] Transmit flow control register 0x70 32 read-write 0 0xFFFF00F3 FCB Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). 0 1 read-write TFE Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. 1 1 read-write PLT Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control signal is checked for automatic retransmission of PAUSE Frame. 4 3 read-write DZPQ Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. 7 1 read-write PT Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. 16 16 read-write MAC_RX_FLOW_CTRL Receive flow control register 0x90 32 read-write 0 0x3 RFE Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. 0 1 read-write UP Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802. 1 1 read-write MAC_TXQ_PRIO_MAP no description available 0x98 32 read-write 0 0xFFFF PSTQ0 Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software. 0 8 read-write PSTQ1 Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. 8 8 read-write MAC_RXQ_CTRL0 Receive Queue Control 0 register 0x0000 0xA0 32 read-write 0 0xFFFFFFFF RXQ0EN Receive Queue 0 Enable. 0 2 read-write RXQ1EN Receive Queue 1 Enable. 2 2 read-write MAC_RXQ_CTRL1 Receive Queue Control 0 register 0x0000 0xA4 32 read-write 0 0xFFFFFFFF AVCPQ AV Untagged Control Packets Queue. 0 3 read-write AVPTPQ AV PTP Packets Queue. 4 3 read-write UPQ Untagged Packet Queue. 12 3 read-write MCBCQ Multicast and Broadcast Queue. 16 3 read-write MCBCQEN Multicast and Broadcast Queue Enable. 20 1 read-write MAC_RXQ_CTRL2 Receive Queue Control 0 register 0x0000 0xA8 32 read-write 0 0xFFFFFFFF PSRQ0 Priorities Selected in the Receive Queue 0. 0 8 read-write PSRQ1 Priorities Selected in the Receive Queue 1. 8 8 read-write PSRQ2 Priorities Selected in the Receive Queue 2. 16 8 read-write PSRQ3 Priorities Selected in the Receive Queue 3. 24 8 read-write MAC_INTR_STAT Interrupt status register 0x0000 0xB0 32 read-only 0 0xFFFFFFFF PHYIS PHY Interrupt. 3 1 read-only PMTIS PMT Interrupt Status. 4 1 read-only LPIIS LPI Interrupt Status. 5 1 read-only TSIS Timestamp interrupt status. 12 1 read-only TXSTSIS Transmit Status Interrupt. 13 1 read-only RXSTSIS Receive Status Interrupt. 14 1 read-only MAC_INTR_EN Interrupt enable register 0x0000 0xB4 32 read-write 0 0xFFFFFFFF PHYIE PHY Interrupt Enable. 3 1 read-write PMTIE PMT Interrupt Enable. 4 1 read-write LPIIE LPI Interrupt Enable. 5 1 read-write TSIE Timestamp Interrupt Enable. 12 1 read-write TXSTSIE Transmit Status Interrupt Enable. 13 1 read-write RXSTSIS Receive Status Interrupt Enable. 14 1 read-write MAC_RXTX_STAT Receive Transmit Status register 0xB8 32 read-only 0 0x13F TJT PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731. 0 1 read-only NCARR No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. 1 1 read-only LCARR Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the loss of carrier occurred during packet transmission, that is, the PHY Carrier signal was inactive for one or more transmission clock periods during packet transmission. 2 1 read-only EXDEF Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when Jumbo packet is enabled). 3 1 read-only LCOL Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode). 4 1 read-only EXCOL Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. 5 1 read-only RWT Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC Configuration register Table 722. 8 1 read-only MAC_PMT_CRTL_STAT no description available 0xC0 32 read-write 0 0x9F000667 PWRDWN Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. 0 1 read-only MGKPKTEN Magic Packet Enable. 1 1 read-only RWKPKTEN Remote Wake-Up Packet Enable When this bit is set, a power management event is generated when the MAC receives a remote wake-up packet. 2 1 read-only MGKPRCVD Magic Packet Received. 5 1 read-only RWKPRCVD Remote Wake-Up Packet Received. 6 1 read-only GLBLUCAST Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet. 9 1 read-write RWKPFE Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wake-up frame. 10 1 read-write RWKPTR Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote Wake-up Packet Filter register pointer. 24 5 read-write RWKFILTRST Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the remote wake-up packet filter register pointer is reset to 3'b000. 31 1 read-write MAC_RWAKE_FRFLT Remote wake-up frame filter 0xC4 32 read-write 0 0xFFFFFFFF ADDR WKUPFMFILTER address. 0 32 read-write MAC_LPI_CTRL_STAT LPI Control and Status Register 0xD0 32 read-write 0 0x3B030F TLPIEN Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. 0 1 read-only TLPIEX Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. 1 1 read-only RLPIEN Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. 2 1 read-only RLPIEX Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal reception. 3 1 read-only TLPIST Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface. 8 1 read-only RLPIST Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface. 9 1 read-only LPIEN LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. 16 1 read-write PLS PHY Link Status This bit indicates the link status of the PHY. 17 1 read-write LPITXA LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. 19 1 read-write LPIATE LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. 20 1 read-write LPITCSE LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. 21 1 read-write MAC_LPI_TIMER_CTRL LPI Timers Control register 0xD4 32 read-write 0 0x3FFFFFF TWT LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. 0 16 read-write LST LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. 16 10 read-write MAC_LPI_ENTR_TIMR LPI entry Timer register 0xD8 32 read-write 0 0xFFFF8 LPIET LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter LPI mode, after it has transmitted all the frames. 3 17 read-write MAC_1US_TIC_COUNTR no description available 0xDC 32 read-write 0 0xFFF TIC_1US_CNTR 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. 0 12 read-write MAC_VERSION MAC version register 0x110 32 read-write 0 0x20FF SNPVER NXP defined version. 0 8 read-write USERVER User defined version. 8 8 read-write MAC_DBG MAC debug register 0x114 32 read-only 0 0x70007 REPESTS MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC MII receive protocol engine is actively receiving data, and it is not in the Idle state. 0 1 read-only RFCFCSTS MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. 1 2 read-only TPESTS MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC or MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. 16 1 read-only TFCSTS MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. 17 2 read-only MAC_HW_FEAT0 MAC hardware feature register 0x0201 0x11C 32 read-write 0 0xFFFFFFFF MIISEL 10 or 100 Mbps Support. 0 1 read-only HDSEL Half-duplex Support. 2 1 read-only VLHASH Hash Table Based Filtering option. 4 1 read-only SMASEL SMA (MDIO) Interface. 5 1 read-only RWKSEL PMT Remote Wake-up Packet Detection. 6 1 read-only MGKSEL PMT magic packet detection. 7 1 read-write MMCSEL RMON Module Enable. 8 1 read-only ARPOFFSEL ARP Offload Enabled. 9 1 read-only TSSEL IEEE 1588-2008 Timestamp support . 12 1 read-only EEESEL Energy Efficient Ethernet Support . 13 1 read-only TXCOESEL Transmit Checksum Offload Support. 14 1 read-only RXCOESEL Receive Checksum Offload Support. 16 1 read-write TSSTSSEL Timestamp System Time Source. 25 2 read-only ACTPHYSEL Active PHY Selected. 28 3 read-only MAC_HW_FEAT1 MAC hardware feature register 0x0201 0x120 32 read-only 0 0xFFFFFFFF RXFIFOSIZE MTL Receive FIFO Size. 0 5 read-only TXFIFOSIZE MTL Transmit FIFO Size. 6 5 read-only OSTEN One-Step Timestamping Feature. 11 1 read-only PTOEN PTP OffLoad Feature. 12 1 read-only ADVTHWORD IEEE 1588 High Word Register Feature. 13 1 read-only ADDR64 Address width. 14 2 read-only DCBEN Data Center Bridging feature. 16 1 read-only SPEN Split Header Structure feature. 17 1 read-only TSOEN TCP Segment Offload Feature. 18 1 read-only DBGMEMA DMA Debug Register Feature. 19 1 read-only AVSEL Audio Video Bridging Feature. 20 1 read-only LPMODEEN Low Power Mode Feature Support . 23 1 read-only HASHTBLSZ Hash Table Size. 24 2 read-only L3_L4_FILTER Total Number of L3 and L4 Filters . 27 4 read-only MAC_HW_FEAT2 MAC hardware feature register 0x0201 0x124 32 read-only 0 0xFFFFFFFF RXQCNT Number of MTL Receive Queues. 0 4 read-only TXQCNT Number of MTL Transmit Queues. 6 4 read-only RXCHCNT Number of DMA Receive Channels. 12 4 read-only TXCHCNT Number of DMA Transmit Channels. 18 4 read-only PPSOUTNUM Number of PPS Outputs. 24 3 read-only AUXSNAPNUM Number of Auxiliary Snapshot Inputs. 28 3 read-only MAC_MDIO_ADDR MIDO address Register 0x200 32 read-write 0 0xFFF7F0D MB MII busy. 0 1 read-write MOC MII Operation Command. 2 2 read-write CR CSR Clock Range. 8 4 read-write NTC Number of Training Clocks This field controls the number of trailing clock cycles generated on MDC after the end of transmission of MDIO frame. 12 3 read-write RDA Register/Device Address These bits select the PHY register in selected PHY device. 16 5 read-write PA Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing. 21 5 read-write BTB Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). 26 1 read-write PSE Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit preamble and transmit MDIO frames with only 1 preamble bit. 27 1 read-write MAC_MDIO_DATA MDIO Data register 0x204 32 read-write 0 0xFFFF MD MII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 0 16 read-write MAC_ADDR_HIGH MAC address0 high register 0x300 32 read-write 0x8000FFFF 0x8001FFFF A47_32 MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. 0 16 read-write DCS DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address content is routed. 16 1 read-write AE Address Enable. 31 1 read-only MAC_ADDR_LOW MAC address0 low register 0x304 32 read-write 0xFFFFFFFF 0xFFFFFFFF A31_0 MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. 0 32 read-write MAC_TIMESTAMP_CTRL Time stamp control register 0xB00 32 read-write 0x2000 0x1107FF3F TSENA Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. 0 1 read-write TSCFUPDT Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. 1 1 read-write TSINIT Initialize Timestamp When this bit is set, the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update. 2 1 read-write TSUPDT Update Timestamp When this bit is set, the system time is updated (added or subtracted) with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time Nanoseconds Update Table 754. 3 1 read-write TSTRIG Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. 4 1 read-write TADDREG Update Addend Register When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. 5 1 read-write TSENALL Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. 8 1 read-write TSCTRLSSR Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. 9 1 read-write TSVER2ENA Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. 10 1 read-write TSIPENA Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. 11 1 read-write TSIPV6ENA Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. 12 1 read-write TSIPV4ENA Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. 13 1 read-write TSEVTENA Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). 14 1 read-write TSMSTRENA Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. 15 1 read-write SNAPTYPSEL Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, decide the set of PTP packet types for which snapshot needs to be taken. 16 2 read-write TSENMACADDR Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. 18 1 read-write TXTTSSTSM Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. 24 1 read-write AV8021ASMEN AV 802. 28 1 read-write MAC_SUB_SCND_INCR Sub-second increment register 0xB04 32 read-write 0 0xFF0000 SSINC Sub-second increment value. 16 8 read-write MAC_SYS_TIME_SCND System time seconds register 0xB08 32 read-only 0 0xFFFFFFFF TSS Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 32 read-only MAC_SYS_TIME_NSCND System time nanoseconds register 0xB0C 32 read-only 0 0x7FFFFFFF TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0. 0 31 read-only MAC_SYS_TIME_SCND_UPD no description available 0xB10 32 read-write 0 0xFFFFFFFF TSS Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time. 0 32 read-write MAC_SYS_TIME_NSCND_UPD no description available 0xB14 32 read-write 0 0xFFFFFFFF TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0. 0 31 read-write ADDSUB Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. 31 1 read-write MAC_SYS_TIMESTMP_ADDEND Time stamp addend register 0xB18 32 read-write 0 0xFFFFFFFF TSAR Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write MAC_SYS_TIME_HWORD_SCND no description available 0xB1C 32 read-write 0 0xFFFF TSHWR Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. 0 16 read-write MAC_SYS_TIMESTMP_STAT Time stamp status register 0xB20 32 read-only 0 0x1 TSSOVF Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp has overflowed beyond 0xFFFF_FFFF. 0 1 read-only MAC_Tx_TIMESTAMP_STATUS_NANOSECONDS Tx timestamp status nanoseconds 0xB30 32 read-only 0 0xFFFFFFFF TXTSSTSLO Transmit timestamp status low. 0 31 read-only TXTSSTSMIS Transmit timestamp status missed. 31 1 read-only MAC_Tx_TIMESTAMP_STATUS_SECONDS Tx timestamp status seconds 0xB34 32 read-only 0 0xFFFFFFFF TXTSSTSHI Transmit timestamp status high. 0 32 read-only MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND Timestamp ingress correction 0xB58 32 read-write 0 0xFFFFFFFF TSIC Transmit ingress correction. 0 32 read-write MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND Timestamp egress correction 0xB5C 32 read-write 0 0xFFFFFFFF TSEC Transmit egress correction. 0 32 read-write MTL_OP_MODE MTL Operation Mode Register 0xC00 32 read-write 0 0x366 DTXSTS Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. 1 1 read-write RAA Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. 2 1 read-only SCHALG Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm. 5 2 read-write CNTPRST Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0. 8 1 read-write CNTCLR Counters Reset When this bit is set, all counters are reset. 9 1 read-write MTL_INTR_STAT MTL Interrupt Status register 0xC20 32 read-only 0 0x3 Q0IS Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. 0 1 read-only Q1IS Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. 1 1 read-only MTL_RXQ_DMA_MAP MTL Receive Queue and DMA Channel Mapping register 0xC30 32 read-write 0 0x1111 Q0MDMACH Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the Q0DDMACH field is reset. 0 1 read-write Q0DDMACH Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 4 1 read-write Q1MDMACH Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the Q1DDMACH field is reset. 8 1 read-write Q1DDMACH Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address. 12 1 read-write DMA_MODE DMA mode register 0x1000 32 read-write 0 0x781F SWR Software Reset When this bit is set, the MAC and the OMA controller reset the logic and all internal registers of the OMA, MTL, and MAC. 0 1 read-write DA DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR bit is set. 1 1 read-write TAA Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected. 2 3 read-write TXPR Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus. 11 1 read-write PR Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. 12 3 read-write DMA_SYSBUS_MODE DMA System Bus mode 0x1004 32 read-write 0 0xD001 FB Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers of specified length (INCRx or SINGLE). 0 1 read-write AAL Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned burst transfers on Read and Write channels. 12 1 read-write MB Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. 14 1 read-write RB Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLEtransfers. 15 1 read-write DMA_INTR_STAT DMA Interrupt status 0x1008 32 read-write 0 0x30003 DC0IS DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. 0 1 read-write DC1IS DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. 1 1 read-write MTLIS MTL Interrupt Status This bit indicates an interrupt event in the MTL. 16 1 read-only MACIS MAC Interrupt Status This bit indicates an interrupt event in the MAC. 17 1 read-only DMA_DBG_STAT DMA Debug Status 0x100C 32 read-write 0 0xFFFF01 AHSTS AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state. 0 1 read-write RPS0 DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer ) 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet data from the Rx buffer to the system memory) This field does not generate an interrupt. 8 4 read-only TPS0 DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer) 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field does not generate an interrupt. 12 4 read-only RPS1 DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. 16 4 read-only TPS1 DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. 20 4 read-only USBHSD LPC5460x USB1 High-speed Device Controller USBHSD 0x40094000 0 0x40 registers USB1 47 USB1_NEEDCLK 48 DEVCMDSTAT USB Device Command/Status register 0 32 read-write 0x800 0xF7DBFFFF DEV_ADDR USB device address. 0 7 read-write DEV_EN USB device enable. 7 1 read-write SETUP SETUP token received. 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on:. 9 1 read-write FORCE_VBUS If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled. 10 1 read-write LPM_SUP LPM Supported:. 11 1 read-write INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP:. 12 1 read-write INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP:. 13 1 read-write INTONNAK_CO Interrupt on NAK for control OUT EP:. 14 1 read-write INTONNAK_CI Interrupt on NAK for control IN EP:. 15 1 read-write DCON Device status - connect. 16 1 read-write DSUS Device status - suspend. 17 1 read-write LPM_SUS Device status - LPM Suspend. 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. 20 1 read-only Speed This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). 22 2 read-only DCON_C Device status - connect change. 24 1 read-write DSUS_C Device status - suspend change. 25 1 read-write DRES_C Device status - reset change. 26 1 read-write VBUS_DEBOUNCED This bit indicates if VBUS is detected or not. 28 1 read-only PHY_TEST_MODE This field is written by firmware to put the PHY into a test mode as defined by the USB2. 29 3 read-write INFO USB Info register 0x4 32 read-only 0x2000000 0xFFFF7FFF FRAME_NR Frame number. 0 11 read-only ERR_CODE The error code which last occurred:. 11 4 read-only Minrev Minor revision. 16 8 read-only Majrev Major revision. 24 8 read-only EPLISTSTART USB EP Command/Status List start address 0x8 32 read-write 0 0xFFFFFF00 EP_LIST_PRG Programmable portion of the USB EP Command/Status List address. 8 12 read-write EP_LIST_FIXED Fixed portion of USB EP Command/Status List address. 20 12 read-only DATABUFSTART USB Data buffer start address 0xC 32 read-write 0x41000000 0xFFFFFFFF DA_BUF Start address of the memory page where all endpoint data buffers are located. 0 32 read-write LPM USB Link Power Management register 0x10 32 read-write 0 0x1FF HIRD_HW Host Initiated Resume Duration - HW. 0 4 read-only HIRD_SW Host Initiated Resume Duration - SW. 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. 8 1 read-write EPSKIP USB Endpoint skip 0x14 32 read-write 0 0xFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. 0 12 read-write EPINUSE USB Endpoint Buffer in use 0x18 32 read-write 0 0xFFC BUF Buffer in use: This register has one bit per physical endpoint. 2 10 read-write EPBUFCFG USB Endpoint Buffer Configuration register 0x1C 32 read-write 0 0xFFC BUF_SB Buffer usage: This register has one bit per physical endpoint. 2 10 read-write INTSTAT USB interrupt status register 0x20 32 read-write 0 0xC0000FFF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. 0 1 read-write EP0IN Interrupt status register bit for the Control EP0 IN direction. 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. 9 1 read-write EP5OUT Interrupt status register bit for the EP5 OUT direction. 10 1 read-write EP5IN Interrupt status register bit for the EP5 IN direction. 11 1 read-write FRAME_INT Frame interrupt. 30 1 read-write DEV_INT Device status interrupt. 31 1 read-write INTEN USB interrupt enable register 0x24 32 read-write 0 0xC0000FFF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 0 12 read-write FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 31 1 read-write INTSETSTAT USB set interrupt status register 0x28 32 read-write 0 0xC0000FFF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 0 12 read-write FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 31 1 read-write EPTOGGLE USB Endpoint toggle register 0x34 32 read-write 0 0x3FFFFFFF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 0 30 read-write ULPIDEBUG UTMI/ULPI debug register 0x3C 32 read-write 0 0x83FFFFFF PHY_ADDR ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. 0 8 read-write PHY_WDATA UTMI+ mode: Reserved. 8 8 read-write PHY_RDATA UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+. 16 8 read-write PHY_RW UTMI+ mode: Reserved. 24 1 read-write PHY_ACCESS Software writes this bit to one to start a read or write operation. 25 1 read-write PHY_MODE This bit indicates if the interface between the controller is UTMI+ or ULPI. 31 1 read-write CRC_ENGINE LPC5411x CRC engine CRC 0x40095000 0 0xC registers MODE CRC mode 0 32 read-write 0 0x3F OrderedDict([('CRC_POLY', OrderedDict([('description', 'CRC polynomial'), ('bitOffset', 0), ('bitWidth', 2), ('CRC_32', [2, 'CRC-32 polynomial']), ('CRC_16', [1, 'CRC-16 polynomial']), ('CRC_CCITT', [0, 'CRC-CCITT polynomial'])])), ('BIT_RVS_DATA', OrderedDict([('description', 'Data bit order'), ('bitOffset', 2), ('bitWidth', 1), ('REVERSE', [1, 'Reverse data bits per byte']), ('NORMAL', [0, 'no reverse for data'])])), ('CMPL_DATA', OrderedDict([('description', 'Data complement'), ('bitOffset', 3), ('bitWidth', 1), ('COMPLEMENT', [1, "1's complement for data bits"]), ('NORMAL', [0, 'no complement for data bits'])])), ('BIT_RVS_SUM', OrderedDict([('description', 'Sum bit order'), ('bitOffset', 4), ('bitWidth', 1), ('REVERSE', [1, 'Reverse sum bits per byte']), ('NORMAL', [0, 'no reverse for sum'])])), ('CMPL_SUM', OrderedDict([('description', 'Sum complement'), ('bitOffset', 5), ('bitWidth', 1), ('COMPLEMENT', [1, "1's complement for sum bits"]), ('NORMAL', [0, 'no complement for sum bits'])]))]) CRC_POLY CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 0 2 read-write BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 2 1 read-write CMPL_WR Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 5 1 read-write SEED CRC seed 4 32 read-write 65535 0xFFFFFFFF OrderedDict([('CRC_SEED', OrderedDict([('description', 'A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1’s complement pre-processes.. Remark: A write access to this register will overrule the CRC calculation in progresses.'), ('bitOffset', 0), ('bitWidth', 32)]))]) CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. 0 32 read-write SUM The most recent CRC sum can be read through this register with selected bit order and 1’s complement post-processes. 8 32 read-only 65535 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 0 32 read-only DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1’s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. 8 32 write-only 0 0xFFFFFFFF CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. 0 32 write-only DATA8Data register - byte sizedDATA88write-only0DATA8Data register bits08 DATA16Data register - half-word sizedDATA816write-only0DATA16Data register bits016 DATA32Data register - word sizedDATA832write-only0DATA32Data register bits032 I2S0 LPC5411x I2S interface FLEXCOMM6 I2S I2S 0x40097000 0 0x1E00 registers FLEXCOMM6 20 3 0x20 SECCHANNEL[%s] no description available 0 PCFG1 Configuration register 1 for channel pair 0xC20 32 read-write 0 0x401 PAIRENABLE Enable for this channel pair.. 0 1 read-write ONECHANNEL Single channel mode. 10 1 read-write PCFG2 Configuration register 2 for channel pair 0xC24 32 read-write 0 0x1FF0000 POSITION Data Position. 16 9 read-write PSTAT Status register for channel pair 0xC28 32 read-write 0 0xF BUSY Busy status for this channel pair. 0 1 read-write SLVFRMERR Save Frame Error flag. 1 1 read-write LR Left/Right indication. 2 1 read-write DATAPAUSED Data Paused status flag. 3 1 read-only CFG1 Configuration register 1 for the primary channel pair. 0xC00 32 read-write 0 0x1F3FFF MAINENABLE Main enable for I 2S function in this Flexcomm 0 1 read-write DISABLED All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. 0 ENABLED This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. 0x1 DATAPAUSE Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. 1 1 read-write NORMAL Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. 0 PAUSE A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. 0x1 PAIRCOUNT Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. 2 2 read-write PAIRS_1 1 I2S channel pairs in this flexcomm 0 PAIRS_2 2 I2S channel pairs in this flexcomm 0x1 PAIRS_3 3 I2S channel pairs in this flexcomm 0x2 PAIRS_4 4 I2S channel pairs in this flexcomm 0x3 MSTSLVCFG Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. 4 2 read-write NORMAL_SLAVE_MODE Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. 0 WS_SYNC_MASTER WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. 0x1 MASTER_USING_SCK Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. 0x2 NORMAL_MASTER Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. 0x3 MODE Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. 6 2 read-write CLASSIC_MODE I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. 0 DSP_MODE_WS_50_DUTYCYCLE DSP mode where WS has a 50% duty cycle. See remark for mode 0. 0x1 DSP_MODE_WS_1_CLOCK DSP mode where WS has a one clock long pulse at the beginning of each data frame. 0x2 DSP_MODE_WS_1_DATA DSP mode where WS has a one data slot long pulse at the beginning of each data frame. 0x3 RIGHTLOW Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. 8 1 read-write RIGHT_HIGH The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. 0 RIGHT_LOW The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. 0x1 LEFTJUST Left Justify data. 9 1 read-write RIGHT_JUSTIFIED Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. 0 LEFT_JUSTIFIED Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. 0x1 ONECHANNEL Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. 10 1 read-write DUAL_CHANNEL I2S data for this channel pair is treated as left and right channels. 0 SINGLE_CHANNEL I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. 0x1 PDMDATA PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. 11 1 read-write NORMAL Normal operation, data is transferred to or from the Flexcomm FIFO. 0 DMIC_SUBSYSTEM The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. 0x1 SCK_POL SCK polarity. 12 1 read-write FALLING_EDGE Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). 0 RISING_EDGE Data is launched on SCK rising edges and sampled on SCK falling edges. 0x1 WS_POL WS polarity. 13 1 read-write NOT_INVERTED Data frames begin at a falling edge of WS (standard for classic I2S). 0 INVERTED WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). 0x1 DATALEN Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length 16 5 read-write CFG2 Configuration register 2 for the primary channel pair. 0xC04 32 read-write 0 0x1FF01FF FRAMELEN Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. 0 9 read-write POSITION Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. 16 9 read-write STAT Status register for the primary channel pair. 0xC08 32 read-write 0 0xD BUSY Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. 0 1 read-only IDLE The transmitter/receiver for channel pair is currently idle. 0 BUSY The transmitter/receiver for channel pair is currently processing data. 0x1 SLVFRMERR Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. 1 1 write-only NO_ERROR No error has been recorded. 0 ERROR An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. 0x1 LR Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. 2 1 read-only LEFT_CHANNEL Left channel. 0 RIGHT_CHANNEL Right channel. 0x1 DATAPAUSED Data Paused status flag. Applies to all I2S channels 3 1 read-only NOT_PAUSED Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. 0 PAUSED A data pause has been requested and is now in force. 0x1 DIV Clock divider, used by all channel pairs. 0xC1C 32 read-write 0 0xFFF DIV This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. 0 12 read-write FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 TXI2SE0 Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. 2 1 read-write LAST_VALUE If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. 0 ZERO If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. 0x1 PACK48 Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. 3 1 read-write BIT_24 48-bit I2S FIFO entries are handled as all 24-bit values. 0 BIT_32_16 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write POPDBG Pop FIFO for debug reads. 18 1 read-write DO_NOT_POP Debug reads of the FIFO do not pop the FIFO. 0 POP A debug read will cause the FIFO to pop. 0x1 FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 write-only 0 0 TXDATA Transmit data to the FIFO. The number of bits used depends on configuration details. 0 32 write-only FIFOWR48H FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE24 32 write-only 0 0 TXDATA Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0 RXDATA Received data from the FIFO. The number of bits used depends on configuration details. 0 32 read-only FIFORD48H FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE34 32 read-only 0 0xFFFFFF RXDATA Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0 RXDATA Received data from the FIFO. 0 32 read-only FIFORD48HNOPOP FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE44 32 read-only 0 0xFFFFFF RXDATA Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 read-only ID I2S Module identification 0x1DFC 32 read-only 0xE0900000 0xFFFFFFFF Aperture Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only Minor_Rev Minor revision of module implementation, starting at 0. 8 4 read-only Major_Rev Major revision of module implementation, starting at 0. 12 4 read-only ID Unique module identifier for this IP block. 16 16 read-only I2S1 LPC5411x I2S interface FLEXCOMM7 I2S 0x40098000 0 0x1E00 registers FLEXCOMM7 21 SDIF SDMMC SDIF 0x4009B000 0 0x300 registers SDIO 42 CTRL Control register 0 32 read-write 0 0x2070FD7 CONTROLLER_RESET Controller reset. 0 1 read-write FIFO_RESET Fifo reset. 1 1 read-write DMA_RESET DMA reset. 2 1 read-write INT_ENABLE Global interrupt enable/disable bit. 4 1 read-write READ_WAIT Read/wait. 6 1 read-write SEND_IRQ_RESPONSE Send irq response. 7 1 read-write ABORT_READ_DATA Abort read data. 8 1 read-write SEND_CCSD Send ccsd. 9 1 read-write SEND_AUTO_STOP_CCSD Send auto stop ccsd. 10 1 read-write CEATA_DEVICE_INTERRUPT_STATUS CEATA device interrupt status. 11 1 read-write CARD_VOLTAGE_A0 Controls the state of the SD_VOLT0 pin. 16 1 read-write CARD_VOLTAGE_A1 Controls the state of the SD_VOLT1 pin. 17 1 read-write CARD_VOLTAGE_A2 Controls the state of the SD_VOLT2 pin. 18 1 read-write USE_INTERNAL_DMAC SD/MMC DMA use. 25 1 read-write PWREN Power Enable register 0x4 32 read-write 0 0x1 POWER_ENABLE Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 1 read-write CLKDIV Clock Divider register 0x8 32 read-write 0 0xFF CLK_DIVIDER0 Clock divider-0 value. 0 8 read-write CLKENA Clock Enable register 0x10 32 read-write 0 0x10001 CCLK_ENABLE Clock-enable control for SD card clock. 0 1 read-write CCLK_LOW_POWER Low-power control for SD card clock. 16 1 read-write TMOUT Time-out register 0x14 32 read-write 0xFFFFFF40 0xFFFFFFFF RESPONSE_TIMEOUT Response time-out value. 0 8 read-write DATA_TIMEOUT Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. 8 24 read-write CTYPE Card Type register 0x18 32 read-write 0 0x10001 CARD_WIDTH0 Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0). 0 1 read-write CARD_WIDTH1 Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. 16 1 read-write BLKSIZ Block Size register 0x1C 32 read-write 0x200 0xFFFF BLOCK_SIZE Block size. 0 16 read-write BYTCNT Byte Count register 0x20 32 read-write 0x200 0xFFFFFFFF BYTE_COUNT Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. 0 32 read-write INTMASK Interrupt Mask register 0x24 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO Response time-out. 8 1 read-write DRTO Data read time-out. 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/Write no CRC. 15 1 read-write SDIO_INT_MASK Mask SDIO interrupt. 16 1 read-write CMDARG Command Argument register 0x28 32 read-write 0 0xFFFFFFFF CMD_ARG Value indicates command argument to be passed to card. 0 32 read-write CMD Command register 0x2C 32 read-write 0 0xBFE0FFFF CMD_INDEX Command index. 0 6 read-write RESPONSE_EXPECT Response expect. 6 1 read-write RESPONSE_LENGTH Response length. 7 1 read-write CHECK_RESPONSE_CRC Check response CRC. 8 1 read-write DATA_EXPECTED Data expected. 9 1 read-write READ_WRITE read/write. 10 1 read-write TRANSFER_MODE Transfer mode. 11 1 read-write SEND_AUTO_STOP Send auto stop. 12 1 read-write WAIT_PRVDATA_COMPLETE Wait prvdata complete. 13 1 read-write STOP_ABORT_CMD Stop abort command. 14 1 read-write SEND_INITIALIZATION Send initialization. 15 1 read-write UPDATE_CLOCK_REGISTERS_ONLY Update clock registers only. 21 1 read-write READ_CEATA_DEVICE Read ceata device. 22 1 read-write CCS_EXPECTED CCS expected. 23 1 read-write ENABLE_BOOT Enable Boot - this bit should be set only for mandatory boot mode. 24 1 read-write EXPECT_BOOT_ACK Expect Boot Acknowledge. 25 1 read-write DISABLE_BOOT Disable Boot. 26 1 read-write BOOT_MODE Boot Mode. 27 1 read-write VOLT_SWITCH Voltage switch bit. 28 1 read-write USE_HOLD_REG Use Hold Register. 29 1 read-write START_CMD Start command. 31 1 read-write 4 0x4 RESP[%s] Response register 0x30 32 read-write 0 0xFFFFFFFF RESPONSE Bits of response. 0 32 read-write MINTSTS Masked Interrupt Status register 0x40 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO Response time-out. 8 1 read-write DRTO Data read time-out. 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/write no CRC. 15 1 read-write SDIO_INTERRUPT Interrupt from SDIO card. 16 1 read-write RINTSTS Raw Interrupt Status register 0x44 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO_BAR Response time-out (RTO)/Boot Ack Received (BAR). 8 1 read-write DRTO_BDS Data read time-out (DRTO)/Boot Data Start (BDS). 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/write no CRC. 15 1 read-write SDIO_INTERRUPT Interrupt from SDIO card. 16 1 read-write STATUS Status register 0x48 32 read-write 0x406 0xFFFFFFFF FIFO_RX_WATERMARK FIFO reached Receive watermark level; not qualified with data transfer. 0 1 read-write FIFO_TX_WATERMARK FIFO reached Transmit watermark level; not qualified with data transfer. 1 1 read-write FIFO_EMPTY FIFO is empty status. 2 1 read-write FIFO_FULL FIFO is full status. 3 1 read-write CMDFSMSTATES Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. 4 4 read-write DATA_3_STATUS Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. 8 1 read-write DATA_BUSY Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. 9 1 read-write DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. 10 1 read-write RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. 11 6 read-write FIFO_COUNT FIFO count - Number of filled locations in FIFO. 17 13 read-write DMA_ACK DMA acknowledge signal state. 30 1 read-write DMA_REQ DMA request signal state. 31 1 read-write FIFOTH FIFO Threshold Watermark register 0x4C 32 read-write 0x1F0000 0x7FFF0FFF TX_WMARK FIFO threshold watermark level when transmitting data to card. 0 12 read-write RX_WMARK FIFO threshold watermark level when receiving data to card. 16 12 read-write DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. 28 3 read-write CDETECT Card Detect register 0x50 32 read-write 0 0x1 CARD_DETECT Card detect. 0 1 read-write WRTPRT Write Protect register 0x54 32 read-write 0 0x1 WRITE_PROTECT Write protect. 0 1 read-write TCBCNT Transferred CIU Card Byte Count register 0x5C 32 read-write 0 0xFFFFFFFF TRANS_CARD_BYTE_COUNT Number of bytes transferred by CIU unit to card. 0 32 read-write TBBCNT Transferred Host to BIU-FIFO Byte Count register 0x60 32 read-write 0 0xFFFFFFFF TRANS_FIFO_BYTE_COUNT Number of bytes transferred between Host/DMA memory and BIU FIFO. 0 32 read-write DEBNCE Debounce Count register 0x64 32 read-write 0xFFFFFF 0xFFFFFF DEBOUNCE_COUNT Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. 0 24 read-write RST_N Hardware Reset 0x78 32 read-write 0x1 0x1 CARD_RESET Hardware reset. 0 1 read-write BMOD Bus Mode register 0x80 32 read-write 0 0x7FF SWR Software Reset. 0 1 read-write FB Fixed Burst. 1 1 read-write DSL Descriptor Skip Length. 2 5 read-write DE SD/MMC DMA Enable. 7 1 read-write PBL Programmable Burst Length. 8 3 read-write PLDMND Poll Demand register 0x84 32 read-write 0 0xFFFFFFFF PD Poll Demand. 0 32 read-write DBADDR Descriptor List Base Address register 0x88 32 read-write 0 0xFFFFFFFF SDL Start of Descriptor List. 0 32 read-write IDSTS Internal DMAC Status register 0x8C 32 read-write 0 0x1FF37 TI Transmit Interrupt. 0 1 read-write RI Receive Interrupt. 1 1 read-write FBE Fatal Bus Error Interrupt. 2 1 read-write DU Descriptor Unavailable Interrupt. 4 1 read-write CES Card Error Summary. 5 1 read-write NIS Normal Interrupt Summary. 8 1 read-write AIS Abnormal Interrupt Summary. 9 1 read-write EB Error Bits. 10 3 read-write FSM DMAC state machine present state. 13 4 read-write IDINTEN Internal DMAC Interrupt Enable register 0x90 32 read-write 0 0x337 TI Transmit Interrupt Enable. 0 1 read-write RI Receive Interrupt Enable. 1 1 read-write FBE Fatal Bus Error Enable. 2 1 read-write DU Descriptor Unavailable Interrupt. 4 1 read-write CES Card Error summary Interrupt Enable. 5 1 read-write NIS Normal Interrupt Summary Enable. 8 1 read-write AIS Abnormal Interrupt Summary Enable. 9 1 read-write DSCADDR Current Host Descriptor Address register 0x94 32 read-write 0 0xFFFFFFFF HDA Host Descriptor Address Pointer. 0 32 read-write BUFADDR Current Buffer Descriptor Address register 0x98 32 read-write 0 0xFFFFFFFF HBA Host Buffer Address Pointer. 0 32 read-write CARDTHRCTL Card Threshold Control 0x100 32 read-write 0 0xFF0003 CARDRDTHREN Card Read Threshold Enable. 0 1 read-write BSYCLRINTEN Busy Clear Interrupt Enable. 1 1 read-write CARDTHRESHOLD Card Threshold size. 16 8 read-write BACKENDPWR Power control 0x104 32 read-write 0 0x1 BACKENDPWR Back-end Power control for card application. 0 1 read-write 64 0x4 FIFO[%s] SDIF FIFO 0x200 32 read-write 0 0xFFFFFFFF DATA SDIF FIFO. 0 32 read-write CAN0 LPC5460x Controller Area Network Flexible Data CAN CAN 0x4009D000 0 0x604 registers CAN0_IRQ0 43 CAN0_IRQ1 44 DBTP Data Bit Timing Prescaler Register 0xC 32 read-write 0xA33 0x9F1FFF DSJW Data (re)synchronization jump width. 0 4 read-write DTSEG2 Data time segment after sample point. 4 4 read-write DTSEG1 Data time segment before sample point. 8 5 read-write DBRP Data bit rate prescaler. 16 5 read-write TDC Transmitter delay compensation. 23 1 read-write TEST Test Register 0x10 32 read-write 0 0xF0 LBCK Loop back mode. 4 1 read-write TX Control of transmit pin. 5 2 read-write RX Monitors the actual value of the CAN_RXD. 7 1 read-write CCCR CC Control Register 0x18 32 read-write 0x1 0xF3FF INIT Initialization. 0 1 read-write CCE Configuration change enable. 1 1 read-write ASM Restricted operational mode. 2 1 read-write CSA Clock Stop Acknowledge. 3 1 read-write CSR Clock Stop Request. 4 1 read-write MON Bus monitoring mode. 5 1 read-write DAR Disable automatic retransmission. 6 1 read-write TEST Test mode enable. 7 1 read-write FDOE CAN FD operation enable. 8 1 read-write BRSE When CAN FD operation is disabled, this bit is not evaluated. 9 1 read-write PXHD Protocol exception handling disable. 12 1 read-write EFBI Edge filtering during bus integration. 13 1 read-write TXP Transmit pause. 14 1 read-write NISO Non ISO operation. 15 1 read-write NBTP Nominal Bit Timing and Prescaler Register 0x1C 32 read-write 0x6000A03 0xFFFFFF7F NTSEG2 Nominal time segment after sample point. 0 7 read-write NTSEG1 Nominal time segment before sample point. 8 8 read-write NBRP Nominal bit rate prescaler. 16 9 read-write NSJW Nominal (re)synchronization jump width. 25 7 read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0 0xF0003 TSS Timestamp select. 0 2 read-write TCP Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. 16 4 read-write TSCV Timestamp Counter Value 0x24 32 read-write 0 0xFFFF TSC Timestamp counter. 0 16 read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0xFFFF0000 0xFFFF0007 ETOC Enable timeout counter. 0 1 read-write TOS Timeout select. 1 2 read-write TOP Timeout period. 16 16 read-write TOCV Timeout Counter Value 0x2C 32 read-only 0xFFFF 0xFFFF TOC Timeout counter. 0 16 read-only ECR Error Counter Register 0x40 32 read-only 0 0xFFFFFF TEC Transmit error counter. 0 8 read-only REC Receive error counter. 8 7 read-only RP Receive error passive. 15 1 read-only CEL CAN error logging. 16 8 read-only PSR Protocol Status Register 0x44 32 read-only 0x707 0x7F7FFF LEC Last error code. 0 3 read-only ACT Activity. 3 2 read-only EP Error Passive. 5 1 read-only EW Warning status. 6 1 read-only BO Bus Off Status. 7 1 read-only DLEC Data phase last error code. 8 3 read-only RESI ESI flag of the last received CAN FD message. 11 1 read-only RBRS BRS flag of last received CAN FD message. 12 1 read-only RFDF Received a CAN FD message. 13 1 read-only PXE Protocol exception event. 14 1 read-only TDCV Transmitter delay compensation value. 16 7 read-only TDCR Transmitter Delay Compensator Register 0x48 32 read-write 0 0x7F7F TDCF Transmitter delay compensation filter window length. 0 7 read-write TDCO Transmitter delay compensation offset. 8 7 read-write IR Interrupt Register 0x50 32 read-write 0 0x3FFFFFFF RF0N Rx FIFO 0 new message. 0 1 read-write RF0W Rx FIFO 0 watermark reached. 1 1 read-write RF0F Rx FIFO 0 full. 2 1 read-write RF0L Rx FIFO 0 message lost. 3 1 read-write RF1N Rx FIFO 1 new message. 4 1 read-write RF1W Rx FIFO 1 watermark reached. 5 1 read-write RF1F Rx FIFO 1 full. 6 1 read-write RF1L Rx FIFO 1 message lost. 7 1 read-write HPM High priority message. 8 1 read-write TC Transmission completed. 9 1 read-write TCF Transmission cancellation finished. 10 1 read-write TFE Tx FIFO empty. 11 1 read-write TEFN Tx event FIFO new entry. 12 1 read-write TEFW Tx event FIFO watermark reached. 13 1 read-write TEFF Tx event FIFO full. 14 1 read-write TEFL Tx event FIFO element lost. 15 1 read-write TSW Timestamp wraparound. 16 1 read-write MRAF Message RAM access failure. 17 1 read-write TOO Timeout occurred. 18 1 read-write DRX Message stored in dedicated Rx buffer. 19 1 read-write BEC Bit error corrected. 20 1 read-write BEU Bit error uncorrected. 21 1 read-write ELO Error logging overflow. 22 1 read-write EP Error passive. 23 1 read-write EW Warning status. 24 1 read-write BO Bus_Off Status. 25 1 read-write WDI Watchdog interrupt. 26 1 read-write PEA Protocol error in arbitration phase. 27 1 read-write PED Protocol error in data phase. 28 1 read-write ARA Access to reserved address. 29 1 read-write IE Interrupt Enable 0x54 32 read-write 0 0x3FFFFFFF RF0NE Rx FIFO 0 new message interrupt enable. 0 1 read-write RF0WE Rx FIFO 0 watermark reached interrupt enable. 1 1 read-write RF0FE Rx FIFO 0 full interrupt enable. 2 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable. 3 1 read-write RF1NE Rx FIFO 1 new message interrupt enable. 4 1 read-write RF1WE Rx FIFO 1 watermark reached interrupt enable. 5 1 read-write RF1FE Rx FIFO 1 full interrupt enable. 6 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable. 7 1 read-write HPME High priority message interrupt enable. 8 1 read-write TCE Transmission completed interrupt enable. 9 1 read-write TCFE Transmission cancellation finished interrupt enable. 10 1 read-write TFEE Tx FIFO empty interrupt enable. 11 1 read-write TEFNE Tx event FIFO new entry interrupt enable. 12 1 read-write TEFWE Tx event FIFO watermark reached interrupt enable. 13 1 read-write TEFFE Tx event FIFO full interrupt enable. 14 1 read-write TEFLE Tx event FIFO element lost interrupt enable. 15 1 read-write TSWE Timestamp wraparound interrupt enable. 16 1 read-write MRAFE Message RAM access failure interrupt enable. 17 1 read-write TOOE Timeout occurred interrupt enable. 18 1 read-write DRXE Message stored in dedicated Rx buffer interrupt enable. 19 1 read-write BECE Bit error corrected interrupt enable. 20 1 read-write BEUE Bit error uncorrected interrupt enable. 21 1 read-write ELOE Error logging overflow interrupt enable. 22 1 read-write EPE Error passive interrupt enable. 23 1 read-write EWE Warning status interrupt enable. 24 1 read-write BOE Bus_Off Status interrupt enable. 25 1 read-write WDIE Watchdog interrupt enable. 26 1 read-write PEAE Protocol error in arbitration phase interrupt enable. 27 1 read-write PEDE Protocol error in data phase interrupt enable. 28 1 read-write ARAE Access to reserved address interrupt enable. 29 1 read-write ILS Interrupt Line Select 0x58 32 read-write 0 0x3FFFFFFF RF0NL Rx FIFO 0 new message interrupt line. 0 1 read-write RF0WL Rx FIFO 0 watermark reached interrupt line. 1 1 read-write RF0FL Rx FIFO 0 full interrupt line. 2 1 read-write RF0LL Rx FIFO 0 message lost interrupt line. 3 1 read-write RF1NL Rx FIFO 1 new message interrupt line. 4 1 read-write RF1WL Rx FIFO 1 watermark reached interrupt line. 5 1 read-write RF1FL Rx FIFO 1 full interrupt line. 6 1 read-write RF1LL Rx FIFO 1 message lost interrupt line. 7 1 read-write HPML High priority message interrupt line. 8 1 read-write TCL Transmission completed interrupt line. 9 1 read-write TCFL Transmission cancellation finished interrupt line. 10 1 read-write TFEL Tx FIFO empty interrupt line. 11 1 read-write TEFNL Tx event FIFO new entry interrupt line. 12 1 read-write TEFWL Tx event FIFO watermark reached interrupt line. 13 1 read-write TEFFL Tx event FIFO full interrupt line. 14 1 read-write TEFLL Tx event FIFO element lost interrupt line. 15 1 read-write TSWL Timestamp wraparound interrupt line. 16 1 read-write MRAFL Message RAM access failure interrupt line. 17 1 read-write TOOL Timeout occurred interrupt line. 18 1 read-write DRXL Message stored in dedicated Rx buffer interrupt line. 19 1 read-write BECL Bit error corrected interrupt line. 20 1 read-write BEUL Bit error uncorrected interrupt line. 21 1 read-write ELOL Error logging overflow interrupt line. 22 1 read-write EPL Error passive interrupt line. 23 1 read-write EWL Warning status interrupt line. 24 1 read-write BOL Bus_Off Status interrupt line. 25 1 read-write WDIL Watchdog interrupt line. 26 1 read-write PEAL Protocol error in arbitration phase interrupt line. 27 1 read-write PEDL Protocol error in data phase interrupt line. 28 1 read-write ARAL Access to reserved address interrupt line. 29 1 read-write ILE Interrupt Line Enable 0x5C 32 read-write 0 0x3 EINT0 Enable interrupt line 0. 0 1 read-write EINT1 Enable interrupt line 1. 1 1 read-write GFC Global Filter Configuration 0x80 32 read-write 0 0x3F RRFE Reject remote frames extended. 0 1 read-write RRFS Reject remote frames standard. 1 1 read-write ANFE Accept non-matching frames extended. 2 2 read-write ANFS Accept non-matching frames standard. 4 2 read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0 0xFFFFFC FLSSA Filter list standard start address. 2 14 read-write LSS List size standard 0 = No standard message ID filter. 16 8 read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0 0xFFFFFC FLESA Filter list extended start address. 2 14 read-write LSE List size extended 0 = No extended message ID filter. 16 8 read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID mask. 0 29 read-write HPMS High Priority Message Status 0x94 32 read-only 0 0xFFFF BIDX Buffer index. 0 6 read-only MSI Message storage indicator. 6 2 read-only FIDX Filter index. 8 7 read-only FLST Filter list. 15 1 read-only NDAT1 New Data 1 0x98 32 read-write 0 0xFFFFFFFF ND New Data. 0 32 read-write NDAT2 New Data 2 0x9C 32 read-write 0 0xFFFFFFFF ND New Data. 0 32 read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0 0xFF7FFFFC F0SA Rx FIFO 0 start address. 2 14 read-write F0S Rx FIFO 0 size. 16 7 read-write F0WM Rx FIFO 0 watermark 0 = Watermark interrupt disabled. 24 7 read-write F0OM FIFO 0 operation mode. 31 1 read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-write 0 0x33F3F7F F0FL Rx FIFO 0 fill level. 0 7 read-write F0GI Rx FIFO 0 get index. 8 6 read-write F0PI Rx FIFO 0 put index. 16 6 read-write F0F Rx FIFO 0 full. 24 1 read-write RF0L Rx FIFO 0 message lost. 25 1 read-write RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0 0x3F F0AI Rx FIFO 0 acknowledge index. 0 6 read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0 0xFFFC RBSA Rx buffer start address. 2 14 read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0 0xFF7FFFFC F1SA Rx FIFO 1 start address. 2 14 read-write F1S Rx FIFO 1 size 0 = No Rx FIFO 1. 16 7 read-write F1WM Rx FIFO 1 watermark 0 = Watermark interrupt disabled. 24 7 read-write F1OM FIFO 1 operation mode. 31 1 read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0 0x33F3F7F F1FL Rx FIFO 1 fill level. 0 7 read-only F1GI Rx FIFO 1 get index. 8 6 read-only F1PI Rx FIFO 1 put index. 16 6 read-only F1F Rx FIFO 1 full. 24 1 read-only RF1L Rx FIFO 1 message lost. 25 1 read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0 0x3F F1AI Rx FIFO 1 acknowledge index. 0 6 read-write RXESC Rx Buffer and FIFO Element Size Configuration 0xBC 32 read-write 0 0x777 F0DS Rx FIFO 0 data field size. 0 3 read-write F1DS Rx FIFO 1 data field size. 4 3 read-write RBDS . 8 3 read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0 0x7F3FFFFC TBSA Tx buffers start address. 2 14 read-write NDTB Number of dedicated transmit buffers 0 = No dedicated Tx buffers. 16 6 read-write TFQS Transmit FIFO/queue size 0 = No tx FIFO/Queue. 24 6 read-write TFQM Tx FIFO/queue mode. 30 1 read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-write 0 0x3F1F3F TFGI Tx FIFO get index. 8 5 read-write TFQPI Tx FIFO/queue put index. 16 5 read-write TFQF Tx FIFO/queue full. 21 1 read-write TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write 0 0x7 TBDS Tx buffer data field size. 0 3 read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-write 0 0xFFFFFFFF TRP Transmission request pending. 0 32 read-write TXBAR Tx Buffer Add Request 0xD0 32 read-write 0 0xFFFFFFFF AR Add request. 0 32 read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write 0 0xFFFFFFFF CR Cancellation request. 0 32 read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-write 0 0xFFFFFFFF TO Transmission occurred. 0 32 read-write TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-write 0 0xFFFFFFFF TO Cancellation finished. 0 32 read-write TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0 0xFFFFFFFF TIE Transmission interrupt enable. 0 32 read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0 0xFFFFFFFF CFIE Cancellation finished interrupt enable. 0 32 read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0 0x3F3FFFFC EFSA Event FIFO start address. 2 14 read-write EFS Event FIFO size 0 = Tx event FIFO disabled. 16 6 read-write EFWM Event FIFO watermark 0 = Watermark interrupt disabled. 24 6 read-write TXEFS Tx Event FIFO Status 0xF4 32 read-only 0 0x33F1F3F EFFL Event FIFO fill level. 0 6 read-only EFGI Event FIFO get index. 8 5 read-only EFPI Event FIFO put index. 16 6 read-only EFF Event FIFO full. 24 1 read-only TEFL Tx event FIFO element lost. 25 1 read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0 0x1F EFAI Event FIFO acknowledge index. 0 5 read-write MRBA CAN Message RAM Base Address 0x200 32 read-write 0 0xFFFFFFFF BA Base address for the message RAM in the chip memory map. 16 16 read-write ETSCC External Timestamp Counter Configuration 0x400 32 read-write 0 0x800007FF ETCP External timestamp prescaler value. 0 11 read-write ETCE External timestamp counter enable. 31 1 read-write ETSCV External Timestamp Counter Value 0x600 32 read-write 0 0xFFFF ETSC External timestamp counter. 0 16 read-write CAN1 LPC5460x Controller Area Network Flexible Data CAN 0x4009E000 0 0x604 registers CAN1_IRQ0 45 CAN1_IRQ1 46 ADC0 LPC5411x 12-bit ADC controller (ADC) ADC 0x400A0000 0 0x74 registers ADC0_SEQA 22 ADC0_SEQB 23 ADC0_THCMP 24 CTRL ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. 0 32 read-write 0x600 0x7FFF CLKDIV In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode. 0 8 read-write ASYNMODE Select clock mode. 8 1 read-write SYNCHRONOUS_MODE Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse. 0 ASYNCHRONOUS_MODE Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. 0x1 RESOL The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution 9 2 read-write RESOLUTION_6_BIT 6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. 0 RESOLUTION_8_BIT 8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. 0x1 RESOLUTION_10_BIT 10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. 0x2 RESOLUTION_12_BIT 12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. 0x3 BYPASSCAL Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application. 11 1 read-write CALIBRATE Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. 0 BYPASS_CALIBRATION Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. 0x1 TSAMP Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. See Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks. 12 3 read-write INSEL Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. 0x4 32 read-write 0 0x3 SEL Selects the input source for channel 0. All other values are reserved. 0 2 read-write ADC0_IN0 ADC0_IN0 function. 0 TEMPERATURE_SENSOR Internal temperature sensor. 0x3 2 0x4 A,B SEQ_CTRL%s ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. 0x8 32 read-write 0 0xFC0FFFFF CHANNELS Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write. 0 12 read-write TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 12 6 read-write TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 18 1 read-write NEGATIVE_EDGE Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 0 POSITIVE_EDGE Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 0x1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. 19 1 read-write ENABLE_TRIGGER_SYNCH Enable trigger synchronization. The hardware trigger bypass is not enabled. 0 BYPASS_TRIGGER_SYNCH Bypass trigger synchronization. The hardware trigger bypass is enabled. 0x1 START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero. 26 1 read-write BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 27 1 read-write SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. 28 1 read-write LOWPRIO Set priority for sequence A. 29 1 read-write LOW_PRIORITY Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 0 HIGH_PRIORITY High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. 0x1 MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. 30 1 read-write END_OF_CONVERSION End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled. 0 END_OF_SEQUENCE End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. 0x1 SEQ_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. 31 1 read-write DISABLED Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 0 ENABLED Enabled. Sequence n is enabled. 0x1 2 0x4 A,B SEQ_GDAT%s ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. 0x10 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. 4 12 read-only THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). 16 2 read-only THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 18 2 read-only CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). 26 4 read-only OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). 30 1 read-only DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). 31 1 read-only 12 0x4 DAT[%s] ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. 0x20 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only THR0_LOW ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x50 32 read-write 0 0xFFF0 THRLOW Low threshold value against which ADC results will be compared 4 12 read-write THR1_LOW ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x54 32 read-write 0 0xFFF0 THRLOW Low threshold value against which ADC results will be compared 4 12 read-write THR0_HIGH ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x58 32 read-write 0 0xFFF0 THRHIGH High threshold value against which ADC results will be compared 4 12 read-write THR1_HIGH ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x5C 32 read-write 0 0xFFF0 THRHIGH High threshold value against which ADC results will be compared 4 12 read-write CHAN_THRSEL ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel 0x60 32 read-write 0 0xFFF CH0_THRSEL Threshold select for channel 0. 0 1 read-write THRESHOLD0 Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 0 THRESHOLD1 Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. 0x1 CH1_THRSEL Threshold select for channel 1. See description for channel 0. 1 1 read-write CH2_THRSEL Threshold select for channel 2. See description for channel 0. 2 1 read-write CH3_THRSEL Threshold select for channel 3. See description for channel 0. 3 1 read-write CH4_THRSEL Threshold select for channel 4. See description for channel 0. 4 1 read-write CH5_THRSEL Threshold select for channel 5. See description for channel 0. 5 1 read-write CH6_THRSEL Threshold select for channel 6. See description for channel 0. 6 1 read-write CH7_THRSEL Threshold select for channel 7. See description for channel 0. 7 1 read-write CH8_THRSEL Threshold select for channel 8. See description for channel 0. 8 1 read-write CH9_THRSEL Threshold select for channel 9. See description for channel 0. 9 1 read-write CH10_THRSEL Threshold select for channel 10. See description for channel 0. 10 1 read-write CH11_THRSEL Threshold select for channel 11. See description for channel 0. 11 1 read-write INTEN ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. 0x64 32 read-write 0 0x7FFFFFF SEQA_INTEN Sequence A interrupt enable. 0 1 read-write DISABLED Disabled. The sequence A interrupt/DMA trigger is disabled. 0 ENABLED Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. 0x1 SEQB_INTEN Sequence B interrupt enable. 1 1 read-write DISABLED Disabled. The sequence B interrupt/DMA trigger is disabled. 0 ENABLED Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. 0x1 OVR_INTEN Overrun interrupt enable. 2 1 read-write DISABLED Disabled. The overrun interrupt is disabled. 0 ENABLED Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted. 0x1 ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. 3 2 read-write DISABLED Disabled. 0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 ADCMPINTEN1 Channel 1 threshold comparison interrupt enable. See description for channel 0. 5 2 read-write ADCMPINTEN2 Channel 2 threshold comparison interrupt enable. See description for channel 0. 7 2 read-write ADCMPINTEN3 Channel 3 threshold comparison interrupt enable. See description for channel 0. 9 2 read-write ADCMPINTEN4 Channel 4 threshold comparison interrupt enable. See description for channel 0. 11 2 read-write ADCMPINTEN5 Channel 5 threshold comparison interrupt enable. See description for channel 0. 13 2 read-write ADCMPINTEN6 Channel 6 threshold comparison interrupt enable. See description for channel 0. 15 2 read-write ADCMPINTEN7 Channel 7 threshold comparison interrupt enable. See description for channel 0. 17 2 read-write ADCMPINTEN8 Channel 8 threshold comparison interrupt enable. See description for channel 0. 19 2 read-write ADCMPINTEN9 Channel 9 threshold comparison interrupt enable. See description for channel 0. 21 2 read-write ADCMPINTEN10 Channel 10 threshold comparison interrupt enable. See description for channel 0. 23 2 read-write ADCMPINTEN11 Channel 21 threshold comparison interrupt enable. See description for channel 0. 25 2 read-write FLAGS ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). 0x68 32 read-write 0 0xF3FFFFFF THCMP0 Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. 0 1 read-write THCMP1 Threshold comparison event on Channel 1. See description for channel 0. 1 1 read-write THCMP2 Threshold comparison event on Channel 2. See description for channel 0. 2 1 read-write THCMP3 Threshold comparison event on Channel 3. See description for channel 0. 3 1 read-write THCMP4 Threshold comparison event on Channel 4. See description for channel 0. 4 1 read-write THCMP5 Threshold comparison event on Channel 5. See description for channel 0. 5 1 read-write THCMP6 Threshold comparison event on Channel 6. See description for channel 0. 6 1 read-write THCMP7 Threshold comparison event on Channel 7. See description for channel 0. 7 1 read-write THCMP8 Threshold comparison event on Channel 8. See description for channel 0. 8 1 read-write THCMP9 Threshold comparison event on Channel 9. See description for channel 0. 9 1 read-write THCMP10 Threshold comparison event on Channel 10. See description for channel 0. 10 1 read-write THCMP11 Threshold comparison event on Channel 11. See description for channel 0. 11 1 read-write OVERRUN0 Mirrors the OVERRRUN status flag from the result register for ADC channel 0 12 1 read-only OVERRUN1 Mirrors the OVERRRUN status flag from the result register for ADC channel 1 13 1 read-only OVERRUN2 Mirrors the OVERRRUN status flag from the result register for ADC channel 2 14 1 read-only OVERRUN3 Mirrors the OVERRRUN status flag from the result register for ADC channel 3 15 1 read-only OVERRUN4 Mirrors the OVERRRUN status flag from the result register for ADC channel 4 16 1 read-only OVERRUN5 Mirrors the OVERRRUN status flag from the result register for ADC channel 5 17 1 read-only OVERRUN6 Mirrors the OVERRRUN status flag from the result register for ADC channel 6 18 1 read-only OVERRUN7 Mirrors the OVERRRUN status flag from the result register for ADC channel 7 19 1 read-only OVERRUN8 Mirrors the OVERRRUN status flag from the result register for ADC channel 8 20 1 read-only OVERRUN9 Mirrors the OVERRRUN status flag from the result register for ADC channel 9 21 1 read-only OVERRUN10 Mirrors the OVERRRUN status flag from the result register for ADC channel 10 22 1 read-only OVERRUN11 Mirrors the OVERRRUN status flag from the result register for ADC channel 11 23 1 read-only SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register 24 1 read-only SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register 25 1 read-only SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. 28 1 read-only SEQB_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. 29 1 read-only THCMP_INT Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits. 30 1 read-only OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. 31 1 read-only STARTUP ADC Startup register. 0x6C 32 read-write 0 0x3 ADC_ENA ADC Enable bit. This bit can only be set to a 1 by software. It is cleared automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds after the ADC is powered up (typically by altering a system-level ADC power control bit). 0 1 read-write ADC_INIT ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is required if a calibration is not performed. It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required. It should not be set during the same write that sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically when the 'dummy' conversion cycle completes. 1 1 read-write CALIB ADC Calibration register. 0x70 32 read-write 0x2 0x1FF CALIB Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can only be set to a '1' by software. It is cleared automatically when the calibration cycle completes. 0 1 read-write CALREQD Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration. 1 1 read-write CALVALUE Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user. 2 7 read-write USBFSH LPC5460x USB0 Full-speed Host controller USBFSH 0x400A2000 0 0x60 registers USB0_NEEDCLK 27 USB0 28 HCREVISION BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) 0 32 read-only 0x10 0xFF REV Revision. 0 8 read-only HCCONTROL Defines the operating modes of the HC 0x4 32 read-write 0 0x7FF CBSR ControlBulkServiceRatio. 0 2 read-write PLE PeriodicListEnable. 2 1 read-write IE IsochronousEnable. 3 1 read-write CLE ControlListEnable. 4 1 read-write BLE BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. 5 1 read-write HCFS HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. 6 2 read-write IR InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. 8 1 read-write RWC RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. 9 1 read-write RWE RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. 10 1 read-write HCCOMMANDSTATUS This register is used to receive the commands from the Host Controller Driver (HCD) 0x8 32 read-write 0 0xCF HCR HostControllerReset This bit is set by HCD to initiate a software reset of HC. 0 1 read-write CLF ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. 1 1 read-write BLF BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. 2 1 read-write OCR OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. 3 1 read-write SOC SchedulingOverrunCount These bits are incremented on each scheduling overrun error. 6 2 read-write HCINTERRUPTSTATUS Indicates the status on various events that cause hardware interrupts by setting the appropriate bits 0xC 32 read-write 0 0xFFFFFC7F SO SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. 0 1 read-write WDH WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. 1 1 read-write SF StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. 2 1 read-write RD ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. 3 1 read-write UE UnrecoverableError This bit is set when HC detects a system error not related to USB. 4 1 read-write FNO FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. 5 1 read-write RHSC RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. 6 1 read-write OC OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. 10 22 read-write HCINTERRUPTENABLE Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt 0x10 32 read-write 0 0xC000007F SO Scheduling Overrun interrupt. 0 1 read-write WDH HcDoneHead Writeback interrupt. 1 1 read-write SF Start of Frame interrupt. 2 1 read-write RD Resume Detect interrupt. 3 1 read-write UE Unrecoverable Error interrupt. 4 1 read-write FNO Frame Number Overflow interrupt. 5 1 read-write RHSC Root Hub Status Change interrupt. 6 1 read-write OC Ownership Change interrupt. 30 1 read-write MIE Master Interrupt Enable. 31 1 read-write HCINTERRUPTDISABLE The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt 0x14 32 read-write 0 0xC000007F SO Scheduling Overrun interrupt. 0 1 read-write WDH HcDoneHead Writeback interrupt. 1 1 read-write SF Start of Frame interrupt. 2 1 read-write RD Resume Detect interrupt. 3 1 read-write UE Unrecoverable Error interrupt. 4 1 read-write FNO Frame Number Overflow interrupt. 5 1 read-write RHSC Root Hub Status Change interrupt. 6 1 read-write OC Ownership Change interrupt. 30 1 read-write MIE A 0 written to this field is ignored by HC. 31 1 read-write HCHCCA Contains the physical address of the host controller communication area 0x18 32 read-write 0 0xFFFFFF00 HCCA Base address of the Host Controller Communication Area. 8 24 read-write HCPERIODCURRENTED Contains the physical address of the current isochronous or interrupt endpoint descriptor 0x1C 32 read-write 0 0xFFFFFFF0 PCED The content of this register is updated by HC after a periodic ED is processed. 4 28 read-write HCCONTROLHEADED Contains the physical address of the first endpoint descriptor of the control list 0x20 32 read-write 0 0xFFFFFFF0 CHED HC traverses the Control list starting with the HcControlHeadED pointer. 4 28 read-write HCCONTROLCURRENTED Contains the physical address of the current endpoint descriptor of the control list 0x24 32 read-write 0 0xFFFFFFF0 CCED ControlCurrentED. 4 28 read-write HCBULKHEADED Contains the physical address of the first endpoint descriptor of the bulk list 0x28 32 read-write 0 0xFFFFFFF0 BHED BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. 4 28 read-write HCBULKCURRENTED Contains the physical address of the current endpoint descriptor of the bulk list 0x2C 32 read-write 0 0xFFFFFFF0 BCED BulkCurrentED This is advanced to the next ED after the HC has served the current one. 4 28 read-write HCDONEHEAD Contains the physical address of the last transfer descriptor added to the 'Done' queue 0x30 32 read-write 0 0xFFFFFFF0 DH DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. 4 28 read-write HCFMINTERVAL Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun 0x34 32 read-write 0x2EDF 0xFFFF3FFF FI FrameInterval This specifies the interval between two consecutive SOFs in bit times. 0 14 read-write FSMPS FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. 16 15 read-write FIT FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. 31 1 read-write HCFMREMAINING A 14-bit counter showing the bit time remaining in the current frame 0x38 32 read-write 0 0x80003FFF FR FrameRemaining This counter is decremented at each bit time. 0 14 read-write FRT FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. 31 1 read-write HCFMNUMBER Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD 0x3C 32 read-write 0 0xFFFF FN FrameNumber This is incremented when HcFmRemaining is re-loaded. 0 16 read-write HCPERIODICSTART Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list 0x40 32 read-write 0 0x3FFF PS PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. 0 14 read-write HCLSTHRESHOLD Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF 0x44 32 read-write 0x628 0xFFF LST LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. 0 12 read-write HCRHDESCRIPTORA First of the two registers which describes the characteristics of the root hub 0x48 32 read-write 0xFF000902 0xFF001FFF NDP NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. 0 8 read-write PSM PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. 8 1 read-write NPS NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. 9 1 read-write DT DeviceType This bit specifies that the root hub is not a compound device. 10 1 read-write OCPM OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. 11 1 read-write NOCP NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. 12 1 read-write POTPGT PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. 24 8 read-write HCRHDESCRIPTORB Second of the two registers which describes the characteristics of the Root Hub 0x4C 32 read-write 0 0x3FFFFFFF DR DeviceRemovable Each bit is dedicated to a port of the Root Hub. 0 16 read-write PPCM PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. 16 16 read-write HCRHSTATUS This register is divided into two parts 0x50 32 read-write 0 0x80038003 LPS (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. 0 1 read-write OCI OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. 1 1 read-write DRWE (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. 15 1 read-write LPSC (read) LocalPowerStatusChange The root hub does not support the local power status feature. 16 1 read-write OCIC OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. 17 1 read-write CRWE (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. 31 1 read-write HCRHPORTSTATUS Controls and reports the port events on a per-port basis 0x54 32 read-write 0 0x1F031F CCS (read) CurrentConnectStatus This bit reflects the current state of the downstream port. 0 1 read-write PES (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. 1 1 read-write PSS (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. 2 1 read-write POCI (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. 3 1 read-write PRS (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. 4 1 read-write PPS (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. 8 1 read-write LSDA (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. 9 1 read-write CSC ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. 16 1 read-write PESC PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. 17 1 read-write PSSC PortSuspendStatusChange This bit is set when the full resume sequence is completed. 18 1 read-write OCIC PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. 19 1 read-write PRSC PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. 20 1 read-write PORTMODE Controls the port if it is attached to the host block or the device block 0x5C 32 read-write 0 0x10101 ID Port ID pin value. 0 1 read-write ID_EN Port ID pin pull-up enable. 8 1 read-write DEV_ENABLE 1: device 0: host. 16 1 read-write USBHSH LPC5460x USB1 High-speed Host Controller USBHSH 0x400A3000 0 0x54 registers USB1 47 USB1_NEEDCLK 48 CAPLENGTH_CHIPID This register contains the offset value towards the start of the operational register space and the version number of the IP block 0 32 read-only 0x1010010 0xFFFF00FF CAPLENGTH Capability Length: This is used as an offset. 0 8 read-only CHIPID Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. 16 16 read-only HCSPARAMS Host Controller Structural Parameters 0x4 32 read-only 0x10011 0x1001F N_PORTS This register specifies the number of physical downstream ports implemented on this host controller. 0 4 read-only PPC This field indicates whether the host controller implementation includes port power control. 4 1 read-only P_INDICATOR This bit indicates whether the ports support port indicator control. 16 1 read-only HCCPARAMS Host Controller Capability Parameters 0x8 32 read-only 0x20006 0xFFFFFFFF LPMC Link Power Management Capability. 17 1 read-only FLADJ_FRINDEX Frame Length Adjustment 0xC 32 read-write 0x20 0x3FFF003F FLADJ Frame Length Timing Value. 0 6 read-write FRINDEX Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. 16 14 read-write ATL_PTD_BASE_ADDR Memory base address where ATL PTD0 is stored 0x10 32 read-write 0 0xFFFFFFF0 ATL_CUR This indicates the current PTD that is used by the hardware when it is processing the ATL list. 4 5 read-write ATL_BASE Base address to be used by the hardware to find the start of the ATL list. 9 23 read-write ISO_PTD_BASE_ADDR Memory base address where ISO PTD0 is stored 0x14 32 read-write 0 0xFFFFFFE0 ISO_FIRST This indicates the first PTD that is used by the hardware when it is processing the ISO list. 5 5 read-write ISO_BASE Base address to be used by the hardware to find the start of the ISO list. 10 22 read-write INT_PTD_BASE_ADDR Memory base address where INT PTD0 is stored 0x18 32 read-write 0 0xFFFFFFE0 INT_FIRST This indicates the first PTD that is used by the hardware when it is processing the INT list. 5 5 read-write INT_BASE Base address to be used by the hardware to find the start of the INT list. 10 22 read-write DATA_PAYLOAD_BASE_ADDR Memory base address that indicates the start of the data payload buffers 0x1C 32 read-write 0 0xFFFF0000 DAT_BASE Base address to be used by the hardware to find the start of the data payload section. 16 16 read-write USBCMD USB Command register 0x20 32 read-write 0 0x1F00078F RS Run/Stop: 1b = Run. 0 1 read-write HCRESET Host Controller Reset: This control bit is used by the software to reset the host controller. 1 1 read-write FLS Frame List Size: This field specifies the size of the frame list. 2 2 read-write LHCR Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. 7 1 read-write ATL_EN ATL List enabled. 8 1 read-write ISO_EN ISO List enabled. 9 1 read-write INT_EN INT List enabled. 10 1 read-write HIRD Host-Initiated Resume Duration. 24 4 read-write LPM_RWU bRemoteWake field. 28 1 read-write USBSTS USB Interrupt Status register 0x24 32 read-write 0 0xF000C PCD Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. 2 1 read-write FLR Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. 3 1 read-write ATL_IRQ ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. 16 1 read-write ISO_IRQ ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. 17 1 read-write INT_IRQ INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. 18 1 read-write SOF_IRQ SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. 19 1 read-write USBINTR USB Interrupt Enable register 0x28 32 read-write 0 0xF000C PCDE Port Change Detect Interrupt Enable: 1: enable 0: disable. 2 1 read-write FLRE Frame List Rollover Interrupt Enable: 1: enable 0: disable. 3 1 read-write ATL_IRQ_E ATL IRQ Enable bit: 1: enable 0: disable. 16 1 read-write ISO_IRQ_E ISO IRQ Enable bit: 1: enable 0: disable. 17 1 read-write INT_IRQ_E INT IRQ Enable bit: 1: enable 0: disable. 18 1 read-write SOF_E SOF Interrupt Enable bit: 1: enable 0: disable. 19 1 read-write PORTSC1 Port Status and Control register 0x2C 32 read-write 0 0xFFFFDFFF CCS Current Connect Status: Logic 1 indicates a device is present on the port. 0 1 read-write CSC Connect Status Change: Logic 1 means that the value of CCS has changed. 1 1 read-write PED Port Enabled/Disabled. 2 1 read-write PEDC Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. 3 1 read-write OCA Over-current active: Logic 1 means that this port has an over-current condition. 4 1 read-write OCC Over-current change: Logic 1 means that the value of OCA has changed. 5 1 read-write FPR Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. 6 1 read-write SUSP Suspend: Logic 1 means port is in the suspend state. 7 1 read-write PR Port Reset: Logic 1 means the port is in the reset state. 8 1 read-write SUS_L1 Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. 9 1 read-write LS Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. 10 2 read-only PP Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. 12 1 read-write PIC Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. 14 2 read-write PTC Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. 16 4 read-write PSPD Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. 20 2 read-write WOO Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. 22 1 read-write SUS_STAT These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. 23 2 read-write DEV_ADD Device Address for LPM tokens. 25 7 read-write ATL_PTD_DONE_MAP Done map for each ATL PTD 0x30 32 read-write 0 0xFFFFFFFF ATL_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write ATL_PTD_SKIP_MAP Skip map for each ATL PTD 0x34 32 read-write 0 0xFFFFFFFF ATL_SKIP When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. 0 32 read-write ISO_PTD_DONE_MAP Done map for each ISO PTD 0x38 32 read-write 0 0xFFFFFFFF ISO_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write ISO_PTD_SKIP_MAP Skip map for each ISO PTD 0x3C 32 read-write 0 0xFFFFFFFF ISO_SKIP The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write INT_PTD_DONE_MAP Done map for each INT PTD 0x40 32 read-write 0 0xFFFFFFFF INT_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write INT_PTD_SKIP_MAP Skip map for each INT PTD 0x44 32 read-write 0 0xFFFFFFFF INT_SKIP When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. 0 32 read-write LAST_PTD_INUSE Marks the last PTD in the list for ISO, INT and ATL 0x48 32 read-write 0 0x1F1F1F ATL_LAST If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. 0 5 read-write ISO_LAST This indicates the last PTD in the ISO list. 8 5 read-write INT_LAST This indicates the last PTD in the INT list. 16 5 read-write UTMIPLUS_ULPI_DEBUG Register to read/write registers in the attached USB PHY 0x4C 32 read-write 0 0x83FFFFFF PHY_ADDR UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. 0 8 read-write PHY_WDATA UTMI+ mode: Reserved. 8 8 read-write PHY_RDATA UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register. 16 8 read-write PHY_RW UTMI+ mode: Reserved. 24 1 read-write PHY_ACCESS Software writes this bit to one to start a read or write operation. 25 1 read-write PHY_MODE This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW. 31 1 read-write PORTMODE Controls the port if it is attached to the host block or the device block 0x50 32 read-write 0x40000 0xD0101 ID0 Port 0 ID pin value. 0 1 read-write ID0_EN Port 0 ID pin pull-up enable. 8 1 read-write DEV_ENABLE If this bit is set to one, one of the ports will behave as a USB device. 16 1 read-write SW_CTRL_PDCOM This bit indicates if the PHY power-down input is controlled by software or by hardware. 18 1 read-write SW_PDCOM This bit is only used when SW_CTRL_PDCOM is set to 1b. 19 1 read-write SHA0 SHA SHA 0x400A4000 0 0x60 registers CTRL Control register 0 32 read-write 0 0x113 MODE This field is used to select the operational mode of SHA block. 0 2 read-write NEW When this bit is set, a new hash operation is started. 4 1 read-write DMA When this bit is set, the DMA is used to fill INDATA. 8 1 read-write STATUS Status register 0x4 32 read-write 0 0x7 WAITING This field indicates if the block is waiting for more data to process. 0 1 read-write DIGEST This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started. 1 1 read-write ERROR This field indicates if an error has occurred. 2 1 read-write INTENSET Interrupt Enable register 0x8 32 read-write 0 0x7 WAITING This field indicates if interrupt should be enabled when waiting for input data. 0 1 read-write DIGEST This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence). 1 1 read-write ERROR This field indicates if interrupt is generated on an ERROR (as defined in STAT register). 2 1 read-write INTENCLR Interrupt Clear register 0xC 32 read-write 0 0x7 WAITING Writing a 1 clears the interrupt enabled by the INTENSET register. 0 1 read-write DIGEST Writing a 1 clears the interrupt enabled by the INTENSET register. 1 1 read-write ERROR Writing a 1 clears the interrupt enabled by the INTENSET register. 2 1 read-write MEMCTRL Memory Control register 0x10 32 read-write 0 0x7FF0001 MASTER This field is used to enable SHA block as AHB bus master. 0 1 read-write COUNT This field indicates the number of 512-bit blocks to copy starting at MEMADDR. 16 11 read-write MEMADDR Memory Address register 0x14 32 read-write 0 0xFFFFFFFF BASEADDR This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from. 0 32 read-write INDATA Input Data register 0x20 32 read-write 0 0xFFFFFFFF DATA In this field the next word is written in little-endian format. 0 32 read-write 7 0x4 ALIAS[%s] Alias register 0x24 32 read-write 0 0xFFFFFFFF DATA In this field the next word is written in little-endian format. 0 32 read-write 8 0x4 DIGEST[%s] Digest register 0x40 32 read-only 0 0xFFFFFFFF DIGEST This field contains one word of the Digest. 0 32 read-only ITM Instrumentation Trace Macrocell Registers ITM ITM_ 0xE0000000 0 0x1000 registers STIM0_READ Stimulus Port Register 0 (for reading) STIM0_READ_STIM0_WRITE 0 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM0_WRITE Stimulus Port Register 0 (for writing) STIM0_READ_STIM0_WRITE 0 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM1_READ Stimulus Port Register 1 (for reading) STIM1_READ_STIM1_WRITE 0x4 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM1_WRITE Stimulus Port Register 1 (for writing) STIM1_READ_STIM1_WRITE 0x4 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM2_READ Stimulus Port Register 2 (for reading) STIM2_READ_STIM2_WRITE 0x8 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM2_WRITE Stimulus Port Register 2 (for writing) STIM2_READ_STIM2_WRITE 0x8 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM3_READ Stimulus Port Register 3 (for reading) STIM3_READ_STIM3_WRITE 0xC 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM3_WRITE Stimulus Port Register 3 (for writing) STIM3_READ_STIM3_WRITE 0xC 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM4_READ Stimulus Port Register 4 (for reading) STIM4_READ_STIM4_WRITE 0x10 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM4_WRITE Stimulus Port Register 4 (for writing) STIM4_READ_STIM4_WRITE 0x10 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM5_READ Stimulus Port Register 5 (for reading) STIM5_READ_STIM5_WRITE 0x14 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM5_WRITE Stimulus Port Register 5 (for writing) STIM5_READ_STIM5_WRITE 0x14 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM6_READ Stimulus Port Register 6 (for reading) STIM6_READ_STIM6_WRITE 0x18 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM6_WRITE Stimulus Port Register 6 (for writing) STIM6_READ_STIM6_WRITE 0x18 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM7_READ Stimulus Port Register 7 (for reading) STIM7_READ_STIM7_WRITE 0x1C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM7_WRITE Stimulus Port Register 7 (for writing) STIM7_READ_STIM7_WRITE 0x1C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM8_READ Stimulus Port Register 8 (for reading) STIM8_READ_STIM8_WRITE 0x20 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM8_WRITE Stimulus Port Register 8 (for writing) STIM8_READ_STIM8_WRITE 0x20 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM9_READ Stimulus Port Register 9 (for reading) STIM9_READ_STIM9_WRITE 0x24 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM9_WRITE Stimulus Port Register 9 (for writing) STIM9_READ_STIM9_WRITE 0x24 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM10_READ Stimulus Port Register 10 (for reading) STIM10_READ_STIM10_WRITE 0x28 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM10_WRITE Stimulus Port Register 10 (for writing) STIM10_READ_STIM10_WRITE 0x28 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM11_READ Stimulus Port Register 11 (for reading) STIM11_READ_STIM11_WRITE 0x2C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM11_WRITE Stimulus Port Register 11 (for writing) STIM11_READ_STIM11_WRITE 0x2C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM12_READ Stimulus Port Register 12 (for reading) STIM12_READ_STIM12_WRITE 0x30 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM12_WRITE Stimulus Port Register 12 (for writing) STIM12_READ_STIM12_WRITE 0x30 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM13_READ Stimulus Port Register 13 (for reading) STIM13_READ_STIM13_WRITE 0x34 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM13_WRITE Stimulus Port Register 13 (for writing) STIM13_READ_STIM13_WRITE 0x34 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM14_READ Stimulus Port Register 14 (for reading) STIM14_READ_STIM14_WRITE 0x38 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM14_WRITE Stimulus Port Register 14 (for writing) STIM14_READ_STIM14_WRITE 0x38 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM15_READ Stimulus Port Register 15 (for reading) STIM15_READ_STIM15_WRITE 0x3C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM15_WRITE Stimulus Port Register 15 (for writing) STIM15_READ_STIM15_WRITE 0x3C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM16_READ Stimulus Port Register 16 (for reading) STIM16_READ_STIM16_WRITE 0x40 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM16_WRITE Stimulus Port Register 16 (for writing) STIM16_READ_STIM16_WRITE 0x40 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM17_READ Stimulus Port Register 17 (for reading) STIM17_READ_STIM17_WRITE 0x44 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM17_WRITE Stimulus Port Register 17 (for writing) STIM17_READ_STIM17_WRITE 0x44 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM18_READ Stimulus Port Register 18 (for reading) STIM18_READ_STIM18_WRITE 0x48 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM18_WRITE Stimulus Port Register 18 (for writing) STIM18_READ_STIM18_WRITE 0x48 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM19_READ Stimulus Port Register 19 (for reading) STIM19_READ_STIM19_WRITE 0x4C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM19_WRITE Stimulus Port Register 19 (for writing) STIM19_READ_STIM19_WRITE 0x4C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM20_READ Stimulus Port Register 20 (for reading) STIM20_READ_STIM20_WRITE 0x50 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM20_WRITE Stimulus Port Register 20 (for writing) STIM20_READ_STIM20_WRITE 0x50 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM21_READ Stimulus Port Register 21 (for reading) STIM21_READ_STIM21_WRITE 0x54 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM21_WRITE Stimulus Port Register 21 (for writing) STIM21_READ_STIM21_WRITE 0x54 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM22_READ Stimulus Port Register 22 (for reading) STIM22_READ_STIM22_WRITE 0x58 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM22_WRITE Stimulus Port Register 22 (for writing) STIM22_READ_STIM22_WRITE 0x58 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM23_READ Stimulus Port Register 23 (for reading) STIM23_READ_STIM23_WRITE 0x5C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM23_WRITE Stimulus Port Register 23 (for writing) STIM23_READ_STIM23_WRITE 0x5C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM24_READ Stimulus Port Register 24 (for reading) STIM24_READ_STIM24_WRITE 0x60 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM24_WRITE Stimulus Port Register 24 (for writing) STIM24_READ_STIM24_WRITE 0x60 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM25_READ Stimulus Port Register 25 (for reading) STIM25_READ_STIM25_WRITE 0x64 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM25_WRITE Stimulus Port Register 25 (for writing) STIM25_READ_STIM25_WRITE 0x64 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM26_READ Stimulus Port Register 26 (for reading) STIM26_READ_STIM26_WRITE 0x68 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM26_WRITE Stimulus Port Register 26 (for writing) STIM26_READ_STIM26_WRITE 0x68 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM27_READ Stimulus Port Register 27 (for reading) STIM27_READ_STIM27_WRITE 0x6C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM27_WRITE Stimulus Port Register 27 (for writing) STIM27_READ_STIM27_WRITE 0x6C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM28_READ Stimulus Port Register 28 (for reading) STIM28_READ_STIM28_WRITE 0x70 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM28_WRITE Stimulus Port Register 28 (for writing) STIM28_READ_STIM28_WRITE 0x70 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM29_READ Stimulus Port Register 29 (for reading) STIM29_READ_STIM29_WRITE 0x74 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM29_WRITE Stimulus Port Register 29 (for writing) STIM29_READ_STIM29_WRITE 0x74 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM30_READ Stimulus Port Register 30 (for reading) STIM30_READ_STIM30_WRITE 0x78 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM30_WRITE Stimulus Port Register 30 (for writing) STIM30_READ_STIM30_WRITE 0x78 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write STIM31_READ Stimulus Port Register 31 (for reading) STIM31_READ_STIM31_WRITE 0x7C 32 read-write 0 0xFFFFFFFE FIFOREADY no description available 0 1 read-write STIM31_WRITE Stimulus Port Register 31 (for writing) STIM31_READ_STIM31_WRITE 0x7C 32 read-write 0 0 STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet. 0 32 read-write TER Trace Enable Register 0xE00 32 read-write 0 0xFFFFFFFF STIMENA For bit STIMENA[n], in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled 0 32 read-write TPR Trace Privilege Register 0xE40 32 read-write 0 0xFFFFFFFF PRIVMASK Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24] 0 4 read-write TCR Trace Control Register 0xE80 32 read-write 0 0xFFFFFFFF ITMENA no description available 0 1 read-write ITMENA_0 Disabled. 0 ITMENA_1 Enabled. 0x1 TSENA no description available 1 1 read-write TSENA_0 Disabled. 0 TSENA_1 Enabled. 0x1 SYNCENA no description available 2 1 read-write SYNCENA_0 Disabled. 0 SYNCENA_1 Enabled. 0x1 TXENA no description available 3 1 read-write TXENA_0 Disabled. 0 TXENA_1 Enabled. 0x1 SWOENA no description available 4 1 read-write SWOENA_0 Timestamp counter uses the processor system clock. 0 SWOENA_1 Timestamp counter uses asynchronous clock from the TPIU interface. 0x1 TSPrescale Local timestamp prescaler, used with the trace packet reference clock. 8 2 read-write TSPrescale_0 No prescaling. 0 TSPrescale_1 Divide by 4. 0x1 TSPrescale_2 Divide by 16. 0x2 TSPrescale_3 Divide by 64. 0x3 GTSFREQ Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. 10 2 read-write GTSFREQ_0 Disable generation of global timestamps. 0 GTSFREQ_1 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles. 0x1 GTSFREQ_2 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles. 0x2 GTSFREQ_3 Generate a timestamp after every packet, if the output FIFO is empty. 0x3 TraceBusID Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field. 16 7 read-write BUSY Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained. 23 1 read-only BUSY_0 ITM is not processing any events. 0 BUSY_1 ITM events present and beeing drained. 0x1 LAR Lock Access Register 0xFB0 32 read-write 0 0 WriteAccessCode Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. 0 32 read-write LSR Lock Status Register 0xFB4 32 read-only 0x1 0xFFFFFFFD IMP Lock mechanism is implemented. This bit always reads 1. 0 1 read-only STATUS Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. 1 1 read-only s8BIT Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. 2 1 read-only PID4 Peripheral Identification Register 4. 0xFD0 32 read-only 0x4 0xFFFFFFFF JEP106 JEP106 continuation code. 0 4 read-only c4KB 4KB Count 4 4 read-only PID5 Peripheral Identification Register 5. 0xFD4 32 read-only 0 0xFFFFFFFF PID6 Peripheral Identification Register 6. 0xFD8 32 read-only 0 0xFFFFFFFF PID7 Peripheral Identification Register 7. 0xFDC 32 read-only 0 0xFFFFFFFF PID0 Peripheral Identification Register 0. 0xFE0 32 read-only 0x2 0xFFFFFFFF PartNumber Part Number [7:0] 0 8 read-only PID1 Peripheral Identification Register 1. 0xFE4 32 read-only 0xB0 0xFFFFFFFF PartNumber Part Number [11:8] 0 4 read-only JEP106_identity_code JEP106 identity code [3:0] 4 4 read-only PID2 Peripheral Identification Register 2. 0xFE8 32 read-only 0x3B 0xFFFFFFFF JEP106_identity_code JEP106 identity code [6:4] 0 3 read-only Revision Revision 4 4 read-only PID3 Peripheral Identification Register 3. 0xFEC 32 read-only 0 0xFFFFFFFF CustomerModified Customer Modified. 0 4 read-only RevAnd RevAnd 4 4 read-only CID0 Component Identification Register 0. 0xFF0 32 read-only 0xD 0xFFFFFFFF Preamble Preamble 0 8 read-only CID1 Component Identification Register 1. 0xFF4 32 read-only 0xE0 0xFFFFFFFF Preamble Preamble 0 4 read-only ComponentClass Component class 4 4 read-only ComponentClass_1 ROM table. 0x1 ComponentClass_9 CoreSight component. 0x9 ComponentClass_15 PrimeCell of system component with no standardized register layout, for backward compatibility. 0xF CID2 Component Identification Register 2. 0xFF8 32 read-only 0x5 0xFFFFFFFF Preamble Preamble 0 8 read-only CID3 Component Identification Register 3. 0xFFC 32 read-only 0xB1 0xFFFFFFFF Preamble Preamble 0 8 read-only SystemControl System Control Block SCB SCB_ 0xE000E000 0 0xF40 registers ACTLR Auxiliary Control Register, 0x8 32 read-write 0 0xFFFFFFFF DISMCYCINT Disables interruption of multi-cycle instructions. 0 1 read-write DISDEFWBUF Disables write buffer use during default memory map accesses. 1 1 read-write DISFOLD Disables folding of IT instructions. 2 1 read-write CPUID CPUID Base Register 0xD00 32 read-only 0x410FC240 0xFFFFFFFF REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only PARTNO Indicates part number 4 12 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only IMPLEMENTER Implementer code 24 8 read-only ICSR Interrupt Control and State Register 0xD04 32 read-write 0 0xFFFFFFFF VECTACTIVE Active exception number 0 9 read-only RETTOBASE no description available 11 1 read-only RETTOBASE_0 there are preempted active exceptions to execute 0 RETTOBASE_1 there are no active exceptions, or the currently-executing exception is the only active exception 0x1 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only ISRPENDING no description available 22 1 read-only ISRPREEMPT no description available 23 1 read-only ISRPREEMPT_0 Will not service 0 ISRPREEMPT_1 Will service a pending exception 0x1 PENDSTCLR no description available 25 1 write-only PENDSTCLR_0 no effect 0 PENDSTCLR_1 removes the pending state from the SysTick exception 0x1 PENDSTSET no description available 26 1 read-write PENDSTSET_0 write: no effect; read: SysTick exception is not pending 0 PENDSTSET_1 write: changes SysTick exception state to pending; read: SysTick exception is pending 0x1 PENDSVCLR no description available 27 1 write-only PENDSVCLR_0 no effect 0 PENDSVCLR_1 removes the pending state from the PendSV exception 0x1 PENDSVSET no description available 28 1 read-write PENDSVSET_0 write: no effect; read: PendSV exception is not pending 0 PENDSVSET_1 write: changes PendSV exception state to pending; read: PendSV exception is pending 0x1 NMIPENDSET no description available 31 1 read-write NMIPENDSET_0 write: no effect; read: NMI exception is not pending 0 NMIPENDSET_1 write: changes NMI exception state to pending; read: NMI exception is pending 0x1 VTOR Vector Table Offset Register 0xD08 32 read-write 0 0xFFFFFFFF TBLOFF Vector table base offset 7 25 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write 0xFA050000 0xFFFFFFFF VECTRESET no description available 0 1 write-only VECTCLRACTIVE no description available 1 1 write-only SYSRESETREQ no description available 2 1 write-only SYSRESETREQ_0 no system reset request 0 SYSRESETREQ_1 asserts a signal to the outer system that requests a reset 0x1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write ENDIANNESS no description available 15 1 read-only ENDIANNESS_0 Little-endian 0 ENDIANNESS_1 Big-endian 0x1 VECTKEY Register key 16 16 read-write SCR System Control Register 0xD10 32 read-write 0 0xFFFFFFFF SLEEPONEXIT no description available 1 1 read-write SLEEPONEXIT_0 o not sleep when returning to Thread mode 0 SLEEPONEXIT_1 enter sleep, or deep sleep, on return from an ISR 0x1 SLEEPDEEP no description available 2 1 read-write SLEEPDEEP_0 sleep 0 SLEEPDEEP_1 deep sleep 0x1 SEVONPEND no description available 4 1 read-write SEVONPEND_0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 SEVONPEND_1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor 0x1 CCR Configuration and Control Register 0xD14 32 read-write 0 0xFFFFFFFF NONBASETHRDENA no description available 0 1 read-write NONBASETHRDENA_0 processor can enter Thread mode only when no exception is active 0 NONBASETHRDENA_1 processor can enter Thread mode from any level under the control of an EXC_RETURN value 0x1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write USERSETMPEND_0 disable 0 USERSETMPEND_1 enable 0x1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write UNALIGN_TRP_0 do not trap unaligned halfword and word accesses 0 UNALIGN_TRP_1 trap unaligned halfword and word accesses 0x1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write DIV_0_TRP_0 do not trap divide by 0 0 DIV_0_TRP_1 trap divide by 0 0x1 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write BFHFNMIGN_0 data bus faults caused by load and store instructions cause a lock-up 0 BFHFNMIGN_1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 0x1 STKALIGN Indicates stack alignment on exception entry 9 1 read-write STKALIGN_0 4-byte aligned 0 STKALIGN_1 8-byte aligned 0x1 SHPR1 System Handler Priority Register 1 0xD18 32 read-write 0 0xFFFFFFFF PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SHPR2 System Handler Priority Register 2 0xD1C 32 read-write 0 0xFFFFFFFF PRI_11 Priority of system handler 11, SVCall 24 8 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write 0 0xFFFFFFFF PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SHCSR System Handler Control and State Register 0xD24 32 read-write 0 0xFFFFFFFF MEMFAULTACT no description available 0 1 read-write MEMFAULTACT_0 exception is not active 0 MEMFAULTACT_1 exception is active 0x1 BUSFAULTACT no description available 1 1 read-write BUSFAULTACT_0 exception is not active 0 BUSFAULTACT_1 exception is active 0x1 USGFAULTACT no description available 3 1 read-write USGFAULTACT_0 exception is not active 0 USGFAULTACT_1 exception is active 0x1 SVCALLACT no description available 7 1 read-write SVCALLACT_0 exception is not active 0 SVCALLACT_1 exception is active 0x1 MONITORACT no description available 8 1 read-write MONITORACT_0 exception is not active 0 MONITORACT_1 exception is active 0x1 PENDSVACT no description available 10 1 read-write PENDSVACT_0 exception is not active 0 PENDSVACT_1 exception is active 0x1 SYSTICKACT no description available 11 1 read-write SYSTICKACT_0 exception is not active 0 SYSTICKACT_1 exception is active 0x1 USGFAULTPENDED no description available 12 1 read-write USGFAULTPENDED_0 exception is not pending 0 USGFAULTPENDED_1 exception is pending 0x1 MEMFAULTPENDED no description available 13 1 read-write MEMFAULTPENDED_0 exception is not pending 0 MEMFAULTPENDED_1 exception is pending 0x1 BUSFAULTPENDED no description available 14 1 read-write BUSFAULTPENDED_0 exception is not pending 0 BUSFAULTPENDED_1 exception is pending 0x1 SVCALLPENDED no description available 15 1 read-write SVCALLPENDED_0 exception is not pending 0 SVCALLPENDED_1 exception is pending 0x1 MEMFAULTENA no description available 16 1 read-write MEMFAULTENA_0 disable the exception 0 MEMFAULTENA_1 enable the exception 0x1 BUSFAULTENA no description available 17 1 read-write BUSFAULTENA_0 disable the exception 0 BUSFAULTENA_1 enable the exception 0x1 USGFAULTENA no description available 18 1 read-write USGFAULTENA_0 disable the exception 0 USGFAULTENA_1 enable the exception 0x1 CFSR Configurable Fault Status Registers 0xD28 32 read-write 0 0xFFFFFFFF IACCVIOL no description available 0 1 read-write IACCVIOL_0 no instruction access violation fault 0 IACCVIOL_1 the processor attempted an instruction fetch from a location that does not permit execution 0x1 DACCVIOL no description available 1 1 read-write DACCVIOL_0 no data access violation fault 0 DACCVIOL_1 the processor attempted a load or store at a location that does not permit the operation 0x1 MUNSTKERR no description available 3 1 read-write MUNSTKERR_0 no unstacking fault 0 MUNSTKERR_1 unstack for an exception return has caused one or more access violations 0x1 MSTKERR no description available 4 1 read-write MSTKERR_0 no stacking fault 0 MSTKERR_1 stacking for an exception entry has caused one or more access violations 0x1 MLSPERR no description available 5 1 read-write MLSPERR_0 No MemManage fault occurred during floating-point lazy state preservation 0 MLSPERR_1 A MemManage fault occurred during floating-point lazy state preservation 0x1 MMARVALID no description available 7 1 read-write MMARVALID_0 value in MMAR is not a valid fault address 0 MMARVALID_1 MMAR holds a valid fault address 0x1 IBUSERR no description available 8 1 read-write IBUSERR_0 no instruction bus error 0 IBUSERR_1 instruction bus error 0x1 PRECISERR no description available 9 1 read-write PRECISERR_0 no precise data bus error 0 PRECISERR_1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 0x1 IMPRECISERR no description available 10 1 read-write IMPRECISERR_0 no imprecise data bus error 0 IMPRECISERR_1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 0x1 UNSTKERR no description available 11 1 read-write UNSTKERR_0 no unstacking fault 0 UNSTKERR_1 unstack for an exception return has caused one or more BusFaults 0x1 STKERR no description available 12 1 read-write STKERR_0 no stacking fault 0 STKERR_1 stacking for an exception entry has caused one or more BusFaults 0x1 LSPERR no description available 13 1 read-write LSPERR_0 No bus fault occurred during floating-point lazy state preservation 0 LSPERR_1 A bus fault occurred during floating-point lazy state preservation 0x1 BFARVALID no description available 15 1 read-write BFARVALID_0 value in BFAR is not a valid fault address 0 BFARVALID_1 BFAR holds a valid fault address 0x1 UNDEFINSTR no description available 16 1 read-write UNDEFINSTR_0 no undefined instruction UsageFault 0 UNDEFINSTR_1 the processor has attempted to execute an undefined instruction 0x1 INVSTATE no description available 17 1 read-write INVSTATE_0 no invalid state UsageFault 0 INVSTATE_1 the processor has attempted to execute an instruction that makes illegal use of the EPSR 0x1 INVPC no description available 18 1 read-write INVPC_0 no invalid PC load UsageFault 0 INVPC_1 the processor has attempted an illegal load of EXC_RETURN to the PC 0x1 NOCP no description available 19 1 read-write NOCP_0 no UsageFault caused by attempting to access a coprocessor 0 NOCP_1 the processor has attempted to access a coprocessor 0x1 UNALIGNED no description available 24 1 read-write UNALIGNED_0 no unaligned access fault, or unaligned access trapping not enabled 0 UNALIGNED_1 the processor has made an unaligned memory access 0x1 DIVBYZERO no description available 25 1 read-write DIVBYZERO_0 no divide by zero fault, or divide by zero trapping not enabled 0 DIVBYZERO_1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 0x1 HFSR HardFault Status register 0xD2C 32 read-write 0 0xFFFFFFFF VECTTBL no description available 1 1 read-write VECTTBL_0 no BusFault on vector table read 0 VECTTBL_1 BusFault on vector table read 0x1 FORCED no description available 30 1 read-write FORCED_0 no forced HardFault 0 FORCED_1 forced HardFault 0x1 DEBUGEVT no description available 31 1 read-write DFSR Debug Fault Status Register 0xD30 32 read-write 0 0xFFFFFFFF HALTED no description available 0 1 read-write HALTED_0 No active halt request debug event 0 HALTED_1 Halt request debug event active 0x1 BKPT no description available 1 1 read-write BKPT_0 No current breakpoint debug event 0 BKPT_1 At least one current breakpoint debug event 0x1 DWTTRAP no description available 2 1 read-write DWTTRAP_0 No current debug events generated by the DWT 0 DWTTRAP_1 At least one current debug event generated by the DWT 0x1 VCATCH no description available 3 1 read-write VCATCH_0 No Vector catch triggered 0 VCATCH_1 Vector catch triggered 0x1 EXTERNAL no description available 4 1 read-write EXTERNAL_0 No EDBGRQ debug event 0 EXTERNAL_1 EDBGRQ debug event 0x1 MMFAR MemManage Address Register 0xD34 32 read-write 0 0xFFFFFFFF ADDRESS Address of MemManage fault location 0 32 read-write BFAR BusFault Address Register 0xD38 32 read-write 0 0xFFFFFFFF ADDRESS Address of the BusFault location 0 32 read-write AFSR Auxiliary Fault Status Register 0xD3C 32 read-write 0 0xFFFFFFFF AUXFAULT Latched version of the AUXFAULT inputs 0 32 read-write CPACR Coprocessor Access Control Register 0xD88 32 read-write 0 0xFFFFFFFF CP10 Access privileges for coprocessor 10. 20 2 read-write CP10_0 Access denied. Any attempted access generates a NOCP UsageFault 0 CP10_1 Privileged access only. An unprivileged access generates a NOCP fault. 0x1 CP10_3 Full access. 0x3 CP11 Access privileges for coprocessor 11. 22 2 read-write CP11_0 Access denied. Any attempted access generates a NOCP UsageFault 0 CP11_1 Privileged access only. An unprivileged access generates a NOCP fault. 0x1 CP11_3 Full access. 0x3 FPCCR Floating-point Context Control Register 0xF34 32 read-write 0xC0000000 0xFFFFFFFF LSPACT Lazy state preservation. 0 1 read-write LSPACT_0 Lazy state preservation is not active. 0 LSPACT_1 Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. 0x1 USER Privilege level when the floating-point stack frame was allocated. 1 1 read-write USER_0 Privilege level was not user when the floating-point stack frame was allocated. 0 USER_1 Privilege level was user when the floating-point stack frame was allocated. 0x1 THREAD Mode when the floating-point stack frame was allocated. 3 1 read-write THREAD_0 Mode was not Thread Mode when the floating-point stack frame was allocated. 0 THREAD_1 Mode was Thread Mode when the floating-point stack frame was allocated. 0x1 HFRDY Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated. 4 1 read-write HFRDY_0 Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 0 HFRDY_1 Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 0x1 MMRDY Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated. 5 1 read-write MMRDY_0 MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 0 MMRDY_1 MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 0x1 BFRDY Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated. 6 1 read-write BFRDY_0 BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 0 BFRDY_1 BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 0x1 MONRDY Permission to set the MON_PEND when the floating-point stack frame was allocated. 8 1 read-write MONRDY_0 DebugMonitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. 0 MONRDY_1 DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. 0x1 LSPEN Lazy state preservation for floating-point context. 30 1 read-write LSPEN_0 Disable automatic lazy state preservation for floating-point context. 0 LSPEN_1 Enable automatic lazy state preservation for floating-point context. 0x1 ASPEN Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 31 1 read-write ASPEN_0 Disable CONTROL2 setting on execution of a floating-point instruction. 0 ASPEN_1 Enable CONTROL2 setting on execution of a floating-point instruction. 0x1 FPCAR Floating-point Context Address Register 0xF38 32 read-write 0 0 ADDRESS The location of the unpopulated floating-point register space allocated on an exception stack frame. 3 29 read-write FPDSCR Floating-point Default Status Control Register 0xF3C 32 read-write 0 0xFFFFFFFF RMode Default value for FPSCR.RMode (Rounding Mode control field). 22 2 read-write RMode_0 Round to Nearest (RN) mode 0 RMode_1 Round towards Plus Infinity (RP) mode. 0x1 RMode_2 Round towards Minus Infinity (RM) mode. 0x2 RMode_3 Round towards Zero (RZ) mode. 0x3 FZ Default value for FPSCR.FZ (Flush-to-zero mode control bit). 24 1 read-write FZ_0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 0 FZ_1 Flush-to-zero mode enabled. 0x1 DN Default value for FPSCR.DN (Default NaN mode control bit). 25 1 read-write DN_0 NaN operands propagate through to the output of a floating-point operation. 0 DN_1 Any operation involving one or more NaNs returns the Default NaN. 0x1 AHP Default value for FPSCR.AHP (Alternative half-precision control bit). 26 1 read-write AHP_0 IEEE half-precision format selected. 0 AHP_1 Alternative half-precision format selected. 0x1 SysTick System timer SysTick SYST_ 0xE000E010 0 0x10 registers CSR SysTick Control and Status Register 0 32 read-write 0x4 0xFFFFFFFF ENABLE no description available 0 1 read-write ENABLE_0 counter disabled 0 ENABLE_1 counter enabled 0x1 TICKINT no description available 1 1 read-write TICKINT_0 counting down to 0 does not assert the SysTick exception request 0 TICKINT_1 counting down to 0 asserts the SysTick exception request 0x1 CLKSOURCE no description available 2 1 read-write CLKSOURCE_0 external clock 0 CLKSOURCE_1 processor clock 0x1 COUNTFLAG no description available 16 1 read-write RVR SysTick Reload Value Register 0x4 32 read-write 0 0xFFFFFFFF RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write CVR SysTick Current Value Register 0x8 32 read-write 0 0xFFFFFFFF CURRENT Current value at the time the register is accessed 0 24 read-write CALIB SysTick Calibration Value Register 0xC 32 read-only 0x80000000 0xFFFFFFFF TENMS Reload value to use for 10ms timing 0 24 read-only SKEW no description available 30 1 read-only SKEW_0 10ms calibration value is exact 0 SKEW_1 10ms calibration value is inexact, because of the clock frequency 0x1 NOREF no description available 31 1 read-only NOREF_0 The reference clock is provided 0 NOREF_1 The reference clock is not provided 0x1 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0 0xE04 registers NVICISER0 Interrupt Set Enable Register n 0 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIP0 Interrupt Priority Register n 0x300 8 read-write 0 0xFF PRI0 Priority of interrupt 0 0 8 read-write NVICIP1 Interrupt Priority Register n 0x301 8 read-write 0 0xFF PRI1 Priority of interrupt 1 0 8 read-write NVICIP2 Interrupt Priority Register n 0x302 8 read-write 0 0xFF PRI2 Priority of interrupt 2 0 8 read-write NVICIP3 Interrupt Priority Register n 0x303 8 read-write 0 0xFF PRI3 Priority of interrupt 3 0 8 read-write NVICIP4 Interrupt Priority Register n 0x304 8 read-write 0 0xFF PRI4 Priority of interrupt 4 0 8 read-write NVICIP5 Interrupt Priority Register n 0x305 8 read-write 0 0xFF PRI5 Priority of interrupt 5 0 8 read-write NVICIP6 Interrupt Priority Register n 0x306 8 read-write 0 0xFF PRI6 Priority of interrupt 6 0 8 read-write NVICIP7 Interrupt Priority Register n 0x307 8 read-write 0 0xFF PRI7 Priority of interrupt 7 0 8 read-write NVICIP8 Interrupt Priority Register n 0x308 8 read-write 0 0xFF PRI8 Priority of interrupt 8 0 8 read-write NVICIP9 Interrupt Priority Register n 0x309 8 read-write 0 0xFF PRI9 Priority of interrupt 9 0 8 read-write NVICIP10 Interrupt Priority Register n 0x30A 8 read-write 0 0xFF PRI10 Priority of interrupt 10 0 8 read-write NVICIP11 Interrupt Priority Register n 0x30B 8 read-write 0 0xFF PRI11 Priority of interrupt 11 0 8 read-write NVICIP12 Interrupt Priority Register n 0x30C 8 read-write 0 0xFF PRI12 Priority of interrupt 12 0 8 read-write NVICIP13 Interrupt Priority Register n 0x30D 8 read-write 0 0xFF PRI13 Priority of interrupt 13 0 8 read-write NVICIP14 Interrupt Priority Register n 0x30E 8 read-write 0 0xFF PRI14 Priority of interrupt 14 0 8 read-write NVICIP15 Interrupt Priority Register n 0x30F 8 read-write 0 0xFF PRI15 Priority of interrupt 15 0 8 read-write NVICIP16 Interrupt Priority Register n 0x310 8 read-write 0 0xFF PRI16 Priority of interrupt 16 0 8 read-write NVICIP17 Interrupt Priority Register n 0x311 8 read-write 0 0xFF PRI17 Priority of interrupt 17 0 8 read-write NVICIP18 Interrupt Priority Register n 0x312 8 read-write 0 0xFF PRI18 Priority of interrupt 18 0 8 read-write NVICIP19 Interrupt Priority Register n 0x313 8 read-write 0 0xFF PRI19 Priority of interrupt 19 0 8 read-write NVICIP20 Interrupt Priority Register n 0x314 8 read-write 0 0xFF PRI20 Priority of interrupt 20 0 8 read-write NVICIP21 Interrupt Priority Register n 0x315 8 read-write 0 0xFF PRI21 Priority of interrupt 21 0 8 read-write NVICIP22 Interrupt Priority Register n 0x316 8 read-write 0 0xFF PRI22 Priority of interrupt 22 0 8 read-write NVICIP23 Interrupt Priority Register n 0x317 8 read-write 0 0xFF PRI23 Priority of interrupt 23 0 8 read-write NVICIP24 Interrupt Priority Register n 0x318 8 read-write 0 0xFF PRI24 Priority of interrupt 24 0 8 read-write NVICIP25 Interrupt Priority Register n 0x319 8 read-write 0 0xFF PRI25 Priority of interrupt 25 0 8 read-write NVICIP26 Interrupt Priority Register n 0x31A 8 read-write 0 0xFF PRI26 Priority of interrupt 26 0 8 read-write NVICIP27 Interrupt Priority Register n 0x31B 8 read-write 0 0xFF PRI27 Priority of interrupt 27 0 8 read-write NVICIP28 Interrupt Priority Register n 0x31C 8 read-write 0 0xFF PRI28 Priority of interrupt 28 0 8 read-write NVICIP29 Interrupt Priority Register n 0x31D 8 read-write 0 0xFF PRI29 Priority of interrupt 29 0 8 read-write NVICIP30 Interrupt Priority Register n 0x31E 8 read-write 0 0xFF PRI30 Priority of interrupt 30 0 8 read-write NVICIP31 Interrupt Priority Register n 0x31F 8 read-write 0 0xFF PRI31 Priority of interrupt 31 0 8 read-write NVICIP32 Interrupt Priority Register n 0x320 8 read-write 0 0xFF PRI32 Priority of interrupt 32 0 8 read-write NVICIP33 Interrupt Priority Register n 0x321 8 read-write 0 0xFF PRI33 Priority of interrupt 33 0 8 read-write NVICIP34 Interrupt Priority Register n 0x322 8 read-write 0 0xFF PRI34 Priority of interrupt 34 0 8 read-write NVICIP35 Interrupt Priority Register n 0x323 8 read-write 0 0xFF PRI35 Priority of interrupt 35 0 8 read-write NVICIP36 Interrupt Priority Register n 0x324 8 read-write 0 0xFF PRI36 Priority of interrupt 36 0 8 read-write NVICIP37 Interrupt Priority Register n 0x325 8 read-write 0 0xFF PRI37 Priority of interrupt 37 0 8 read-write NVICIP38 Interrupt Priority Register n 0x326 8 read-write 0 0xFF PRI38 Priority of interrupt 38 0 8 read-write NVICIP39 Interrupt Priority Register n 0x327 8 read-write 0 0xFF PRI39 Priority of interrupt 39 0 8 read-write NVICIP40 Interrupt Priority Register n 0x328 8 read-write 0 0xFF PRI40 Priority of interrupt 40 0 8 read-write NVICIP41 Interrupt Priority Register n 0x329 8 read-write 0 0xFF PRI41 Priority of interrupt 41 0 8 read-write NVICIP42 Interrupt Priority Register n 0x32A 8 read-write 0 0xFF PRI42 Priority of interrupt 42 0 8 read-write NVICIP43 Interrupt Priority Register n 0x32B 8 read-write 0 0xFF PRI43 Priority of interrupt 43 0 8 read-write NVICIP44 Interrupt Priority Register n 0x32C 8 read-write 0 0xFF PRI44 Priority of interrupt 44 0 8 read-write NVICIP45 Interrupt Priority Register n 0x32D 8 read-write 0 0xFF PRI45 Priority of interrupt 45 0 8 read-write NVICIP46 Interrupt Priority Register n 0x32E 8 read-write 0 0xFF PRI46 Priority of interrupt 46 0 8 read-write NVICIP47 Interrupt Priority Register n 0x32F 8 read-write 0 0xFF PRI47 Priority of interrupt 47 0 8 read-write NVICIP48 Interrupt Priority Register n 0x330 8 read-write 0 0xFF PRI48 Priority of interrupt 48 0 8 read-write NVICIP49 Interrupt Priority Register n 0x331 8 read-write 0 0xFF PRI49 Priority of interrupt 49 0 8 read-write NVICIP50 Interrupt Priority Register n 0x332 8 read-write 0 0xFF PRI50 Priority of interrupt 50 0 8 read-write NVICIP51 Interrupt Priority Register n 0x333 8 read-write 0 0xFF PRI51 Priority of interrupt 51 0 8 read-write NVICIP52 Interrupt Priority Register n 0x334 8 read-write 0 0xFF PRI52 Priority of interrupt 52 0 8 read-write NVICIP53 Interrupt Priority Register n 0x335 8 read-write 0 0xFF PRI53 Priority of interrupt 53 0 8 read-write NVICIP54 Interrupt Priority Register n 0x336 8 read-write 0 0xFF PRI54 Priority of interrupt 54 0 8 read-write NVICIP55 Interrupt Priority Register n 0x337 8 read-write 0 0xFF PRI55 Priority of interrupt 55 0 8 read-write NVICIP56 Interrupt Priority Register n 0x338 8 read-write 0 0xFF PRI56 Priority of interrupt 56 0 8 read-write NVICIP57 Interrupt Priority Register n 0x339 8 read-write 0 0xFF PRI57 Priority of interrupt 57 0 8 read-write NVICIP58 Interrupt Priority Register n 0x33A 8 read-write 0 0xFF PRI58 Priority of interrupt 58 0 8 read-write NVICIP59 Interrupt Priority Register n 0x33B 8 read-write 0 0xFF PRI59 Priority of interrupt 59 0 8 read-write NVICIP60 Interrupt Priority Register n 0x33C 8 read-write 0 0xFF PRI60 Priority of interrupt 60 0 8 read-write NVICIP61 Interrupt Priority Register n 0x33D 8 read-write 0 0xFF PRI61 Priority of interrupt 61 0 8 read-write NVICIP62 Interrupt Priority Register n 0x33E 8 read-write 0 0xFF PRI62 Priority of interrupt 62 0 8 read-write NVICIP63 Interrupt Priority Register n 0x33F 8 read-write 0 0xFF PRI63 Priority of interrupt 63 0 8 read-write NVICIP64 Interrupt Priority Register n 0x340 8 read-write 0 0xFF PRI64 Priority of interrupt 64 0 8 read-write NVICIP65 Interrupt Priority Register n 0x341 8 read-write 0 0xFF PRI65 Priority of interrupt 65 0 8 read-write NVICIP66 Interrupt Priority Register n 0x342 8 read-write 0 0xFF PRI66 Priority of interrupt 66 0 8 read-write NVICIP67 Interrupt Priority Register n 0x343 8 read-write 0 0xFF PRI67 Priority of interrupt 67 0 8 read-write NVICIP68 Interrupt Priority Register n 0x344 8 read-write 0 0xFF PRI68 Priority of interrupt 68 0 8 read-write NVICIP69 Interrupt Priority Register n 0x345 8 read-write 0 0xFF PRI69 Priority of interrupt 69 0 8 read-write NVICIP70 Interrupt Priority Register n 0x346 8 read-write 0 0xFF PRI70 Priority of interrupt 70 0 8 read-write NVICIP71 Interrupt Priority Register n 0x347 8 read-write 0 0xFF PRI71 Priority of interrupt 71 0 8 read-write NVICIP72 Interrupt Priority Register n 0x348 8 read-write 0 0xFF PRI72 Priority of interrupt 72 0 8 read-write NVICIP73 Interrupt Priority Register n 0x349 8 read-write 0 0xFF PRI73 Priority of interrupt 73 0 8 read-write NVICIP74 Interrupt Priority Register n 0x34A 8 read-write 0 0xFF PRI74 Priority of interrupt 74 0 8 read-write NVICIP75 Interrupt Priority Register n 0x34B 8 read-write 0 0xFF PRI75 Priority of interrupt 75 0 8 read-write NVICIP76 Interrupt Priority Register n 0x34C 8 read-write 0 0xFF PRI76 Priority of interrupt 76 0 8 read-write NVICIP77 Interrupt Priority Register n 0x34D 8 read-write 0 0xFF PRI77 Priority of interrupt 77 0 8 read-write NVICIP78 Interrupt Priority Register n 0x34E 8 read-write 0 0xFF PRI78 Priority of interrupt 78 0 8 read-write NVICIP79 Interrupt Priority Register n 0x34F 8 read-write 0 0xFF PRI79 Priority of interrupt 79 0 8 read-write NVICIP80 Interrupt Priority Register n 0x350 8 read-write 0 0xFF PRI80 Priority of interrupt 80 0 8 read-write NVICIP81 Interrupt Priority Register n 0x351 8 read-write 0 0xFF PRI81 Priority of interrupt 81 0 8 read-write NVICIP82 Interrupt Priority Register n 0x352 8 read-write 0 0xFF PRI82 Priority of interrupt 82 0 8 read-write NVICIP83 Interrupt Priority Register n 0x353 8 read-write 0 0xFF PRI83 Priority of interrupt 83 0 8 read-write NVICIP84 Interrupt Priority Register n 0x354 8 read-write 0 0xFF PRI84 Priority of interrupt 84 0 8 read-write NVICIP85 Interrupt Priority Register n 0x355 8 read-write 0 0xFF PRI85 Priority of interrupt 85 0 8 read-write NVICIP86 Interrupt Priority Register n 0x356 8 read-write 0 0xFF PRI86 Priority of interrupt 86 0 8 read-write NVICIP87 Interrupt Priority Register n 0x357 8 read-write 0 0xFF PRI87 Priority of interrupt 87 0 8 read-write NVICIP88 Interrupt Priority Register n 0x358 8 read-write 0 0xFF PRI88 Priority of interrupt 88 0 8 read-write NVICIP89 Interrupt Priority Register n 0x359 8 read-write 0 0xFF PRI89 Priority of interrupt 89 0 8 read-write NVICIP90 Interrupt Priority Register n 0x35A 8 read-write 0 0xFF PRI90 Priority of interrupt 90 0 8 read-write NVICIP91 Interrupt Priority Register n 0x35B 8 read-write 0 0xFF PRI91 Priority of interrupt 91 0 8 read-write NVICIP92 Interrupt Priority Register n 0x35C 8 read-write 0 0xFF PRI92 Priority of interrupt 92 0 8 read-write NVICIP93 Interrupt Priority Register n 0x35D 8 read-write 0 0xFF PRI93 Priority of interrupt 93 0 8 read-write NVICIP94 Interrupt Priority Register n 0x35E 8 read-write 0 0xFF PRI94 Priority of interrupt 94 0 8 read-write NVICIP95 Interrupt Priority Register n 0x35F 8 read-write 0 0xFF PRI95 Priority of interrupt 95 0 8 read-write NVICIP96 Interrupt Priority Register n 0x360 8 read-write 0 0xFF PRI96 Priority of interrupt 96 0 8 read-write NVICIP97 Interrupt Priority Register n 0x361 8 read-write 0 0xFF PRI97 Priority of interrupt 97 0 8 read-write NVICIP98 Interrupt Priority Register n 0x362 8 read-write 0 0xFF PRI98 Priority of interrupt 98 0 8 read-write NVICIP99 Interrupt Priority Register n 0x363 8 read-write 0 0xFF PRI99 Priority of interrupt 99 0 8 read-write NVICIP100 Interrupt Priority Register n 0x364 8 read-write 0 0xFF PRI100 Priority of interrupt 100 0 8 read-write NVICIP101 Interrupt Priority Register n 0x365 8 read-write 0 0xFF PRI101 Priority of interrupt 101 0 8 read-write NVICIP102 Interrupt Priority Register n 0x366 8 read-write 0 0xFF PRI102 Priority of interrupt 102 0 8 read-write NVICIP103 Interrupt Priority Register n 0x367 8 read-write 0 0xFF PRI103 Priority of interrupt 103 0 8 read-write NVICIP104 Interrupt Priority Register n 0x368 8 read-write 0 0xFF PRI104 Priority of interrupt 104 0 8 read-write NVICIP105 Interrupt Priority Register n 0x369 8 read-write 0 0xFF PRI105 Priority of interrupt 105 0 8 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write 0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write ETM Embedded Trace Macrocell Registers ETM ETM 0xE0041000 0 0x1000 registers CR Main Control Register 0 32 read-write 0x411 0xFFFFFFFF ETMPD ETM power down. This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, writes to some registers and fields might be ignored. 0 1 read-write PS Port size. The ETM-M4 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001. 4 3 read-write SP Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace resumes without corruption once the FIFO has drained, if overflow does occur. An ETM reset sets this bit to 0. 7 1 read-write BO Branch output. When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed. When this bit is set to 1, more trace data is generated, and this may affect the performance of the trace system. Information about the execution of a branch is traced regardless of the state of this bit. An ETM reset sets this bit to 0. 8 1 read-write DRC Debug request control. When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state. An ETM reset sets this bit to 0. 9 1 read-write ETMP ETM programming. This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while this bit is set to 1. On an ETM reset this bit is set to b1. 10 1 read-write ETMPS ETM port selection. This bit can be used to control other trace components in an implementation. This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM. An ETM reset sets this bit to 0. 11 1 read-write ETMPS_0 ETMEN is LOW. 0 ETMPS_1 ETMEN is HIGH. 0x1 PM2 This bit is implemented but has no function. An ETM reset sets this bit to 0. 13 1 read-write PM These bits are implemented but have no function. An ETM reset sets these bits to 0. 16 2 read-write PS3 This bit is implemented but has no function. An ETM reset sets this bit to 0. 21 1 read-write TE When set, this bit enables timestamping. An ETM reset sets this bit to 0. 28 1 read-write CCR Configuration Code Register 0x4 32 read-only 0x8C802000 0xFFFFFFFF NumberOfAddressComparatorPairs Number of address comparator pairs. The value of these bits is b0000, indicating that address comparator pairs are not implemented. 0 4 read-only NDVC Number of data value comparators. The value of these bits is b0000, indicating that data value comparators are not implemented. 4 4 read-only NMMD Number of memory map decoders. The value of these bits is b00000, indicating that memory map decoder inputs are not implemented. 8 5 read-only NC Number of counters. The value of these bits is b001, indicating that one counter is implemented. 13 3 read-only SP Sequencer present. The value of this bit is 0, indicating that the sequencer is not implemented. 16 1 read-only NEI Number of external inputs. The value of these bits is between b000 and b010, indicating the number of external inputs, from 0 to 2, implemented in the system. 17 3 read-only NEO Number of external outputs. The value of these bits is b000, indicating that no external outputs are supported. 20 3 read-only FFLP FIFOFULL logic present. The value of this bit is 1, indicating that FIFOFULL logic is present in the ETM. To use FIFOFULL the system must also support the function, as indicated by bit [8] of ETMSCR. 23 1 read-only NCIDC Number of Context ID comparators. The value of these bits is b00, indicating that Context ID comparators are not implemented. 24 2 read-only TSSBP Trace start/stop block present. The value of this bit is 1, indicating that the Trace start/stop block is present. 26 1 read-only CMA Coprocessor and memory access. The value of this bit is 1, indicating that memory-mapped access to registers is supported. 27 1 read-only ETMIDRP The value of this bit is 1, indicating that the ETMIDR, register 0x79, is present and defines the ETM architecture version in use. 31 1 read-only TRIGGER Trigger Event Register 0x8 32 read-write 0 0xFFFE0000 TriggerEvent Trigger event 0 17 read-write SR ETM Status Register 0x10 32 read-write 0 0xFFFFFFF0 UOF Untraced overflow flag. If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either: - trace is restarted - the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1. Note: Setting or clearing the ETM programming bit does not cause this bit to be cleared to 0. 0 1 read-only Progbit ETM programming bit value (Progbit). The current effective value of the ETM Programming bit (ETM Control Register bit [10]). Tou must wait for this bit to go to 1 before you start to program the ETM. 1 1 read-only Status Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match. 2 1 read-write Trigger Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is next programmed. 3 1 read-write SCR System Configuration Register 0x14 32 read-only 0x20D09 0xFFFFFFFF MaximumPortSize Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is b001. 0 3 read-only FIFOFULLsupported FIFOFULL supported. The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR. 8 1 read-only MaximumPortSize3 Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0. This has no effect on the TPIU trace port. 9 1 read-only PortSizeSupported Port size supported. This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port. 10 1 read-only PortModeSupported Port mode supported. This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port. 11 1 read-only N These bits give the number of supported processors minus 1. The value of these bits is b000, indicating that there is only one processor connected. 12 3 read-only NoFetchComparisons No Fetch comparisons. The value of this bit is 1, indicating that fetch comparisons are not implemented. 17 1 read-only EEVR Trace Enable Event Register 0x20 32 read-write 0 0 TraceEnableEvent Trace Enable event. 0 17 read-write TECR1 Trace Enable Control 1 Register 0x24 32 read-write 0 0xFDFFFFFF TraceControlEnable Trace start/stop enable. The trace start/stop resource, resource 0x5F, is unaffected by the value of this bit. 25 1 read-write TraceControlEnable_0 Tracing is unaffected by the trace start/stop logic. 0 TraceControlEnable_1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. 0x1 FFLR FIFOFULL Level Register 0x28 32 read-write 0 0 FIFOFullLevel FIFO full level. The number of bytes left in FIFO, below which the FIFOFULL or SupressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO. 0 8 read-write CNTRLDVR1 Free-running counter reload value 0x140 32 read-write 0 0 IntitialCount Initial count. 0 16 read-write SYNCFR Synchronization Frequency Register 0x1E0 32 read-only 0x400 0xFFFFFFFF SyncFrequency Synchronization frequency. Default value is 1024. 0 12 read-only IDR ID Register 0x1E4 32 read-only 0x4114F250 0xFFFFFFFF ImplementationRevision Implementation revision. The value of these bits is b0000, indicating implementation revision, 0. 0 4 read-only MinorETMarchitectureVersion Minor ETM architecture version. The value of these bits is 0b0101, indicating minor architecture version number 5. 4 4 read-only MajorETMarchitectureVersion Major ETM architecture version. The value of these bits is 0b0010, indicating major architecture version number 3, ETMv3. 8 4 read-only ProcessorFamily Processor family. The value of these bits is 0b1111, indicating that the processor family is not identified in this register. 12 4 read-only LoadPCfirst Load PC first. The value of this bit is 0, indicating that data tracing is not supported. 16 1 read-only ThumbInstructionTracing 32-bit Thumb instruction tracing. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction. 18 1 read-only ThumbInstructionTracing_0 A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions. 0 ThumbInstructionTracing_1 A 32-bit Thimb instruction is traced as a single instruction. 0x1 SecurityExtensionSupport Security Extensions support. The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times. 19 1 read-only SecurityExtensionSupport_0 The ETM behaves as if the processor is in Secure state at all times. 0 SecurityExtensionSupport_1 The ARM architecture Security Extensions are implemented by the processor. 0x1 BranchPacketEncoding Branch packet encoding. The value of this bit is 1, indicating that alternative branch packet encoding is implemented. 20 1 read-only BranchPacketEncoding_0 The ETM implements the original branch packet encoding. 0 BranchPacketEncoding_1 The ETM implements the alternative branch packet encoding. 0x1 ImplementorCode Implementor code. These bits identify ARM as the implementor of the processor. The value of these bits is 01000001. 24 8 read-only CCER Configuration Code Extension Register 0x1E8 32 read-only 0x18541800 0xFFFFFFFF ExtendedExternalInputSelectors Extended external input selectors. The value of these bits is 0, indicating that extended external input selectors are not implemented. 0 3 read-only ExtendedExternalInputBus Extended external input bus. The value of these bits is 0, indicating that the extended external input bus is not implemented. 3 8 read-only ReadableRegisters Readable registers. The value of this bit is 1, indicating that all registers are readable. 11 1 read-only DataAddressComparisons Data address comparisons. The value of this bit is 1, indicating that data address comparisons are not supported. 12 1 read-only InstrumentationResources Instrumentation resources. The value of these bits is 0b000, indicating that no Instrumentation resources are supported. 13 3 read-only EmbeddedICEwatchpointInputs EmbeddedICE watchpoint inputs. The value of these bits is 0b0100, indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT. 16 4 read-only TraceStartStopBlockUsesEmbeddedICEwatchpointInputs Trace Start/Stop block uses EmbeddedICE watchpoint inputs. The value of this bit is 1, indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs. 20 1 read-only EmbeddedICEbehaviorControlImplemented EmbeddedICE behavior control implemented. The value of this bit is 0, indicating that the ETMEIBCR is not implemented. 21 1 read-only TimestampingImplemented Timestamping implemented. This bit is set to 1, indicating that timestamping is implemented. 22 1 read-only ReducedFunctionCounter Reduced function counter. Set to 1 to indicate that Counter 1 is a reduced function counter. 27 1 read-only TimestampEncoding Timestamp encoding. Set to 1 to indicate that the timestamp is encoded as a natural binary number. 28 1 read-only TimestampSize Timestamp size. Set to 0 to indicate a size of 48 bits. 29 1 read-only TESSEICR TraceEnable Start/Stop EmbeddedICE Control Register 0x1F0 32 read-write 0 0xFFF0FFF0 StartResourceSelection Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4. 0 4 read-write StopResourceSelection Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4. 16 4 read-write TSEVR Timestamp Event Register 0x1F8 32 read-write 0 0 TimestampEvent Timestamp event. 0 12 read-write TRACEIDR CoreSight Trace ID Register 0x200 32 read-write 0 0xFFFFFFFF TraceID Trace ID to output onto the trace bus. On an ETM reset this field is cleared to 0x00. 0 7 read-write IDR2 ETM ID Register 2 0x208 32 read-only 0 0xFFFFFFFF PDSR Device Power-Down Status Register 0x314 32 read-only 0x1 0xFFFFFFFF ETMpoweredup The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is always 1, indicating that the ETM Trace Registers can be accessed. 0 1 read-only _ITMISCIN Integration Test Miscelaneous Inputs Register 0xEE0 32 read-only 0 0xFFFFFFE0 EXTIN A read of these bits returns the value of the EXTIN[1:0] input pins. 0 2 read-only COREHALT A read of this bit returns the value of the COREHALT input pin. 4 1 read-only _ITTRIGOUT Integration Test Trigger Out Register 0xEE8 32 read-write 0 0xFFFFFFFE TRIGGER A write to this bit sets the TRIGGER output. 0 1 write-only _ITATBCTR2 ETM Integration Test ATB Control 2 Register 0xEF0 32 read-only 0 0xFFFFFFFE ATREADY A read of this bit returns the value of the ETM ATREADY input. 0 1 read-only _ITATBCTR0 ETM Integration Test ATB Control 0 Register 0xEF8 32 read-write 0 0xFFFFFFFE ATVALID A write to this bit sets the value of the ETM ATVALID output. 0 1 write-only ITCTRL Integration Mode Control Register 0xF00 32 read-write 0 0xFFFFFFFF Mode Enable integration mode. When this bit is set to 1, the device enters integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0. 0 1 read-write CLAIMSET Claim Tag Set Register 0xFA0 32 read-write 0 0 CLAIMSET A bit programmable register bank which sets the Claim Tag Value. Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations. 0 4 read-write CLAIMCLR Claim Tag Clear Register 0xFA4 32 read-write 0 0 CLAIMCLR A bit programmable register bank that is zero at reset. Write 1 to clear the bit in the claim tag. On reads, returns the current setting of the claim tag. 0 4 read-write LAR Lock Access Register 0xFB0 32 read-write 0 0 WriteAccessCode Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. 0 32 read-write LSR Lock Status Register 0xFB4 32 read-only 0x1 0x5 IMP Lock mechanism is implemented. This bit always reads 1. 0 1 read-only STATUS Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. 1 1 read-only STATUS_0 Access permitted. 0 STATUS_1 Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. 0x1 s8BIT Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. 2 1 read-only AUTHSTATUS Authentication Status Register 0xFB8 32 read-only 0 0xFFFFFF00 NSID Reads as b00, Non-secure invasive debug not supported by the ETM. 0 2 read-only NSNID Permission for Non-secure non-invasive debug. 2 2 read-only NSNID_2 Non-secure non-invasive debug disabled 0x2 NSNID_3 Non-secure non-invasive debug enabled 0x3 SID Reads as b00, Secure invasive debug not supported by the ETM. 4 2 read-only SNID Permission for Secure non-invasive debug. 6 2 read-only DEVTYPE CoreSight Device Type Register 0xFCC 32 read-only 0x13 0xFFFFFFFF MajorType Major Type and Class 0 4 read-only MajorType_3 Trace source 0x3 SubType Sub Type 4 4 read-only SubType_1 Processor trace 0x1 PIDR4 Peripheral Identification Register 4 0xFD0 32 read-only 0x4 0xFFFFFFFF JEP106 JEP106 continuation code. 0 4 read-only c4KB 4KB Count 4 4 read-only PIDR5 Peripheral Identification Register 5 0xFD4 32 read-only 0 0xFFFFFFFF PIDR6 Peripheral Identification Register 6 0xFD8 32 read-only 0 0xFFFFFFFF PIDR7 Peripheral Identification Register 7 0xFDC 32 read-only 0 0xFFFFFFFF PIDR0 Peripheral Identification Register 0 0xFE0 32 read-only 0x25 0xFFFFFFFF PartNumber Part Number [7:0] 0 8 read-only PIDR1 Peripheral Identification Register 1 0xFE4 32 read-only 0xB9 0xFFFFFFFF PartNumber Part Number [11:8] 0 4 read-only JEP106_identity_code JEP106 identity code [3:0] 4 4 read-only PIDR2 Peripheral Identification Register 2 0xFE8 32 read-only 0xB 0xFFFFFFFF JEP106_identity_code JEP106 identity code [6:4] 0 3 read-only Revision Revision 4 4 read-only PIDR3 Peripheral Identification Register 3 0xFEC 32 read-only 0 0xFFFFFFFF CustomerModified Customer Modified. 0 4 read-only RevAnd RevAnd 4 4 read-only CIDR0 Component Identification Register 0 0xFF0 32 read-only 0xD 0xFFFFFFFF Preamble Preamble 0 8 read-only CIDR1 Component Identification Register 1 0xFF4 32 read-only 0x90 0xFFFFFFFF Preamble Preamble 0 4 read-only ComponentClass Component class 4 4 read-only ComponentClass_1 ROM table. 0x1 ComponentClass_9 CoreSight component. 0x9 ComponentClass_15 PrimeCell of system component with no standardized register layout, for backward compatibility. 0xF CIDR2 Component Identification Register 2 0xFF8 32 read-only 0x5 0xFFFFFFFF Preamble Preamble 0 8 read-only CIDR3 Component Identification Register 3 0xFFC 32 read-only 0xB1 0xFFFFFFFF Preamble Preamble 0 8 read-only